adds terminator to char str in wrap_puts

fixes ROM location
adapts riscv-vp rom to implementation
2025-10-24 10:05:55 +02:00 · 2025-09-15 21:02:23 +02:00 · 2025-09-15 20:52:50 +02:00 · 2025-09-14 14:55:23 +02:00 · 2025-09-12 08:32:47 +02:00 · 2025-08-22 15:34:32 +02:00
90 changed files with 938 additions and 1939 deletions
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -0,0 +1,46 @@
+cmake_minimum_required(VERSION 3.21)
+include(CheckLinkerFlag)
+
+project(mnrs-bsp LANGUAGES ASM C)
+set(LINKER_SCRIPT "${CMAKE_CURRENT_SOURCE_DIR}/env/${BOARD}/link.lds"
+    CACHE FILEPATH "Linker script to use for BSP linking")
+set(BSP_STARTUP "${CMAKE_CURRENT_SOURCE_DIR}/env/start.S"
+    CACHE FILEPATH "Path to the BSP startup assembly file")
+set(BSP_TRAP_HANDLER "${CMAKE_CURRENT_SOURCE_DIR}/env/entry.S"
+    CACHE FILEPATH "Assembly file implementing trap handler")
+if(NOT DEFINED BOARD)
+message(FATAL_ERROR "No Board selected")
+endif()
+add_compile_definitions("BOARD_${BOARD}")
+
+set(TESTBENCHES "rtl" "TGCP")
+list(FIND TESTBENCHES ${BOARD} _index)
+if(NOT _index EQUAL -1)
+    set(BOARD "testbench/${BOARD}")
+endif()
+
+option(SEMIHOSTING "Enable semihosting support" OFF)
+if(SEMIHOSTING)
+    add_compile_definitions(SEMIHOSTING)
+endif()
+
+add_library(startup STATIC ${BSP_STARTUP} ${BSP_TRAP_HANDLER})
+target_include_directories(startup PUBLIC env include)
+
+add_subdirectory(libwrap)
+
+add_library(bsp STATIC env/${BOARD}/init.c)
+target_link_libraries(bsp PUBLIC startup wrap)
+target_include_directories(bsp PUBLIC env/${BOARD})
+
+check_linker_flag(C "LINKER:--no-warn-rwx-segments" HAS_NO_WARN_RWX_SEGMENTS)
+
+if(HAS_NO_WARN_RWX_SEGMENTS)
+    target_link_options(bsp INTERFACE LINKER:--no-warn-rwx-segments)
+endif()
+target_link_options(bsp INTERFACE LINKER: -nostartfiles -T ${LINKER_SCRIPT})
+
+if(SEMIHOSTING)
+    target_include_directories(bsp INTERFACE include)
+    target_sources(bsp INTERFACE env/semihosting.c env/trap.c)
+endif()
--- a/cmake/rv32imc.cmake
+++ b/cmake/rv32imc.cmake
@@ -0,0 +1,59 @@
+# Look for GCC in path
+# https://xpack.github.io/riscv-none-embed-gcc/
+FIND_FILE( RISCV_XPACK_GCC_COMPILER_EXE "riscv-none-embed-gcc.exe" PATHS ENV INCLUDE)
+FIND_FILE( RISCV_XPACK_GCC_COMPILER "riscv-none-embed-gcc" PATHS ENV INCLUDE)
+# New versions of xpack
+FIND_FILE( RISCV_XPACK_NEW_GCC_COMPILER_EXE "riscv-none-elf-gcc.exe" PATHS ENV INCLUDE)
+FIND_FILE( RISCV_XPACK_NEW_GCC_COMPILER "riscv-none-elf-gcc" PATHS ENV INCLUDE)
+# Look for RISC-V github GCC
+# https://github.com/riscv/riscv-gnu-toolchain
+FIND_FILE( RISCV_XPACK_GCC_COMPILER_EXT "riscv64-unknown-elf-gcc.exe" PATHS ENV INCLUDE)
+FIND_FILE( RISCV_XPACK_GCC_COMPILER "riscv64-unknown-elf-gcc" PATHS ENV INCLUDE)
+
+# Select which is found
+if (EXISTS ${RISCV_XPACK_NEW_GCC_COMPILER})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_NEW_GCC_COMPILER})
+elseif (EXISTS ${RISCV_XPACK_GCC_NEW_COMPILER_EXE})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_NEW_GCC_COMPILER_EXE})
+elseif (EXISTS ${RISCV_XPACK_GCC_COMPILER})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_GCC_COMPILER})
+elseif (EXISTS ${RISCV_XPACK_GCC_COMPILER_EXE})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_GCC_COMPILER_EXE})
+elseif (EXISTS ${RISCV_GITHUB_GCC_COMPILER})
+set( RISCV_GCC_COMPILER ${RISCV_GITHUB_GCC_COMPILER})
+elseif (EXISTS ${RISCV_GITHUB_GCC_COMPILER_EXE})
+set( RISCV_GCC_COMPILER ${RISCV_GITHUB_GCC_COMPILER_EXE})
+else()
+message(FATAL_ERROR "RISC-V GCC not found. ${RISCV_GITHUB_GCC_COMPILER} ${RISCV_XPACK_GCC_COMPILER} ${RISCV_GITHUB_GCC_COMPILER_EXE} ${RISCV_XPACK_GCC_COMPILER_EXE}")
+endif()
+
+get_filename_component(RISCV_TOOLCHAIN_BIN_PATH ${RISCV_GCC_COMPILER} DIRECTORY)
+get_filename_component(RISCV_TOOLCHAIN_BIN_GCC ${RISCV_GCC_COMPILER} NAME_WE)
+get_filename_component(RISCV_TOOLCHAIN_BIN_EXT ${RISCV_GCC_COMPILER} EXT)
+
+STRING(REGEX REPLACE "\-gcc" "-" CROSS_COMPILE ${RISCV_TOOLCHAIN_BIN_GCC})
+
+# The Generic system name is used for embedded targets (targets without OS)
+set(CMAKE_SYSTEM_NAME Generic )
+set(CMAKE_EXECUTABLE_SUFFIX_C ".elf")
+set(RISCV_ARCH rv32imc_zicsr_zifencei )
+set(RISCV_ABI ilp32)
+
+
+set(CMAKE_ASM_COMPILER {CROSS_COMPILE}gcc )
+set(CMAKE_AR ${CROSS_COMPILE}ar)
+set(CMAKE_ASM_COMPILER ${CROSS_COMPILE}gcc)
+set(CMAKE_C_COMPILER ${CROSS_COMPILE}gcc)
+set(CMAKE_CXX_COMPILER ${CROSS_COMPILE}g++)
+
+set( CMAKE_OBJCOPY      ${RISCV_TOOLCHAIN_BIN_PATH}/${CROSS_COMPILE}objcopy
+     CACHE FILEPATH "The toolchain objcopy command " FORCE )
+
+set( CMAKE_OBJDUMP      ${RISCV_TOOLCHAIN_BIN_PATH}/${CROSS_COMPILE}objdump
+     CACHE FILEPATH "The toolchain objdump command " FORCE )
+
+set( CMAKE_C_FLAGS "-march=${RISCV_ARCH} -mabi=${RISCV_ABI} -mcmodel=medany" )
+
+set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
+set( CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
+set( CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
--- a/cmake/rv64gc.cmake
+++ b/cmake/rv64gc.cmake
@@ -0,0 +1,59 @@
+# Look for GCC in path
+# https://xpack.github.io/riscv-none-embed-gcc/
+FIND_FILE( RISCV_XPACK_GCC_COMPILER_EXE "riscv-none-embed-gcc.exe" PATHS ENV INCLUDE)
+FIND_FILE( RISCV_XPACK_GCC_COMPILER "riscv-none-embed-gcc" PATHS ENV INCLUDE)
+# New versions of xpack
+FIND_FILE( RISCV_XPACK_NEW_GCC_COMPILER_EXE "riscv-none-elf-gcc.exe" PATHS ENV INCLUDE)
+FIND_FILE( RISCV_XPACK_NEW_GCC_COMPILER "riscv-none-elf-gcc" PATHS ENV INCLUDE)
+# Look for RISC-V github GCC
+# https://github.com/riscv/riscv-gnu-toolchain
+FIND_FILE( RISCV_XPACK_GCC_COMPILER_EXT "riscv64-unknown-elf-gcc.exe" PATHS ENV INCLUDE)
+FIND_FILE( RISCV_XPACK_GCC_COMPILER "riscv64-unknown-elf-gcc" PATHS ENV INCLUDE)
+
+# Select which is found
+if (EXISTS ${RISCV_XPACK_NEW_GCC_COMPILER})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_NEW_GCC_COMPILER})
+elseif (EXISTS ${RISCV_XPACK_GCC_NEW_COMPILER_EXE})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_NEW_GCC_COMPILER_EXE})
+elseif (EXISTS ${RISCV_XPACK_GCC_COMPILER})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_GCC_COMPILER})
+elseif (EXISTS ${RISCV_XPACK_GCC_COMPILER_EXE})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_GCC_COMPILER_EXE})
+elseif (EXISTS ${RISCV_GITHUB_GCC_COMPILER})
+set( RISCV_GCC_COMPILER ${RISCV_GITHUB_GCC_COMPILER})
+elseif (EXISTS ${RISCV_GITHUB_GCC_COMPILER_EXE})
+set( RISCV_GCC_COMPILER ${RISCV_GITHUB_GCC_COMPILER_EXE})
+else()
+message(FATAL_ERROR "RISC-V GCC not found. ${RISCV_GITHUB_GCC_COMPILER} ${RISCV_XPACK_GCC_COMPILER} ${RISCV_GITHUB_GCC_COMPILER_EXE} ${RISCV_XPACK_GCC_COMPILER_EXE}")
+endif()
+
+get_filename_component(RISCV_TOOLCHAIN_BIN_PATH ${RISCV_GCC_COMPILER} DIRECTORY)
+get_filename_component(RISCV_TOOLCHAIN_BIN_GCC ${RISCV_GCC_COMPILER} NAME_WE)
+get_filename_component(RISCV_TOOLCHAIN_BIN_EXT ${RISCV_GCC_COMPILER} EXT)
+
+STRING(REGEX REPLACE "\-gcc" "-" CROSS_COMPILE ${RISCV_TOOLCHAIN_BIN_GCC})
+
+# The Generic system name is used for embedded targets (targets without OS)
+set(CMAKE_SYSTEM_NAME Generic )
+set(CMAKE_EXECUTABLE_SUFFIX_C ".elf")
+set(RISCV_ARCH rv64gc )
+set(RISCV_ABI lp64d)
+
+
+set(CMAKE_ASM_COMPILER {CROSS_COMPILE}gcc )
+set(CMAKE_AR ${CROSS_COMPILE}ar)
+set(CMAKE_ASM_COMPILER ${CROSS_COMPILE}gcc)
+set(CMAKE_C_COMPILER ${CROSS_COMPILE}gcc)
+set(CMAKE_CXX_COMPILER ${CROSS_COMPILE}g++)
+
+set( CMAKE_OBJCOPY      ${RISCV_TOOLCHAIN_BIN_PATH}/${CROSS_COMPILE}objcopy
+     CACHE FILEPATH "The toolchain objcopy command " FORCE )
+
+set( CMAKE_OBJDUMP      ${RISCV_TOOLCHAIN_BIN_PATH}/${CROSS_COMPILE}objdump
+     CACHE FILEPATH "The toolchain objdump command " FORCE )
+
+set( CMAKE_C_FLAGS "-march=${RISCV_ARCH} -mabi=${RISCV_ABI} -mcmodel=medany" )
+
+set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
+set( CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
+set( CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
--- a/drivers/fe300prci/fe300prci_driver.c
+++ b/drivers/fe300prci/fe300prci_driver.c
@@ -1,252 +0,0 @@
-// See LICENSE file for license details
-
-#include "platform.h"
-
-#ifdef PRCI_CTRL_ADDR
-#include "fe300prci/fe300prci_driver.h"
-#include <unistd.h>
-
-#define rdmcycle(x)  {				       \
-    uint32_t lo, hi, hi2;			       \
-    __asm__ __volatile__ ("1:\n\t"		       \
-			  "csrr %0, mcycleh\n\t"       \
-			  "csrr %1, mcycle\n\t"	       \
-			  "csrr %2, mcycleh\n\t"		\
-			  "bne  %0, %2, 1b\n\t"			\
-			  : "=r" (hi), "=r" (lo), "=r" (hi2)) ;	\
-    *(x) = lo | ((uint64_t) hi << 32); 				\
-  }
-
-uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq)
-{
-
-  uint32_t start_mtime = CLINT_REG(CLINT_MTIME);
-  uint32_t end_mtime = start_mtime + mtime_ticks + 1;
-
-  // Make sure we won't get rollover.
-  while (end_mtime < start_mtime){
-    start_mtime = CLINT_REG(CLINT_MTIME);
-    end_mtime = start_mtime + mtime_ticks + 1;
-  }
-
-  // Don't start measuring until mtime edge.
-  uint32_t tmp = start_mtime;
-  do {
-    start_mtime = CLINT_REG(CLINT_MTIME);
-  } while (start_mtime == tmp);
-  
-  uint64_t start_mcycle;
-  rdmcycle(&start_mcycle);
-  
-  while (CLINT_REG(CLINT_MTIME) < end_mtime) ;
-  
-  uint64_t end_mcycle;
-  rdmcycle(&end_mcycle);
-  uint32_t difference = (uint32_t) (end_mcycle - start_mcycle);
-
-  uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks;
-  return (uint32_t) freq & 0xFFFFFFFF;
-  
-}
- 
-
-void PRCI_use_hfrosc(int div, int trim)
-{
-  // Make sure the HFROSC is running at its default setting
-  // It is OK to change this even if we are running off of it.
-  
-  PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
-
-  while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0);
-  
-  PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
-}
-
-void PRCI_use_pll(int refsel, int bypass,
-			 int r, int f, int q, int finaldiv,
-			 int hfroscdiv, int hfrosctrim)
-{
-  // Ensure that we aren't running off the PLL before we mess with it.
-  if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
-    // Make sure the HFROSC is running at its default setting
-    PRCI_use_hfrosc(4, 16);
-  }
-  
-  // Set PLL Source to be HFXOSC if desired.
-  uint32_t config_value = 0;
-
-  config_value |= PLL_REFSEL(refsel);
-  
-  if (bypass) {
-    // Bypass
-    config_value |= PLL_BYPASS(1);
-
-    PRCI_REG(PRCI_PLLCFG) = config_value;
-
-    // If we don't have an HFXTAL, this doesn't really matter.
-    // Set our Final output divide to divide-by-1:
-    PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
-  } else {
-  
-    // To overclock, use the hfrosc
-    if (hfrosctrim >= 0 && hfroscdiv >= 0) {
-      PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
-    }
-    
-    // Set DIV Settings for PLL
-    
-    // (Legal values of f_REF are 6-48MHz)
-
-    // Set DIVR to divide-by-2 to get 8MHz frequency
-    // (legal values of f_R are 6-12 MHz)
-
-    config_value |= PLL_BYPASS(1);
-    config_value |= PLL_R(r);
-
-    // Set DIVF to get 512Mhz frequncy
-    // There is an implied multiply-by-2, 16Mhz.
-    // So need to write 32-1
-    // (legal values of f_F are 384-768 MHz)
-    config_value |= PLL_F(f);
-
-    // Set DIVQ to divide-by-2 to get 256 MHz frequency
-    // (legal values of f_Q are 50-400Mhz)
-    config_value |= PLL_Q(q);
-
-    // Set our Final output divide to divide-by-1:
-    if (finaldiv == 1){
-      PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
-    } else {
-      PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1));
-    }
-
-    PRCI_REG(PRCI_PLLCFG) = config_value;
-
-    // Un-Bypass the PLL.
-    PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
-
-    // Wait for PLL Lock
-    // Note that the Lock signal can be glitchy.
-    // Need to wait 100 us
-    // RTC is running at 32kHz.
-    // So wait 4 ticks of RTC.
-    uint32_t now = CLINT_REG(CLINT_MTIME);
-    while (CLINT_REG(CLINT_MTIME) - now < 4) ;
-    
-    // Now it is safe to check for PLL Lock
-    while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0);
-
-  }
-
-  // Switch over to PLL Clock source
-  PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
-
-  // If we're running off HFXOSC, turn off the HFROSC to
-  // save power.
-  if (refsel) {
-    PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);
-  }
-  
-}
-
-void PRCI_use_default_clocks()
-{
-  // Turn off the LFROSC
-  AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
-
-  // Use HFROSC
-  PRCI_use_hfrosc(4, 16);
-}
-
-void PRCI_use_hfxosc(uint32_t finaldiv)
-{
-  
-  PRCI_use_pll(1, // Use HFXTAL
-	       1, // Bypass = 1
-	       0, // PLL settings don't matter
-	       0, // PLL settings don't matter
-	       0, // PLL settings don't matter
-	       finaldiv,
-	       -1,
-	       -1);
-}
-
-// This is a generic function, which
-// doesn't span the entire range of HFROSC settings.
-// It only adjusts the trim, which can span a hundred MHz or so.
-// This function does not check the legality of the PLL settings
-// at all, and it is quite possible to configure invalid PLL settings
-// this way.
-// It returns the actual measured CPU frequency.
-
-uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target )
-{
-
-  uint32_t hfrosctrim = 0;
-  uint32_t hfroscdiv = 4;
-  uint32_t prev_trim = 0;
-
-  // In this function we use PLL settings which
-  // will give us a 32x multiplier from the output
-  // of the HFROSC source to the output of the
-  // PLL. We first measure our HFROSC to get the
-  // right trim, then finally use it as the PLL source.
-  // We should really check here that the f_cpu
-  // requested is something in the limit of the PLL. For
-  // now that is up to the user.
-
-  // This will undershoot for frequencies not divisible by 16.
-  uint32_t desired_hfrosc_freq = (f_cpu/ 16);
-
-  PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
-  
-  // Ignore the first run (for icache reasons)
-  uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
-
-  cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
-  uint32_t prev_freq = cpu_freq;
-  
-  while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){
-    prev_trim = hfrosctrim;
-    prev_freq = cpu_freq;
-    hfrosctrim ++;
-    PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
-    cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
-  } 
-
-  // We couldn't go low enough
-  if (prev_freq > desired_hfrosc_freq){
-    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
-    cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
-    return cpu_freq;
-  }
-  
-  // We couldn't go high enough
-  if (cpu_freq < desired_hfrosc_freq){
-    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
-    cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
-    return cpu_freq;
-  }
-
-  // Check for over/undershoot
-  switch(target) {
-  case(PRCI_FREQ_CLOSEST):
-    if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) {
-      PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
-    } else {
-      PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
-    }
-    break;
-  case(PRCI_FREQ_UNDERSHOOT):
-    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
-    break;
-  default:
-    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
-  }
-
-  cpu_freq =  PRCI_measure_mcycle_freq(1000, RTC_FREQ);
-  return cpu_freq;
-
-}
-
-#endif
--- a/drivers/fe300prci/fe300prci_driver.h
+++ b/drivers/fe300prci/fe300prci_driver.h
@@ -1,79 +0,0 @@
-// See LICENSE file for license details
-
-#ifndef _FE300PRCI_DRIVER_H_
-#define _FE300PRCI_DRIVER_H_
-
-__BEGIN_DECLS
-
-#include <unistd.h>
-
-typedef enum prci_freq_target {
-  
-  PRCI_FREQ_OVERSHOOT,
-  PRCI_FREQ_CLOSEST,
-  PRCI_FREQ_UNDERSHOOT
-
-} PRCI_freq_target;
-
-/* Measure and return the approximate frequency of the 
- * CPU, as given by measuring the mcycle counter against 
- * the mtime ticks.
- */
-uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq);
-
-/* Safely switch over to the HFROSC using the given div
- * and trim settings.
- */
-void PRCI_use_hfrosc(int div, int trim);
-
-/* Safely switch over to the 16MHz HFXOSC,
- * applying the finaldiv clock divider (1 is the lowest
- * legal value).
- */
-void PRCI_use_hfxosc(uint32_t finaldiv);
-
-/* Safely switch over to the PLL using the given
- * settings.
- * 
- * Note that not all combinations of the inputs are actually
- * legal, and this function does not check for their
- * legality ("safely" means that this function won't turn off
- * or glitch the clock the CPU is actually running off, but
- * doesn't protect against you making it too fast or slow.)
- */
-
-void PRCI_use_pll(int refsel, int bypass,
-			 int r, int f, int q, int finaldiv,
-			 int hfroscdiv, int hfrosctrim);
-
-/* Use the default clocks configured at reset.
- * This is ~16Mhz HFROSC and turns off the LFROSC
- * (on the current FE310 Dev Platforms, an external LFROSC is 
- * used as it is more power efficient).
- */
-void PRCI_use_default_clocks();
-
-/* This routine will adjust the HFROSC trim
- * while using HFROSC as the clock source, 
- * measure the resulting frequency, then
- * use it as the PLL clock source, 
- * in an attempt to get over, under, or close to the 
- * requested frequency. It returns the actual measured 
- * frequency. 
- *
- * Note that the requested frequency must be within the 
- * range supported by the PLL so not all values are 
- * achievable with this function, and not all 
- * are guaranteed to actually work. The PLL
- * is rated higher than the hardware.
- * 
- * There is no check on the desired f_cpu frequency, it
- * is up to the user to specify something reasonable.
- */
-
-uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target);
-
-__END_DECLS
-
-#endif
-  
--- a/env/common-gcc.mk
+++ b/env/common-gcc.mk
@@ -16,6 +16,8 @@ BOARD?=iss

 ASM_SRCS += $(ENV_DIR)/start.S $(ENV_DIR)/entry.S
 C_SRCS   += $(PLATFORM_DIR)/init.c
+C_SRCS   += $(PLATFORM_DIR)/bsp_write.c $(PLATFORM_DIR)/bsp_read.c
+

 LINKER_SCRIPT ?= $(PLATFORM_DIR)/$(LINK_TARGET).lds

@@ -23,9 +25,10 @@ INCLUDES += -I$(BSP_BASE)/include
 INCLUDES += -I$(BSP_BASE)/drivers/
 INCLUDES += -I$(ENV_DIR)
 INCLUDES += -I$(PLATFORM_DIR)
+INCLUDES += -I$(BSP_BASE)/libwrap/sys/

 LDFLAGS += -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
-LDFLAGS += -L$(ENV_DIR)
+LDFLAGS += -L$(ENV_DIR) -L$(PLATFORM_DIR)
 LD_SCRIPT += -T $(LINKER_SCRIPT) -Wl,--no-warn-rwx-segments -Wl,-Map=$(TARGET).map  -nostartfiles 

 ifneq (,$(findstring specs=nano.specs,$(LDFLAGS), LD_SCRIPT))
--- a/env/hifive1.h
+++ b/env/hifive1.h
@@ -1,81 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_HIFIVE1_H
-#define _SIFIVE_HIFIVE1_H
-
-#include <stdint.h>
-
-/****************************************************************************
- * GPIO Connections
- *****************************************************************************/
-
-// These are the GPIO bit offsets for the RGB LED on HiFive1 Board.
-// These are also mapped to RGB LEDs on the Freedom E300 Arty
-// FPGA
-// Dev Kit.
-
-#define RED_LED_OFFSET   22
-#define GREEN_LED_OFFSET 19
-#define BLUE_LED_OFFSET  21
-
-// These are the GPIO bit offsets for the differen digital pins
-// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit.
-#define PIN_0_OFFSET 16
-#define PIN_1_OFFSET 17
-#define PIN_2_OFFSET 18
-#define PIN_3_OFFSET 19
-#define PIN_4_OFFSET 20
-#define PIN_5_OFFSET 21
-#define PIN_6_OFFSET 22
-#define PIN_7_OFFSET 23
-#define PIN_8_OFFSET 0
-#define PIN_9_OFFSET 1
-#define PIN_10_OFFSET 2
-#define PIN_11_OFFSET 3
-#define PIN_12_OFFSET 4
-#define PIN_13_OFFSET 5
-//#define PIN_14_OFFSET 8 //This pin is not connected on either board.
-#define PIN_15_OFFSET 9
-#define PIN_16_OFFSET 10
-#define PIN_17_OFFSET 11
-#define PIN_18_OFFSET 12
-#define PIN_19_OFFSET 13
-
-// These are *PIN* numbers, not
-// GPIO Offset Numbers.
-#define PIN_SPI1_SCK    (13u)
-#define PIN_SPI1_MISO   (12u)
-#define PIN_SPI1_MOSI   (11u)
-#define PIN_SPI1_SS0    (10u)
-#define PIN_SPI1_SS1    (14u) 
-#define PIN_SPI1_SS2    (15u)
-#define PIN_SPI1_SS3    (16u)
-
-#define SS_PIN_TO_CS_ID(x) \
-  ((x==PIN_SPI1_SS0 ? 0 :		 \
-    (x==PIN_SPI1_SS1 ? 1 :		 \
-     (x==PIN_SPI1_SS2 ? 2 :		 \
-      (x==PIN_SPI1_SS3 ? 3 :		 \
-       -1))))) 
-
-
-// These buttons are present only on the Freedom E300 Arty Dev Kit.
-#ifdef HAS_BOARD_BUTTONS
-#define BUTTON_0_OFFSET 15
-#define BUTTON_1_OFFSET 30
-#define BUTTON_2_OFFSET 31
-
-#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET)
-#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET)
-#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET)
-
-#endif
-
-#define HAS_HFXOSC 1
-#define HAS_LFROSC_BYPASS 1
-
-#define RTC_FREQ 32768
-
-void write_hex(int fd, unsigned long int hex);
-
-#endif /* _SIFIVE_HIFIVE1_H */
--- a/env/hifive1/init.c
+++ b/env/hifive1/init.c
@@ -1,238 +0,0 @@
-#include <stdint.h>
-#include <stdio.h>
-#include <unistd.h>
-
-#include "platform.h"
-#include "encoding.h"
-
-extern int main(int argc, char** argv);
-extern void trap_entry();
-
-static unsigned long mtime_lo(void)
-{
-  return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME);
-}
-
-#ifdef __riscv32
-
-static uint32_t mtime_hi(void)
-{
-  return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4);
-}
-
-uint64_t get_timer_value()
-{
-  while (1) {
-    uint32_t hi = mtime_hi();
-    uint32_t lo = mtime_lo();
-    if (hi == mtime_hi())
-      return ((uint64_t)hi << 32) | lo;
-  }
-}
-
-#else /* __riscv32 */
-
-uint64_t get_timer_value()
-{
-  return mtime_lo();
-}
-
-#endif
-
-unsigned long get_timer_freq()
-{
-  return 32768;
-}
-
-static void use_hfrosc(int div, int trim)
-{
-  // Make sure the HFROSC is running at its default setting
-  PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
-  while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ;
-  PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
-}
-
-static void use_pll(int refsel, int bypass, int r, int f, int q)
-{
-  // Ensure that we aren't running off the PLL before we mess with it.
-  if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
-    // Make sure the HFROSC is running at its default setting
-    use_hfrosc(4, 16);
-  }
-
-  // Set PLL Source to be HFXOSC if available.
-  uint32_t config_value = 0;
-
-  config_value |= PLL_REFSEL(refsel);
-
-  if (bypass) {
-    // Bypass
-    config_value |= PLL_BYPASS(1);
-
-    PRCI_REG(PRCI_PLLCFG) = config_value;
-
-    // If we don't have an HFXTAL, this doesn't really matter.
-    // Set our Final output divide to divide-by-1:
-    PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
-  } else {
-    // In case we are executing from QSPI,
-    // (which is quite likely) we need to
-    // set the QSPI clock divider appropriately
-    // before boosting the clock frequency.
-
-    // Div = f_sck/2
-    SPI0_REG(SPI_REG_SCKDIV) = 8;
-
-    // Set DIV Settings for PLL
-    // Both HFROSC and HFXOSC are modeled as ideal
-    // 16MHz sources (assuming dividers are set properly for
-    // HFROSC).
-    // (Legal values of f_REF are 6-48MHz)
-
-    // Set DIVR to divide-by-2 to get 8MHz frequency
-    // (legal values of f_R are 6-12 MHz)
-
-    config_value |= PLL_BYPASS(1);
-    config_value |= PLL_R(r);
-
-    // Set DIVF to get 512Mhz frequncy
-    // There is an implied multiply-by-2, 16Mhz.
-    // So need to write 32-1
-    // (legal values of f_F are 384-768 MHz)
-    config_value |= PLL_F(f);
-
-    // Set DIVQ to divide-by-2 to get 256 MHz frequency
-    // (legal values of f_Q are 50-400Mhz)
-    config_value |= PLL_Q(q);
-
-    // Set our Final output divide to divide-by-1:
-    PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
-
-    PRCI_REG(PRCI_PLLCFG) = config_value;
-
-    // Un-Bypass the PLL.
-    PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
-
-    // Wait for PLL Lock
-    // Note that the Lock signal can be glitchy.
-    // Need to wait 100 us
-    // RTC is running at 32kHz.
-    // So wait 4 ticks of RTC.
-    uint32_t now = mtime_lo();
-    while (mtime_lo() - now < 4) ;
-
-    // Now it is safe to check for PLL Lock
-    while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ;
-  }
-
-  // Switch over to PLL Clock source
-  PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
-}
-
-static void use_default_clocks()
-{
-  // Turn off the LFROSC
-  AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
-
-  // Use HFROSC
-  use_hfrosc(4, 16);
-}
-
-static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n)
-{
-  unsigned long start_mtime, delta_mtime;
-  unsigned long mtime_freq = get_timer_freq();
-
-  // Don't start measuruing until we see an mtime tick
-  unsigned long tmp = mtime_lo();
-  do {
-    start_mtime = mtime_lo();
-  } while (start_mtime == tmp);
-
-  unsigned long start_mcycle = read_csr(mcycle);
-
-  do {
-    delta_mtime = mtime_lo() - start_mtime;
-  } while (delta_mtime < n);
-
-  unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle;
-
-  return (delta_mcycle / delta_mtime) * mtime_freq
-         + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
-}
-
-unsigned long get_cpu_freq()
-{
-  static uint32_t cpu_freq;
-
-  if (!cpu_freq) {
-    // warm up I$
-    measure_cpu_freq(1);
-    // measure for real
-    cpu_freq = measure_cpu_freq(10);
-  }
-
-  return cpu_freq;
-}
-
-static void uart_init(size_t baud_rate)
-{
-  GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
-  GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
-  UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
-  UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
-}
-
-
-
-#ifdef USE_PLIC
-extern void handle_m_ext_interrupt();
-#endif
-
-#ifdef USE_M_TIME
-extern void handle_m_time_interrupt();
-#endif
-
-uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
-{
-  if (0){
-#ifdef USE_PLIC
-    // External Machine-Level interrupt from PLIC
-  } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
-    handle_m_ext_interrupt();
-#endif
-#ifdef USE_M_TIME
-    // External Machine-Level interrupt from PLIC
-  } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
-    handle_m_time_interrupt();
-#endif
-  }
-  else {
-    write(1, "trap\n", 5);
-    _exit(1 + mcause);
-  }
-  return epc;
-}
-
-void _init()
-{
-  
-  #ifndef NO_INIT
-  use_default_clocks();
-  use_pll(0, 0, 1, 31, 1);
-  uart_init(115200);
-
-  printf("core freq at %d Hz\n", get_cpu_freq());
-
-  write_csr(mtvec, &trap_entry);
-  if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
-    write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
-    write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
-  }
-  #endif
-  
-}
-
-void _fini()
-{
-}
--- a/env/hifive1/openocd.cfg
+++ b/env/hifive1/openocd.cfg
@@ -1,34 +0,0 @@
-adapter_khz     10000
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0008 0x001b
-ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
-
-#Reset Stretcher logic on FE310 is ~1 second long
-#This doesn't apply if you use
-# ftdi_set_signal, but still good to document
-#adapter_nsrst_delay 1500
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
-init
-#reset -- This type of reset is not implemented yet
-if {[ info exists pulse_srst]} {
-  ftdi_set_signal nSRST 0
-  ftdi_set_signal nSRST z
-  #Wait for the reset stretcher
-  #It will work without this, but
-  #will incur lots of delays for later commands.
-  sleep 1500
-}	
-halt
-#flash protect 0 64 last off
--- a/env/hifive1/platform.h
+++ b/env/hifive1/platform.h
@@ -1,133 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_PLATFORM_H
-#define _SIFIVE_PLATFORM_H
-
-// Some things missing from the official encoding.h
-#define MCAUSE_INT         0x80000000
-#define MCAUSE_CAUSE       0x7FFFFFFF
-
-#include "bits.h"
-#include "sifive/devices/aon.h"
-#include "sifive/devices/clint.h"
-#include "sifive/devices/gpio.h"
-#include "sifive/devices/otp.h"
-#include "sifive/devices/plic.h"
-#include "sifive/devices/prci.h"
-#include "sifive/devices/pwm.h"
-#include "sifive/devices/spi.h"
-#include "sifive/devices/uart.h"
-
-/****************************************************************************
- * Platform definitions
- *****************************************************************************/
-
-// Memory map
-#define MASKROM_MEM_ADDR _AC(0x00001000,UL)
-#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
-#define OTP_MEM_ADDR _AC(0x00020000,UL)
-#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
-#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
-#define AON_CTRL_ADDR _AC(0x10000000,UL)
-#define PRCI_CTRL_ADDR _AC(0x10008000,UL)
-#define OTP_CTRL_ADDR _AC(0x10010000,UL)
-#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
-#define UART0_CTRL_ADDR _AC(0x10013000,UL)
-#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
-#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
-#define UART1_CTRL_ADDR _AC(0x10023000,UL)
-#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
-#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
-#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
-#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
-#define SPI0_MEM_ADDR _AC(0x20000000,UL)
-#define MEM_CTRL_ADDR _AC(0x80000000,UL)
-
-// IOF masks
-#define IOF0_SPI1_MASK          _AC(0x000007FC,UL)
-#define SPI11_NUM_SS     (4)
-#define IOF_SPI1_SS0          (2u)
-#define IOF_SPI1_SS1          (8u)
-#define IOF_SPI1_SS2          (9u)
-#define IOF_SPI1_SS3          (10u)
-#define IOF_SPI1_MOSI         (3u)
-#define IOF_SPI1_MISO         (4u)
-#define IOF_SPI1_SCK          (5u)
-#define IOF_SPI1_DQ0          (3u)
-#define IOF_SPI1_DQ1          (4u)
-#define IOF_SPI1_DQ2          (6u)
-#define IOF_SPI1_DQ3          (7u)
-
-#define IOF0_SPI2_MASK          _AC(0xFC000000,UL)
-#define SPI2_NUM_SS       (1)
-#define IOF_SPI2_SS0          (26u)
-#define IOF_SPI2_MOSI         (27u)
-#define IOF_SPI2_MISO         (28u)
-#define IOF_SPI2_SCK          (29u)
-#define IOF_SPI2_DQ0          (27u)
-#define IOF_SPI2_DQ1          (28u)
-#define IOF_SPI2_DQ2          (30u)
-#define IOF_SPI2_DQ3          (31u)
-
-//#define IOF0_I2C_MASK          _AC(0x00003000,UL)
-
-#define IOF0_UART0_MASK         _AC(0x00030000, UL)
-#define IOF_UART0_RX   (16u)
-#define IOF_UART0_TX   (17u)
-
-#define IOF0_UART1_MASK         _AC(0x03000000, UL)
-#define IOF_UART1_RX (24u)
-#define IOF_UART1_TX (25u)
-
-#define IOF1_PWM0_MASK          _AC(0x0000000F, UL)
-#define IOF1_PWM1_MASK          _AC(0x00780000, UL)
-#define IOF1_PWM2_MASK          _AC(0x00003C00, UL)
-
-// Interrupt numbers
-#define INT_RESERVED 0
-#define INT_WDOGCMP 1
-#define INT_RTCCMP 2
-#define INT_UART0_BASE 3
-#define INT_UART1_BASE 4
-#define INT_SPI0_BASE 5
-#define INT_SPI1_BASE 6
-#define INT_SPI2_BASE 7
-#define INT_GPIO_BASE 8
-#define INT_PWM0_BASE 40
-#define INT_PWM1_BASE 44
-#define INT_PWM2_BASE 48
-
-// Helper functions
-#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
-#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
-#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
-#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
-#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
-#define OTP_REG(offset)  _REG32(OTP_CTRL_ADDR, offset)
-#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
-#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)
-#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
-#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
-#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
-#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
-#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
-#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
-#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
-#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
-
-// Misc
-
-#include <stdint.h>
-
-#define NUM_GPIO 32
-
-#define PLIC_NUM_INTERRUPTS 52
-#define PLIC_NUM_PRIORITIES 7
-
-#include "hifive1.h"
-
-unsigned long get_cpu_freq(void);
-unsigned long get_timer_freq(void);
-uint64_t get_timer_value(void);
-
-#endif /* _SIFIVE_PLATFORM_H */
--- a/env/hifive1/settings.mk
+++ b/env/hifive1/settings.mk
@@ -1,3 +0,0 @@
-# Describes the CPU on this board to the rest of the SDK.
-RISCV_ARCH := rv32imac
-RISCV_ABI  := ilp32
--- a/env/iss/bsp_read.c
+++ b/env/iss/bsp_read.c
@@ -0,0 +1,6 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+ssize_t _bsp_read(int fd, void *ptr, size_t len) { return EOF; }
--- a/env/iss/bsp_write.c
+++ b/env/iss/bsp_write.c
@@ -0,0 +1,25 @@
+/* See LICENSE of license details. */
+
+#include <errno.h>
+#include <stdint.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include <string.h>
+
+extern volatile uint64_t tohost;
+
+ssize_t _bsp_write(int fd, const void *ptr, size_t len) {
+
+  if (isatty(fd)) {
+    volatile uint64_t payload[8];
+    memset((void *)payload, 0, 8 * sizeof(uint64_t));
+    payload[0] = 64;
+    payload[2] = (uintptr_t)ptr;
+    payload[3] = len;
+    tohost = (uintptr_t)payload;
+    return len;
+  }
+
+  return 1;
+}
--- a/env/iss/link.lds
+++ b/env/iss/link.lds
@@ -5,7 +5,7 @@ ENTRY( _start )
 MEMORY
 {
  flash (rxai!w) : ORIGIN = 0x00000000, LENGTH = 1M
-  ram (wxa!ri) :   ORIGIN = 0x10000000, LENGTH = 16K
+  ram (wxa!ri) :   ORIGIN = 0x20000000, LENGTH = 1M
 }

 PHDRS
@@ -13,11 +13,12 @@ PHDRS
  flash PT_LOAD;
  ram_init PT_LOAD;
  ram PT_NULL;
+
 }

 SECTIONS
 {
-  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 8K;

  .init ORIGIN(flash)        :
  {
@@ -48,6 +49,18 @@ SECTIONS
    *(.gnu.linkonce.r.*)
  } >flash AT>flash :flash

+  .srodata        :
+  {
+
+    PROVIDE( _gp = . + 0x800 );
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+
+  } >flash AT>flash :flash
+  
  . = ALIGN(4);

  .preinit_array  :
@@ -123,23 +136,16 @@ SECTIONS
    *(.gnu.linkonce.d.*)
  } >ram AT>flash :ram_init

-  .srodata        :
-  {
-    PROVIDE( _gp = . + 0x800 );
-    *(.srodata.cst16)
-    *(.srodata.cst8)
-    *(.srodata.cst4)
-    *(.srodata.cst2)
-    *(.srodata .srodata.*)
-  } >ram AT>flash :ram_init
-
+ 
  .sdata          :
-  {
+  {    
+     
    __SDATA_BEGIN__ = .;
    *(.sdata .sdata.*)
    *(.gnu.linkonce.s.*)
-  } >ram AT>flash :ram_init

+  } >ram AT>flash :ram_init
+ 
  . = ALIGN(4);
  PROVIDE( _edata = . );
  PROVIDE( edata = . );
@@ -169,6 +175,7 @@ SECTIONS
    PROVIDE( _sp = . );
  } >ram AT>ram :ram

-  PROVIDE( tohost = 0xfffffff0 );
-  PROVIDE( fromhost = 0xfffffff8 );
+  PROVIDE( tohost = . );
+  PROVIDE( fromhost = . + 8 );
 }
+
--- a/env/iss/platform.h
+++ b/env/iss/platform.h
@@ -22,6 +22,9 @@

 #include <stdint.h>

+extern volatile uintptr_t tohost;
+extern volatile uintptr_t fromhost;
+
 void init_pll(void);
 unsigned long get_cpu_freq(void);
 unsigned long get_timer_freq(void);
--- a/env/moonlight/.gitignore
+++ b/env/moonlight/.gitignore
--- a/env/moonlight/bsp_read.c
+++ b/env/moonlight/bsp_read.c
@@ -0,0 +1,21 @@
+#include "platform.h"
+#include <stdint.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+ssize_t _bsp_read(int fd, void *ptr, size_t len) {
+  uint8_t *current = (uint8_t *)ptr;
+  ssize_t result = 0;
+  if (isatty(fd)) {
+    for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len) &&
+                                   (get_uart_rx_tx_reg_rx_avail(uart) > 0);
+         current++) {
+      *current = uart_read(uart);
+      result++;
+    }
+
+    return result;
+  }
+  return EOF;
+}
--- a/env/moonlight/bsp_write.c
+++ b/env/moonlight/bsp_write.c
@@ -0,0 +1,21 @@
+/* See LICENSE of license details. */
+
+#include "platform.h"
+#include <errno.h>
+#include <stdint.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+ssize_t _bsp_write(int fd, const void *ptr, size_t len) {
+  const uint8_t *current = (const uint8_t *)ptr;
+  if (isatty(fd)) {
+    for (size_t jj = 0; jj < len; jj++) {
+      uart_write(uart, current[jj]);
+      if (current[jj] == '\n') {
+        uart_write(uart, '\r');
+      }
+    }
+    return len;
+  }
+  return 1;
+}
--- a/env/moonlight/camera.lds
+++ b/env/moonlight/camera.lds
--- a/env/moonlight/init.c
+++ b/env/moonlight/init.c
--- a/env/moonlight/link.lds
+++ b/env/moonlight/link.lds
@@ -176,6 +176,8 @@ SECTIONS
    PROVIDE( _sp = . );
  } >ram AT>ram :ram

-  PROVIDE( tohost = 0xfffffff0 );
-  PROVIDE( fromhost = 0xfffffff8 );
+
+  
+  PROVIDE( tohost = . );
+  PROVIDE( fromhost = . + 8 );
 }
--- a/env/moonlight/platform.h
+++ b/env/moonlight/platform.h
@@ -13,16 +13,16 @@

 #define APB_BUS

-#include "ehrenberg/devices/aclint.h"
-#include "ehrenberg/devices/camera.h"
-#include "ehrenberg/devices/dma.h"
-#include "ehrenberg/devices/gen/sysctrl.h"
-#include "ehrenberg/devices/gpio.h"
-#include "ehrenberg/devices/i2s.h"
-#include "ehrenberg/devices/msg_if.h"
-#include "ehrenberg/devices/qspi.h"
-#include "ehrenberg/devices/timer.h"
-#include "ehrenberg/devices/uart.h"
+#include "minres/devices/aclint.h"
+#include "minres/devices/camera.h"
+#include "minres/devices/dma.h"
+#include "minres/devices/gen/sysctrl.h"
+#include "minres/devices/gpio.h"
+#include "minres/devices/i2s.h"
+#include "minres/devices/msg_if.h"
+#include "minres/devices/qspi.h"
+#include "minres/devices/timer.h"
+#include "minres/devices/uart.h"

 #define PERIPH(TYPE, ADDR) ((volatile TYPE *)(ADDR))

@@ -39,8 +39,8 @@
 #define dma PERIPH(dma_t, APB_BASE + 0xB0000)
 #define msgif PERIPH(mkcontrolclusterstreamcontroller_t, APB_BASE + 0xC0000)

-#include "ehrenberg/devices/fki_cluster_info.h"
-#include "ehrenberg/devices/flexki_messages.h"
+#include "minres/devices/fki_cluster_info.h"
+#include "minres/devices/flexki_messages.h"

 #ifndef XIP_START_LOC
 #define XIP_START_LOC 0xE0000000
--- a/env/moonlight/ram.lds
+++ b/env/moonlight/ram.lds
--- a/env/moonlight/rom.lds
+++ b/env/moonlight/rom.lds
--- a/env/moonlight/spi_flash.lds
+++ b/env/moonlight/spi_flash.lds
@@ -171,10 +171,10 @@ SECTIONS
  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
  {
    PROVIDE( _heap_end = . );
+	PROVIDE( tohost = . );
+  	PROVIDE( fromhost = . );
    . = __stack_size;
    PROVIDE( _sp = . );
  } >ram AT>ram :ram

-  PROVIDE( tohost = 0xfffffff0 );
-  PROVIDE( fromhost = 0xfffffff8 );
 }
--- a/env/ehrenberg/.gitignore
+++ b/env/ehrenberg/.gitignore
--- a/env/riscv_vp/bsp_read.c
+++ b/env/riscv_vp/bsp_read.c
@@ -0,0 +1,21 @@
+#include "platform.h"
+#include <stdint.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+ssize_t _bsp_read(int fd, void *ptr, size_t len) {
+  uint8_t *current = (uint8_t *)ptr;
+  ssize_t result = 0;
+  if (isatty(fd)) {
+    for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len) &&
+                                   (get_uart_rx_tx_reg_rx_avail(uart) > 0);
+         current++) {
+      *current = uart_read(uart);
+      result++;
+    }
+
+    return result;
+  }
+  return EOF;
+}
--- a/env/riscv_vp/bsp_write.c
+++ b/env/riscv_vp/bsp_write.c
@@ -0,0 +1,21 @@
+/* See LICENSE of license details. */
+
+#include "platform.h"
+#include <errno.h>
+#include <stdint.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+ssize_t _bsp_write(int fd, const void *ptr, size_t len) {
+  const uint8_t *current = (const uint8_t *)ptr;
+  if (isatty(fd)) {
+    for (size_t jj = 0; jj < len; jj++) {
+      uart_write(uart, current[jj]);
+      if (current[jj] == '\n') {
+        uart_write(uart, '\r');
+      }
+    }
+    return len;
+  }
+  return 1;
+}
--- a/env/riscv_vp/flash.lds
+++ b/env/riscv_vp/flash.lds
@@ -2,24 +2,21 @@ OUTPUT_ARCH( "riscv" )

 ENTRY( _start )

-MEMORY
-{
-  flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
-  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 512K
-}
+INCLUDE memory_map.ld

 PHDRS
 {
  flash PT_LOAD;
  ram_init PT_LOAD;
  ram PT_NULL;
+  dram PT_NULL;
 }

 SECTIONS
 {
  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;

-  .init           :
+  .init ORIGIN(flash)        :
  {
    KEEP (*(SORT_NONE(.init)))
  } >flash AT>flash :flash
@@ -104,11 +101,11 @@ SECTIONS
    KEEP (*(.dtors))
  } >flash AT>flash :flash

-  .except :
+  .dummy          :
  {
-  	*(.gcc_except_table.*)
-  } >flash AT>flash :flash
-  
+	*(.comment.*)
+
+  }
  .lalign         :
  {
    . = ALIGN(4);
@@ -123,13 +120,20 @@ SECTIONS

  .data          :
  {
+    __DATA_BEGIN__ = .;
    *(.data .data.*)
    *(.gnu.linkonce.d.*)
-    . = ALIGN(8);
-    PROVIDE( __global_pointer$ = . + 0x800 );
+  } >ram AT>flash :ram_init
+
+  .sdata          :
+  {
+    __SDATA_BEGIN__ = .;
    *(.sdata .sdata.*)
    *(.gnu.linkonce.s.*)
-    . = ALIGN(8);
+  } >ram AT>flash :ram_init
+
+  .srodata        :
+  {
    *(.srodata.cst16)
    *(.srodata.cst8)
    *(.srodata.cst4)
@@ -154,6 +158,8 @@ SECTIONS
  } >ram AT>ram :ram

  . = ALIGN(8);
+  __BSS_END__ = .;
+  __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,  MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
  PROVIDE( _end = . );
  PROVIDE( end = . );

@@ -163,4 +169,9 @@ SECTIONS
    . = __stack_size;
    PROVIDE( _sp = . );
  } >ram AT>ram :ram
+
+
+  
+  PROVIDE( tohost = . );
+  PROVIDE( fromhost = . + 8 );
 }
--- a/env/riscv_vp/init.c
+++ b/env/riscv_vp/init.c
@@ -0,0 +1,138 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <unistd.h>
+
+#include "platform.h"
+#include "encoding.h"
+
+
+extern int main(int argc, char** argv);
+extern void trap_entry(void);
+#define IRQ_M_SOFT   3
+#define IRQ_M_TIMER  7
+#define IRQ_M_EXT    11
+
+#define NUM_INTERRUPTS 16
+#define MTIMER_NEXT_TICK_INC 1000
+
+void handle_m_ext_interrupt(void);
+void handle_m_time_interrupt(void);
+uint32_t handle_trap(uint32_t mcause, uint32_t mepc, uint32_t sp);
+void default_handler(void);
+void _init(void);
+
+typedef void (*my_interrupt_function_ptr_t) (void);
+my_interrupt_function_ptr_t localISR[NUM_INTERRUPTS] __attribute__((aligned(64)));
+
+static unsigned long mtime_lo(void)
+{
+    unsigned long ret;
+    __asm volatile("rdtime %0":"=r"(ret));
+    return ret;
+}
+
+
+#if __riscv_xlen==32
+
+static uint32_t mtime_hi(void)
+{
+    unsigned long ret;
+    __asm volatile("rdtimeh %0":"=r"(ret));
+    return ret;
+}
+
+uint64_t get_timer_value(void)
+{
+  while (1) {
+    uint32_t hi = mtime_hi();
+    uint32_t lo = mtime_lo();
+    if (hi == mtime_hi())
+      return ((uint64_t)hi << 32) | lo;
+  }
+}
+
+#elif __riscv_xlen==64
+
+uint64_t get_timer_value()
+{
+  return mtime_lo();
+}
+
+#endif
+
+unsigned long get_timer_freq()
+{
+  return 32768;
+}
+
+unsigned long get_cpu_freq()
+{
+  return 100000000;
+}
+
+void init_pll(void){
+    //TODO: implement initialization
+}
+
+static void uart_init(size_t baud_rate)
+{
+  //TODO: implement initialization
+}
+
+void __attribute__((weak)) handle_m_ext_interrupt(){
+}
+
+void __attribute__((weak)) handle_m_time_interrupt(){
+  uint64_t time = get_aclint_mtime(aclint);
+  time+=MTIMER_NEXT_TICK_INC;
+  set_aclint_mtimecmp(aclint, time);
+}
+
+void __attribute__((weak)) default_handler(void) {
+  puts("default handler\n");
+}
+
+void __attribute__((weak)) interrupt_handler(unsigned) {
+  puts("interrupt handler\n");
+}
+
+uint32_t handle_trap(uint32_t mcause, uint32_t mepc, uint32_t sp){
+  if ((mcause & MCAUSE_INT)) {
+    if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT) {
+      handle_m_ext_interrupt();
+    } else if (((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ 
+      handle_m_time_interrupt();
+    } else {
+      interrupt_handler(mcause& ~MCAUSE_INT);
+    }
+  } else {
+    write(1, "trap\n", 5);
+    _exit(1 + mcause);
+  }
+  return mepc;
+}
+
+void _init()
+{
+  
+#ifndef NO_INIT
+  init_pll();
+  uart_init(115200);
+  printf("core freq at %lu Hz\n", get_cpu_freq());
+  write_csr(mtvec, &trap_entry);
+  if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
+    write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
+    write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
+  }
+  int i=0;
+  while(i<NUM_INTERRUPTS)  {
+    localISR[i++] = default_handler;
+  }
+
+#endif
+  
+}
+
+void _fini(void)
+{
+}
--- a/env/riscv_vp/memory_map.ld
+++ b/env/riscv_vp/memory_map.ld
@@ -0,0 +1,7 @@
+MEMORY
+{
+  ram   (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 128K
+  rom   (rxai!w) : ORIGIN = 0x10080000, LENGTH = 8k
+  flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 16M
+  dram  (wxa!ri) : ORIGIN = 0x40000000, LENGTH = 2048M
+}
--- a/env/riscv_vp/platform.h
+++ b/env/riscv_vp/platform.h
@@ -0,0 +1,48 @@
+// See LICENSE for license details.
+
+#ifndef _ISS_PLATFORM_H
+#define _ISS_PLATFORM_H
+
+#if __riscv_xlen == 32
+#define MCAUSE_INT 0x80000000UL
+#define MCAUSE_CAUSE 0x000003FFUL
+#else
+#define MCAUSE_INT 0x8000000000000000UL
+#define MCAUSE_CAUSE 0x00000000000003FFUL
+#endif
+
+#define APB_BUS
+
+#include "minres/devices/aclint.h"
+#include "minres/devices/dma.h"
+#include "minres/devices/gen/sysctrl.h"
+#include "minres/devices/gpio.h"
+#include "minres/devices/i2s.h"
+#include "minres/devices/qspi.h"
+#include "minres/devices/timer.h"
+#include "minres/devices/uart.h"
+
+#define PERIPH(TYPE, ADDR) ((volatile TYPE*)(ADDR))
+// values from memory_map.ld
+#define XIP_START_LOC 0x20000000
+#define RAM_START_LOC 0x00000000
+#define APB_BASE 0x10000000
+
+#define gpio PERIPH(gpio_t, APB_BASE + 0x0000)
+#define uart PERIPH(uart_t, APB_BASE + 0x01000)
+#define timer PERIPH(timercounter_t, APB_BASE + 0x20000)
+#define aclint PERIPH(aclint_t, APB_BASE + 0x30000)
+#define sysctrl PERIPH(sysctrl_t, APB_BASE + 0x40000)
+#define qspi PERIPH(qspi_t, APB_BASE + 0x50000)
+#define i2s PERIPH(i2s_t, APB_BASE + 0x90000)
+#define dma PERIPH(dma_t, APB_BASE + 0xB0000)
+
+// Misc
+
+#include <stdint.h>
+
+void init_pll(void);
+unsigned long get_cpu_freq(void);
+unsigned long get_timer_freq(void);
+
+#endif /* _ISS_PLATFORM_H */
--- a/env/hifive1/dhrystone.lds
+++ b/env/hifive1/dhrystone.lds
@@ -2,27 +2,24 @@ OUTPUT_ARCH( "riscv" )

 ENTRY( _start )

-MEMORY
-{
-  flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
-  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
-}
+INCLUDE memory_map.ld

 PHDRS
 {
-  flash PT_LOAD;
+  rom PT_LOAD;
  ram_init PT_LOAD;
  ram PT_NULL;
+  dram PT_NULL;
 }

 SECTIONS
 {
  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;

-  .init           :
+  .init ORIGIN(rom)        :
  {
    KEEP (*(SORT_NONE(.init)))
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom

  .text           :
  {
@@ -30,17 +27,24 @@ SECTIONS
    *(.text.startup .text.startup.*)
    *(.text .text.*)
    *(.gnu.linkonce.t.*)
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom

  .fini           :
  {
    KEEP (*(SORT_NONE(.fini)))
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom

  PROVIDE (__etext = .);
  PROVIDE (_etext = .);
  PROVIDE (etext = .);

+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >rom AT>rom :rom
+
  . = ALIGN(4);

  .preinit_array  :
@@ -48,7 +52,7 @@ SECTIONS
    PROVIDE_HIDDEN (__preinit_array_start = .);
    KEEP (*(.preinit_array))
    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom

  .init_array     :
  {
@@ -56,7 +60,7 @@ SECTIONS
    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
    PROVIDE_HIDDEN (__init_array_end = .);
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom

  .fini_array     :
  {
@@ -64,7 +68,7 @@ SECTIONS
    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom

  .ctors          :
  {
@@ -86,7 +90,7 @@ SECTIONS
    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
    KEEP (*(SORT(.ctors.*)))
    KEEP (*(.ctors))
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom

  .dtors          :
  {
@@ -95,38 +99,47 @@ SECTIONS
    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
    KEEP (*(SORT(.dtors.*)))
    KEEP (*(.dtors))
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom

+  .dummy          :
+  {
+	*(.comment.*)
+
+  }
  .lalign         :
  {
    . = ALIGN(4);
    PROVIDE( _data_lma = . );
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom

  .dalign         :
  {
    . = ALIGN(4);
    PROVIDE( _data = . );
-  } >ram AT>flash :ram_init
+  } >ram AT>rom :ram_init

  .data          :
  {
-    *(.rdata)
-    *(.rodata .rodata.*)
-    *(.gnu.linkonce.r.*)
+    __DATA_BEGIN__ = .;
    *(.data .data.*)
    *(.gnu.linkonce.d.*)
-    . = ALIGN(8);
-    PROVIDE( __global_pointer$ = . + 0x800 );
+  } >ram AT>rom :ram_init
+
+  .sdata          :
+  {
+    __SDATA_BEGIN__ = .;
    *(.sdata .sdata.*)
    *(.gnu.linkonce.s.*)
-    . = ALIGN(8);
+  } >ram AT>rom :ram_init
+
+  .srodata        :
+  {
    *(.srodata.cst16)
    *(.srodata.cst8)
    *(.srodata.cst4)
    *(.srodata.cst2)
    *(.srodata .srodata.*)
-  } >ram AT>flash :ram_init
+  } >ram AT>rom :ram_init

  . = ALIGN(4);
  PROVIDE( _edata = . );
@@ -145,6 +158,8 @@ SECTIONS
  } >ram AT>ram :ram

  . = ALIGN(8);
+  __BSS_END__ = .;
+  __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,  MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
  PROVIDE( _end = . );
  PROVIDE( end = . );

@@ -154,4 +169,9 @@ SECTIONS
    . = __stack_size;
    PROVIDE( _sp = . );
  } >ram AT>ram :ram
+
+
+  
+  PROVIDE( tohost = . );
+  PROVIDE( fromhost = . + 8 );
 }
--- a/libwrap/semihosting/semihosting.c
+++ b/libwrap/semihosting/semihosting.c
--- a/env/start.S
+++ b/env/start.S
@@ -1,3 +1,4 @@
+#include "encoding.h"
 // See LICENSE for license details.

 	.section .init
--- a/env/testbench/TGCP/.gitignore
+++ b/env/testbench/TGCP/.gitignore
--- a/env/testbench/TGCP/init.c
+++ b/env/testbench/TGCP/init.c
--- a/env/testbench/TGCP/link.lds
+++ b/env/testbench/TGCP/link.lds
--- a/env/testbench/TGCP/platform.h
+++ b/env/testbench/TGCP/platform.h
--- a/env/testbench/rtl/.gitignore
+++ b/env/testbench/rtl/.gitignore
@@ -0,0 +1 @@
+/*.o
--- a/env/testbench/rtl/bsp_read.c
+++ b/env/testbench/rtl/bsp_read.c
@@ -0,0 +1,19 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+ssize_t _bsp_read(int fd, void *ptr, size_t len) {
+  uint8_t *current = (uint8_t *)ptr;
+  volatile uint32_t *uart_rx = (uint32_t *)0xFFFF0000;
+  ssize_t result = 0;
+  if (isatty(fd)) {
+    for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len);
+         current++) {
+      *current = *uart_rx;
+      result++;
+    }
+    return result;
+  }
+  return EOF;
+}
--- a/env/testbench/rtl/bsp_write.c
+++ b/env/testbench/rtl/bsp_write.c
@@ -0,0 +1,18 @@
+/* See LICENSE of license details. */
+
+#include <errno.h>
+#include <stdint.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+ssize_t _bsp_write(int fd, const void *ptr, size_t len) {
+  const uint8_t *current = (const uint8_t *)ptr;
+  if (isatty(fd)) {
+    for (size_t jj = 0; jj < len; jj++) {
+      *((uint32_t *)0xFFFF0000) = current[jj];
+    }
+    return len;
+  }
+
+  return 1;
+}
--- a/env/testbench/rtl/init.c
+++ b/env/testbench/rtl/init.c
--- a/env/testbench/rtl/link.lds
+++ b/env/testbench/rtl/link.lds
--- a/env/testbench/rtl/platform.h
+++ b/env/testbench/rtl/platform.h
--- a/env/tgc_vp
+++ b/env/tgc_vp
@@ -1 +1 @@
-ehrenberg
+moonlight/
--- a/libwrap/semihosting/trap.c
+++ b/libwrap/semihosting/trap.c
--- a/include/ehrenberg/devices/gen/mkcontrolclusterstreamcontroller.h
+++ b/include/ehrenberg/devices/gen/mkcontrolclusterstreamcontroller.h
@@ -1,290 +0,0 @@
-/*
-* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Generated at 2025-05-05 14:06:05 UTC 
-* by peakrdl_mnrs version 1.2.9
-*/
-
-#ifndef _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
-#define _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
-
-#include <stdint.h>
-
-typedef struct {
-    volatile uint32_t REG_SEND;
-    volatile uint32_t REG_HEADER;
-    volatile uint32_t REG_ACK;
-    volatile uint32_t REG_RECV_ID;
-    volatile uint32_t REG_RECV_PAYLOAD;
-    uint8_t fill0[12];
-    volatile uint32_t REG_PAYLOAD_0;
-    volatile uint32_t REG_PAYLOAD_1;
-    volatile uint32_t REG_PAYLOAD_2;
-    volatile uint32_t REG_PAYLOAD_3;
-    volatile uint32_t REG_PAYLOAD_4;
-    volatile uint32_t REG_PAYLOAD_5;
-    volatile uint32_t REG_PAYLOAD_6;
-    volatile uint32_t REG_PAYLOAD_7;
-    volatile uint32_t REG_PAYLOAD_8;
-    volatile uint32_t REG_PAYLOAD_9;
-    volatile uint32_t REG_PAYLOAD_10;
-    volatile uint32_t REG_PAYLOAD_11;
-    volatile uint32_t REG_PAYLOAD_12;
-    volatile uint32_t REG_PAYLOAD_13;
-    volatile uint32_t REG_PAYLOAD_14;
-    volatile uint32_t REG_PAYLOAD_15;
-} mkcontrolclusterstreamcontroller_t;
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK 0x1
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND(V) \
-  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK 0xf
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID(V) \
-  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS 4
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH(V) \
-  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK 0x1
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS 1
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK 0x1
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK 0xf
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_OFFS)
-
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_OFFS 0
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_MASK 0xffffffff
-#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_OFFS)
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND
-static inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-     reg->REG_SEND = value;
-}
-static inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
-    reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER
-static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg) {
-     return reg->REG_HEADER;
-}
-static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-     reg->REG_HEADER = value;
-}
-static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
-    return (reg->REG_HEADER >> 0) & 0xf;
-}
-static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
-    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
-}
-static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg) {
-    return (reg->REG_HEADER >> 4) & 0xf;
-}
-static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
-    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
-}
-static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg) {
-    return (reg->REG_HEADER >> 8) & 0x7;
-}
-static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
-    reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
-}
-static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg) {
-    return (reg->REG_HEADER >> 11) & 0x3;
-}
-static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
-    reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK
-static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg) {
-     return reg->REG_ACK;
-}
-static inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-     reg->REG_ACK = value;
-}
-static inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
-    reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
-}
-static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(volatile mkcontrolclusterstreamcontroller_t* reg) {
-    return (reg->REG_ACK >> 1) & 0x1;
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID
-static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
-     return reg->REG_RECV_ID;
-}
-static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
-    return (reg->REG_RECV_ID >> 0) & 0xf;
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD
-static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg) {
-    return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_8(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_8 = (reg->REG_PAYLOAD_8 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_9(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_9 = (reg->REG_PAYLOAD_9 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_10(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_10 = (reg->REG_PAYLOAD_10 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_11(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_11 = (reg->REG_PAYLOAD_11 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_12(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_12 = (reg->REG_PAYLOAD_12 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_13(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_13 = (reg->REG_PAYLOAD_13 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_14(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_14 = (reg->REG_PAYLOAD_14 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15
-static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_15(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_15 = (reg->REG_PAYLOAD_15 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-#endif /* _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H */
--- a/include/ehrenberg/devices/aclint.h
+++ b/include/ehrenberg/devices/aclint.h
@@ -16,6 +16,7 @@ static uint64_t get_aclint_mtime(volatile aclint_t* reg){
 }

 static void set_aclint_mtimecmp(volatile aclint_t* reg, uint64_t value){
+    set_aclint_mtimecmp0lo(reg, (uint32_t)0xFFFFFFFF);
    set_aclint_mtimecmp0hi(reg, (uint32_t)(value >> 32));
    set_aclint_mtimecmp0lo(reg, (uint32_t)value);
 }
--- a/include/ehrenberg/devices/camera.h
+++ b/include/ehrenberg/devices/camera.h
--- a/include/ehrenberg/devices/dma.h
+++ b/include/ehrenberg/devices/dma.h
--- a/include/ehrenberg/devices/fki_cluster_info.h
+++ b/include/ehrenberg/devices/fki_cluster_info.h
@@ -13,7 +13,6 @@ static inline uint32_t fki_addr_sram2(uint8_t cluster);
 static inline uint32_t fki_addr_cntrl_cva5(uint8_t cluster);
 static inline uint32_t fki_addr_cntrl_tgc(uint8_t cluster);
 static inline uint32_t fki_addr_ccc_idxTasks(uint8_t cluster);
-static inline uint32_t fki_addr_cacheFlushControl(uint8_t cluster);
 static inline uint32_t fki_addr_cntrl_tgc_clusterReg(uint8_t cluster);
 static inline uint32_t fki_addr_ccc_idxJobs(uint8_t cluster);
 static inline uint32_t fki_addr_cntrl_cva5_clusterReg(uint8_t cluster);
@@ -57,11 +56,8 @@ static inline uint32_t fki_addr_sram3(uint8_t cluster);
 #define BYTES_Compute0_cntrl_tgc 8192
 #define HIGH_Compute0_cntrl_tgc 0x8000cfff
 #define ADDR_Compute0_ut_adapter 0x8000e000
-#define BYTES_Compute0_ut_adapter 4096
-#define HIGH_Compute0_ut_adapter 0x8000efff
-#define ADDR_Compute0_cacheFlushControl 0x8000f000
-#define BYTES_Compute0_cacheFlushControl 4096
-#define HIGH_Compute0_cacheFlushControl 0x8000ffff
+#define BYTES_Compute0_ut_adapter 8192
+#define HIGH_Compute0_ut_adapter 0x8000ffff
 #define ADDR_Compute0_sram0 0x80010000
 #define BYTES_Compute0_sram0 524288
 #define HIGH_Compute0_sram0 0x8008ffff
@@ -108,11 +104,8 @@ static inline uint32_t fki_addr_sram3(uint8_t cluster);
 #define BYTES_Compute1_cntrl_tgc 12288
 #define HIGH_Compute1_cntrl_tgc 0x9000dfff
 #define ADDR_Compute1_ut_adapter 0x9000e000
-#define BYTES_Compute1_ut_adapter 4096
-#define HIGH_Compute1_ut_adapter 0x9000efff
-#define ADDR_Compute1_cacheFlushControl 0x9000f000
-#define BYTES_Compute1_cacheFlushControl 4096
-#define HIGH_Compute1_cacheFlushControl 0x9000ffff
+#define BYTES_Compute1_ut_adapter 8192
+#define HIGH_Compute1_ut_adapter 0x9000ffff
 #define ADDR_Compute1_sram0 0x90010000
 #define BYTES_Compute1_sram0 524288
 #define HIGH_Compute1_sram0 0x9008ffff
@@ -280,20 +273,6 @@ static inline uint32_t fki_addr_ccc_idxTasks(uint8_t cluster) {
 	}
 }

-static inline uint32_t fki_addr_cacheFlushControl(uint8_t cluster) {
-	switch(cluster) {
-		case 3: {
-			return 0x9000f000;
-		}
-		case 2: {
-			return 0x8000f000;
-		}
-		default: {
-			return -1;
-		}
-	}
-}
-
 static inline uint32_t fki_addr_cntrl_tgc_clusterReg(uint8_t cluster) {
 	switch(cluster) {
 		case 3: {
--- a/include/ehrenberg/devices/flexki_messages.h
+++ b/include/ehrenberg/devices/flexki_messages.h
@@ -36,27 +36,6 @@ static void send_msg(uint32_t cluster, uint32_t component, uint32_t msg_len, uin
            case 7:
                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(msgif, words[i]);
                break;
-            case 8:
-                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_8(msgif, words[i]);
-                break;
-            case 9:
-                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_9(msgif, words[i]);
-                break;
-            case 10:
-                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_10(msgif, words[i]);
-                break;
-            case 11:
-                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_11(msgif, words[i]);
-                break;
-            case 12:
-                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_12(msgif, words[i]);
-                break;
-            case 13:
-                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_13(msgif, words[i]);
-                break;
-            case 14:
-                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_14(msgif, words[i]);
-                break;
            default:
                break;
        }
--- a/include/ehrenberg/devices/gen/aclint.h
+++ b/include/ehrenberg/devices/gen/aclint.h
--- a/include/ehrenberg/devices/gen/apb3spi.h
+++ b/include/ehrenberg/devices/gen/apb3spi.h
--- a/include/ehrenberg/devices/gen/camera.h
+++ b/include/ehrenberg/devices/gen/camera.h
--- a/include/ehrenberg/devices/gen/dma.h
+++ b/include/ehrenberg/devices/gen/dma.h
--- a/include/ehrenberg/devices/gen/gpio.h
+++ b/include/ehrenberg/devices/gen/gpio.h
--- a/include/ehrenberg/devices/gen/i2s.h
+++ b/include/ehrenberg/devices/gen/i2s.h
--- a/include/minres/devices/gen/mkcontrolclusterstreamcontroller.h
+++ b/include/minres/devices/gen/mkcontrolclusterstreamcontroller.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2023 - 2025 MINRES Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generated at 2025-02-18 11:11:47 UTC
+ * by peakrdl_mnrs version 1.2.9
+ */
+
+#ifndef _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
+#define _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
+
+#include <stdint.h>
+
+typedef struct {
+  volatile uint32_t REG_SEND;
+  volatile uint32_t REG_HEADER;
+  volatile uint32_t REG_ACK;
+  volatile uint32_t REG_RECV_ID;
+  volatile uint32_t REG_RECV_PAYLOAD;
+  uint8_t fill0[12];
+  volatile uint32_t REG_PAYLOAD_0;
+  volatile uint32_t REG_PAYLOAD_1;
+  volatile uint32_t REG_PAYLOAD_2;
+  volatile uint32_t REG_PAYLOAD_3;
+  volatile uint32_t REG_PAYLOAD_4;
+  volatile uint32_t REG_PAYLOAD_5;
+  volatile uint32_t REG_PAYLOAD_6;
+  volatile uint32_t REG_PAYLOAD_7;
+} mkcontrolclusterstreamcontroller_t;
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK 0x1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS 4
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT(V)    \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK) \
+   << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER(V)    \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK) \
+   << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK 0x1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS 1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK 0x1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS)
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND
+static inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_SEND = value;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
+  reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return reg->REG_HEADER;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_HEADER = value;
+}
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return (reg->REG_HEADER >> 0) & 0xf;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg,
+                                                                              uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
+}
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return (reg->REG_HEADER >> 4) & 0xf;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg,
+                                                                                  uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
+}
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(
+    volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return (reg->REG_HEADER >> 8) & 0x7;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg,
+                                                                                       uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
+}
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return (reg->REG_HEADER >> 11) & 0x3;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg,
+                                                                                     uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return reg->REG_ACK;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_ACK = value;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
+  reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
+}
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return (reg->REG_ACK >> 1) & 0x1;
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return reg->REG_RECV_ID;
+}
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return (reg->REG_RECV_ID >> 0) & 0xf;
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H */
--- a/include/ehrenberg/devices/gen/msgif.h
+++ b/include/ehrenberg/devices/gen/msgif.h
--- a/include/ehrenberg/devices/gen/sysctrl.h
+++ b/include/ehrenberg/devices/gen/sysctrl.h
--- a/include/ehrenberg/devices/gen/timercounter.h
+++ b/include/ehrenberg/devices/gen/timercounter.h
--- a/include/ehrenberg/devices/gen/uart.h
+++ b/include/ehrenberg/devices/gen/uart.h
--- a/include/ehrenberg/devices/gpio.h
+++ b/include/ehrenberg/devices/gpio.h
--- a/include/ehrenberg/devices/i2s.h
+++ b/include/ehrenberg/devices/i2s.h
--- a/include/ehrenberg/devices/interrupt.h
+++ b/include/ehrenberg/devices/interrupt.h
--- a/include/ehrenberg/devices/msg_if.h
+++ b/include/ehrenberg/devices/msg_if.h
--- a/include/ehrenberg/devices/qspi.h
+++ b/include/ehrenberg/devices/qspi.h
@@ -66,9 +66,11 @@ static inline uint8_t spi_read(volatile qspi_t *qspi) {
  qspi->DATA = SPI_CMD_READ;
  while (spi_rsp_occupied(qspi) == 0)
    ;
-  while ((qspi->DATA & 0x80000000) == 0)
-    ;
-  return qspi->DATA;
+  int32_t data;
+  do {
+      data = qspi->DATA ;
+  } while (data<0);
+  return data;
 }

 static inline void spi_select(volatile qspi_t *qspi, uint32_t slaveId) {
--- a/include/ehrenberg/devices/sysctrl.h
+++ b/include/ehrenberg/devices/sysctrl.h
--- a/include/ehrenberg/devices/timer.h
+++ b/include/ehrenberg/devices/timer.h
--- a/include/ehrenberg/devices/uart.h
+++ b/include/ehrenberg/devices/uart.h
@@ -21,7 +21,7 @@ static inline void uart_write(volatile uart_t* reg, uint8_t data){
    set_uart_rx_tx_reg_data(reg, data);
 }

-static inline inline uint8_t uart_read(volatile uart_t* reg){
+static inline uint8_t uart_read(volatile uart_t* reg){
    uint32_t res = get_uart_rx_tx_reg_data(reg);
    while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg);
    return res;
--- a/libwrap/semihosting/semihosting.h
+++ b/libwrap/semihosting/semihosting.h
--- a/include/sifive/devices/aon.h
+++ b/include/sifive/devices/aon.h
@@ -1,88 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_AON_H
-#define _SIFIVE_AON_H
-
-/* Register offsets */
-
-#define AON_WDOGCFG     0x000
-#define AON_WDOGCOUNT   0x008
-#define AON_WDOGS       0x010
-#define AON_WDOGFEED    0x018
-#define AON_WDOGKEY     0x01C
-#define AON_WDOGCMP     0x020
-
-#define AON_RTCCFG      0x040
-#define AON_RTCLO       0x048
-#define AON_RTCHI       0x04C
-#define AON_RTCS        0x050
-#define AON_RTCCMP      0x060
-
-#define AON_BACKUP0     0x080
-#define AON_BACKUP1     0x084
-#define AON_BACKUP2     0x088
-#define AON_BACKUP3     0x08C
-#define AON_BACKUP4     0x090
-#define AON_BACKUP5     0x094
-#define AON_BACKUP6     0x098
-#define AON_BACKUP7     0x09C
-#define AON_BACKUP8     0x0A0
-#define AON_BACKUP9     0x0A4
-#define AON_BACKUP10    0x0A8
-#define AON_BACKUP11    0x0AC
-#define AON_BACKUP12    0x0B0
-#define AON_BACKUP13    0x0B4
-#define AON_BACKUP14    0x0B8
-#define AON_BACKUP15    0x0BC
-
-#define AON_PMUWAKEUPI0 0x100
-#define AON_PMUWAKEUPI1 0x104
-#define AON_PMUWAKEUPI2 0x108
-#define AON_PMUWAKEUPI3 0x10C
-#define AON_PMUWAKEUPI4 0x110
-#define AON_PMUWAKEUPI5 0x114
-#define AON_PMUWAKEUPI6 0x118
-#define AON_PMUWAKEUPI7 0x11C
-#define AON_PMUSLEEPI0  0x120
-#define AON_PMUSLEEPI1  0x124
-#define AON_PMUSLEEPI2  0x128
-#define AON_PMUSLEEPI3  0x12C
-#define AON_PMUSLEEPI4  0x130
-#define AON_PMUSLEEPI5  0x134
-#define AON_PMUSLEEPI6  0x138
-#define AON_PMUSLEEPI7  0x13C
-#define AON_PMUIE       0x140
-#define AON_PMUCAUSE    0x144
-#define AON_PMUSLEEP    0x148
-#define AON_PMUKEY      0x14C
-
-#define AON_LFROSC      0x070
-/* Constants */
-
-#define AON_WDOGKEY_VALUE  0x51F15E
-#define AON_WDOGFEED_VALUE 0xD09F00D
-
-#define AON_WDOGCFG_SCALE       0x0000000F
-#define AON_WDOGCFG_RSTEN       0x00000100
-#define AON_WDOGCFG_ZEROCMP     0x00000200
-#define AON_WDOGCFG_ENALWAYS    0x00001000
-#define AON_WDOGCFG_ENCOREAWAKE 0x00002000
-#define AON_WDOGCFG_CMPIP       0x10000000
-
-#define AON_RTCCFG_SCALE     0x0000000F
-#define AON_RTCCFG_ENALWAYS  0x00001000
-#define AON_RTCCFG_CMPIP     0x10000000
-
-#define AON_WAKEUPCAUSE_RESET   0x00
-#define AON_WAKEUPCAUSE_RTC     0x01
-#define AON_WAKEUPCAUSE_DWAKEUP 0x02
-#define AON_WAKEUPCAUSE_AWAKEUP 0x03
-
-#define AON_RESETCAUSE_POWERON  0x0000
-#define AON_RESETCAUSE_EXTERNAL 0x0100
-#define AON_RESETCAUSE_WATCHDOG 0x0200
-
-#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF
-#define AON_PMUCAUSE_RESETCAUSE  0xFF00
-
-#endif /* _SIFIVE_AON_H */
--- a/include/sifive/devices/clic.h
+++ b/include/sifive/devices/clic.h
@@ -1,30 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_CLIC_H
-#define _SIFIVE_CLIC_H
-
-#define CLIC_HART0          0x00800000
-#define CLIC_MSIP           0x0000
-#define CLIC_MSIP_size      0x4
-#define CLIC_MTIMECMP       0x4000
-#define CLIC_MTIMECMP_size  0x8
-#define CLIC_MTIME          0xBFF8
-#define CLIC_MTIME_size     0x8
-
-#define CLIC_INTIP          0x000
-#define CLIC_INTIE          0x400
-#define CLIC_INTCFG         0x800
-#define CLIC_CFG            0xc00
-
-// These interrupt IDs are consistent across old and new mtvec modes
-#define SSIPID              1
-#define MSIPID              3
-#define STIPID              5
-#define MTIPID              7
-#define SEIPID              9
-#define MEIPID              11
-#define CSIPID              12
-#define LOCALINTIDBASE      16
-
-
-#endif /* _SIFIVE_CLIC_H */ 
--- a/include/sifive/devices/clint.h
+++ b/include/sifive/devices/clint.h
@@ -1,14 +0,0 @@
-// See LICENSE for license details
-
-#ifndef _SIFIVE_CLINT_H
-#define _SIFIVE_CLINT_H
-
-
-#define CLINT_MSIP 0x0000
-#define CLINT_MSIP_size   0x4
-#define CLINT_MTIMECMP 0x4000
-#define CLINT_MTIMECMP_size 0x8
-#define CLINT_MTIME 0xBFF8
-#define CLINT_MTIME_size 0x8
-
-#endif /* _SIFIVE_CLINT_H */ 
--- a/include/sifive/devices/gpio.h
+++ b/include/sifive/devices/gpio.h
@@ -1,24 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_GPIO_H
-#define _SIFIVE_GPIO_H
-
-#define GPIO_INPUT_VAL  (0x00)
-#define GPIO_INPUT_EN   (0x04)
-#define GPIO_OUTPUT_EN  (0x08)
-#define GPIO_OUTPUT_VAL (0x0C)
-#define GPIO_PULLUP_EN  (0x10)
-#define GPIO_DRIVE      (0x14)
-#define GPIO_RISE_IE    (0x18)
-#define GPIO_RISE_IP    (0x1C)
-#define GPIO_FALL_IE    (0x20)
-#define GPIO_FALL_IP    (0x24)
-#define GPIO_HIGH_IE    (0x28)
-#define GPIO_HIGH_IP    (0x2C)
-#define GPIO_LOW_IE     (0x30)
-#define GPIO_LOW_IP     (0x34)
-#define GPIO_IOF_EN     (0x38)
-#define GPIO_IOF_SEL    (0x3C)
-#define GPIO_OUTPUT_XOR    (0x40)
-
-#endif /* _SIFIVE_GPIO_H */
--- a/include/sifive/devices/otp.h
+++ b/include/sifive/devices/otp.h
@@ -1,23 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_OTP_H
-#define _SIFIVE_OTP_H
-
-/* Register offsets */
-
-#define OTP_LOCK         0x00
-#define OTP_CK           0x04
-#define OTP_OE           0x08
-#define OTP_SEL          0x0C
-#define OTP_WE           0x10
-#define OTP_MR           0x14
-#define OTP_MRR          0x18
-#define OTP_MPP          0x1C
-#define OTP_VRREN        0x20
-#define OTP_VPPEN        0x24
-#define OTP_A            0x28
-#define OTP_D            0x2C
-#define OTP_Q            0x30
-#define OTP_READ_TIMINGS 0x34
-
-#endif
--- a/include/sifive/devices/plic.h
+++ b/include/sifive/devices/plic.h
@@ -1,31 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef PLIC_H
-#define PLIC_H
-
-//#include <sifive/const.h>
-
-// 32 bits per source
-#define PLIC_PRIORITY_OFFSET            _AC(0x0000,UL)
-#define PLIC_PRIORITY_SHIFT_PER_SOURCE  2
-// 1 bit per source (1 address)
-#define PLIC_PENDING_OFFSET             _AC(0x1000,UL)
-#define PLIC_PENDING_SHIFT_PER_SOURCE   0
-
-//0x80 per target
-#define PLIC_ENABLE_OFFSET              _AC(0x2000,UL)
-#define PLIC_ENABLE_SHIFT_PER_TARGET    7
-
-
-#define PLIC_THRESHOLD_OFFSET           _AC(0x200000,UL)
-#define PLIC_CLAIM_OFFSET               _AC(0x200004,UL)
-#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
-#define PLIC_CLAIM_SHIFT_PER_TARGET     12
-
-#define PLIC_MAX_SOURCE                 1023
-#define PLIC_SOURCE_MASK                0x3FF
-
-#define PLIC_MAX_TARGET                 15871
-#define PLIC_TARGET_MASK                0x3FFF
-
-#endif /* PLIC_H */
--- a/include/sifive/devices/prci.h
+++ b/include/sifive/devices/prci.h
@@ -1,56 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_PRCI_H
-#define _SIFIVE_PRCI_H
-
-/* Register offsets */
-
-#define PRCI_HFROSCCFG   (0x0000)
-#define PRCI_HFXOSCCFG   (0x0004)
-#define PRCI_PLLCFG      (0x0008)
-#define PRCI_PLLDIV      (0x000C)
-#define PRCI_PROCMONCFG  (0x00F0)
-
-/* Fields */
-#define ROSC_DIV(x)    (((x) & 0x2F) << 0 ) 
-#define ROSC_TRIM(x)   (((x) & 0x1F) << 16)
-#define ROSC_EN(x)     (((x) & 0x1 ) << 30) 
-#define ROSC_RDY(x)    (((x) & 0x1 ) << 31)
-
-#define XOSC_EN(x)     (((x) & 0x1) << 30)
-#define XOSC_RDY(x)    (((x) & 0x1) << 31)
-
-#define PLL_R(x)       (((x) & 0x7)  << 0)
-// single reserved bit for F LSB.
-#define PLL_F(x)       (((x) & 0x3F) << 4)
-#define PLL_Q(x)       (((x) & 0x3)  << 10)
-#define PLL_SEL(x)     (((x) & 0x1)  << 16)
-#define PLL_REFSEL(x)  (((x) & 0x1)  << 17)
-#define PLL_BYPASS(x)  (((x) & 0x1)  << 18)
-#define PLL_LOCK(x)    (((x) & 0x1)  << 31)
-
-#define PLL_R_default 0x1
-#define PLL_F_default 0x1F
-#define PLL_Q_default 0x3
-
-#define PLL_REFSEL_HFROSC 0x0
-#define PLL_REFSEL_HFXOSC 0x1
-
-#define PLL_SEL_HFROSC 0x0
-#define PLL_SEL_PLL    0x1
-
-#define PLL_FINAL_DIV(x)      (((x) & 0x3F) << 0)
-#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8)
-
-#define PROCMON_DIV(x)   (((x) & 0x1F) << 0)
-#define PROCMON_TRIM(x)  (((x) & 0x1F) << 8)
-#define PROCMON_EN(x)    (((x) & 0x1)  << 16)
-#define PROCMON_SEL(x)   (((x) & 0x3)  << 24)
-#define PROCMON_NT_EN(x) (((x) & 0x1)  << 28)
-
-#define PROCMON_SEL_HFCLK     0
-#define PROCMON_SEL_HFXOSCIN  1
-#define PROCMON_SEL_PLLOUTDIV 2
-#define PROCMON_SEL_PROCMON   3
-
-#endif // _SIFIVE_PRCI_H
--- a/include/sifive/devices/pwm.h
+++ b/include/sifive/devices/pwm.h
@@ -1,37 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_PWM_H
-#define _SIFIVE_PWM_H
-
-/* Register offsets */
-
-#define PWM_CFG   0x00
-#define PWM_COUNT 0x08
-#define PWM_S     0x10
-#define PWM_CMP0  0x20
-#define PWM_CMP1  0x24
-#define PWM_CMP2  0x28
-#define PWM_CMP3  0x2C
-
-/* Constants */
-
-#define PWM_CFG_SCALE       0x0000000F
-#define PWM_CFG_STICKY      0x00000100
-#define PWM_CFG_ZEROCMP     0x00000200
-#define PWM_CFG_DEGLITCH    0x00000400
-#define PWM_CFG_ENALWAYS    0x00001000
-#define PWM_CFG_ONESHOT     0x00002000
-#define PWM_CFG_CMP0CENTER  0x00010000
-#define PWM_CFG_CMP1CENTER  0x00020000
-#define PWM_CFG_CMP2CENTER  0x00040000
-#define PWM_CFG_CMP3CENTER  0x00080000
-#define PWM_CFG_CMP0GANG    0x01000000
-#define PWM_CFG_CMP1GANG    0x02000000
-#define PWM_CFG_CMP2GANG    0x04000000
-#define PWM_CFG_CMP3GANG    0x08000000
-#define PWM_CFG_CMP0IP      0x10000000
-#define PWM_CFG_CMP1IP      0x20000000
-#define PWM_CFG_CMP2IP      0x40000000
-#define PWM_CFG_CMP3IP      0x80000000
-
-#endif /* _SIFIVE_PWM_H */
--- a/include/sifive/devices/spi.h
+++ b/include/sifive/devices/spi.h
@@ -1,80 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_SPI_H
-#define _SIFIVE_SPI_H
-
-/* Register offsets */
-
-#define SPI_REG_SCKDIV          0x00
-#define SPI_REG_SCKMODE         0x04
-#define SPI_REG_CSID            0x10
-#define SPI_REG_CSDEF           0x14
-#define SPI_REG_CSMODE          0x18
-
-#define SPI_REG_DCSSCK          0x28
-#define SPI_REG_DSCKCS          0x2a
-#define SPI_REG_DINTERCS        0x2c
-#define SPI_REG_DINTERXFR       0x2e
-
-#define SPI_REG_FMT             0x40
-#define SPI_REG_TXFIFO          0x48
-#define SPI_REG_RXFIFO          0x4c
-#define SPI_REG_TXCTRL          0x50
-#define SPI_REG_RXCTRL          0x54
-
-#define SPI_REG_FCTRL           0x60
-#define SPI_REG_FFMT            0x64
-
-#define SPI_REG_IE              0x70
-#define SPI_REG_IP              0x74
-
-/* Fields */
-
-#define SPI_SCK_PHA             0x1
-#define SPI_SCK_POL             0x2
-
-#define SPI_FMT_PROTO(x)        ((x) & 0x3)
-#define SPI_FMT_ENDIAN(x)       (((x) & 0x1) << 2)
-#define SPI_FMT_DIR(x)          (((x) & 0x1) << 3)
-#define SPI_FMT_LEN(x)          (((x) & 0xf) << 16)
-
-/* TXCTRL register */
-#define SPI_TXWM(x)             ((x) & 0xffff)
-/* RXCTRL register */
-#define SPI_RXWM(x)             ((x) & 0xffff)
-
-#define SPI_IP_TXWM             0x1
-#define SPI_IP_RXWM             0x2
-
-#define SPI_FCTRL_EN            0x1
-
-#define SPI_INSN_CMD_EN         0x1
-#define SPI_INSN_ADDR_LEN(x)    (((x) & 0x7) << 1)
-#define SPI_INSN_PAD_CNT(x)     (((x) & 0xf) << 4)
-#define SPI_INSN_CMD_PROTO(x)   (((x) & 0x3) << 8)
-#define SPI_INSN_ADDR_PROTO(x)  (((x) & 0x3) << 10)
-#define SPI_INSN_DATA_PROTO(x)  (((x) & 0x3) << 12)
-#define SPI_INSN_CMD_CODE(x)    (((x) & 0xff) << 16)
-#define SPI_INSN_PAD_CODE(x)    (((x) & 0xff) << 24)
-
-#define SPI_TXFIFO_FULL  (1 << 31)   
-#define SPI_RXFIFO_EMPTY (1 << 31)   
-
-/* Values */
-
-#define SPI_CSMODE_AUTO         0
-#define SPI_CSMODE_HOLD         2
-#define SPI_CSMODE_OFF          3
-
-#define SPI_DIR_RX              0
-#define SPI_DIR_TX              1
-
-#define SPI_PROTO_S             0
-#define SPI_PROTO_D             1
-#define SPI_PROTO_Q             2
-
-#define SPI_ENDIAN_MSB          0
-#define SPI_ENDIAN_LSB          1
-
-
-#endif /* _SIFIVE_SPI_H */
--- a/include/sifive/devices/uart.h
+++ b/include/sifive/devices/uart.h
@@ -1,27 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_UART_H
-#define _SIFIVE_UART_H
-
-/* Register offsets */
-#define UART_REG_TXFIFO         0x00
-#define UART_REG_RXFIFO         0x04
-#define UART_REG_TXCTRL         0x08
-#define UART_REG_RXCTRL         0x0c
-#define UART_REG_IE             0x10
-#define UART_REG_IP             0x14
-#define UART_REG_DIV            0x18
-
-/* TXCTRL register */
-#define UART_TXEN               0x1
-#define UART_TXWM(x)            (((x) & 0xffff) << 16)
-
-/* RXCTRL register */
-#define UART_RXEN               0x1
-#define UART_RXWM(x)            (((x) & 0xffff) << 16)
-
-/* IP register */
-#define UART_IP_TXWM            0x1
-#define UART_IP_RXWM            0x2
-
-#endif /* _SIFIVE_UART_H */
--- a/include/sifive/smp.h
+++ b/include/sifive/smp.h
@@ -1,65 +0,0 @@
-#ifndef SIFIVE_SMP
-#define SIFIVE_SMP
-
-// The maximum number of HARTs this code supports
-#ifndef MAX_HARTS
-#define MAX_HARTS 32
-#endif
-#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
-
-// The hart that non-SMP tests should run on
-#ifndef NONSMP_HART
-#define NONSMP_HART 0
-#endif
-
-/* If your test cannot handle multiple-threads, use this: 
- *   smp_disable(reg1)
- */
-#define smp_disable(reg1, reg2)			 \
-  csrr reg1, mhartid				;\
-  li   reg2, NONSMP_HART			;\
-  beq  reg1, reg2, hart0_entry			;\
-42:						;\
-  wfi    					;\
-  j 42b						;\
-hart0_entry:
-
-/* If your test needs to temporarily block multiple-threads, do this:
- *    smp_pause(reg1, reg2)
- *    ... single-threaded work ...
- *    smp_resume(reg1, reg2)
- *    ... multi-threaded work ...
- */
-
-#define smp_pause(reg1, reg2)	 \
-  li reg2, 0x8			;\
-  csrw mie, reg2		;\
-  csrr reg2, mhartid		;\
-  bnez reg2, 42f
-
-#define smp_resume(reg1, reg2)	 \
-  li reg1, CLINT_CTRL_ADDR	;\
-41:				;\
-  li reg2, 1			;\
-  sw reg2, 0(reg1)		;\
-  addi reg1, reg1, 4		;\
-  li reg2, CLINT_END_HART_IPI	;\
-  blt reg1, reg2, 41b		;\
-42:				;\
-  wfi    			;\
-  csrr reg2, mip		;\
-  andi reg2, reg2, 0x8		;\
-  beqz reg2, 42b		;\
-  li reg1, CLINT_CTRL_ADDR	;\
-  csrr reg2, mhartid		;\
-  slli reg2, reg2, 2		;\
-  add reg2, reg2, reg1		;\
-  sw zero, 0(reg2)		;\
-41:				;\
-  lw reg2, 0(reg1)		;\
-  bnez reg2, 41b		;\
-  addi reg1, reg1, 4		;\
-  li reg2, CLINT_END_HART_IPI	;\
-  blt reg1, reg2, 41b
-
-#endif
--- a/libwrap/CMakeLists.txt
+++ b/libwrap/CMakeLists.txt
@@ -1,55 +1,41 @@
-
-IF(NOT DEFINED _MK_LIBWRAP)
-
-SET(_MK_LIBWRAP TRUE)
-
-SET(LIBWRAP_DIR ${CMAKE_CURRENT_LIST_DIR})
-
-SET(LIBWRAP_SRCS
-    ${LIBWRAP_DIR}/stdlib/malloc.c
-    ${LIBWRAP_DIR}/sys/open.c
-    ${LIBWRAP_DIR}/sys/lseek.c
-    ${LIBWRAP_DIR}/sys/read.c
-    ${LIBWRAP_DIR}/sys/write.c
-    ${LIBWRAP_DIR}/sys/fstat.c
-    ${LIBWRAP_DIR}/sys/stat.c
-    ${LIBWRAP_DIR}/sys/close.c
-    ${LIBWRAP_DIR}/sys/link.c
-    ${LIBWRAP_DIR}/sys/unlink.c
-    ${LIBWRAP_DIR}/sys/execve.c
-    ${LIBWRAP_DIR}/sys/fork.c
-    ${LIBWRAP_DIR}/sys/getpid.c
-    ${LIBWRAP_DIR}/sys/kill.c
-    ${LIBWRAP_DIR}/sys/wait.c
-    ${LIBWRAP_DIR}/sys/isatty.c
-    ${LIBWRAP_DIR}/sys/times.c
-    ${LIBWRAP_DIR}/sys/sbrk.c
-    ${LIBWRAP_DIR}/sys/_exit.c
-    ${LIBWRAP_DIR}/misc/write_hex.c
-    ${LIBWRAP_DIR}/sys/printf.c
-    ${LIBWRAP_DIR}/sys/puts.c
+include(CMakePrintHelpers)
+set(LIB_SOURCES
+    sys/_exit.c
+    sys/close.c
+    sys/execve.c
+    sys/fork.c
+    sys/fstat.c
+    sys/getpid.c
+    sys/isatty.c
+    sys/kill.c
+    sys/link.c
+    sys/lseek.c
+    sys/open.c
+    sys/openat.c
+    sys/printf.c
+    sys/puts.c
+    sys/read.c
+    sys/sbrk.c
+    sys/stat.c
+    sys/times.c
+    sys/unlink.c
+    sys/wait.c
+    sys/write.c    
+    # Standard library
+    stdlib/malloc.c    
+    # Miscellaneous
+    misc/write_hex.c
 )
-IF(${SEMIHOSTING})
-    SET(LIBWRAP_SRCS ${LIBWRAP_SRCS} ${LIBWRAP_DIR}/semihosting/semihosting.c ${LIBWRAP_DIR}/semihosting/trap.c)
-ENDIF()
+set(WRAP_ARGS "")
+foreach(FILE ${LIB_SOURCES})
+    get_filename_component(DIR ${FILE} DIRECTORY)
+    if(NOT DIR STREQUAL "misc")
+    get_filename_component(BASE_NAME ${FILE} NAME_WE)
+    list(APPEND WRAP_ARGS "LINKER:--wrap=${BASE_NAME}")
+    endif()
+endforeach()

-SET(LIBWRAP_SYMS malloc free open lseek read write fstat stat close link unlink execve fork getpid jukk wait isatty times sbrk _exit printf puts)
-# Includes
-INCLUDE_DIRECTORIES(
-    ${LIBWRAP_DIR}
-    ${LIBWRAP_DIR}/../include
-    ${LIBWRAP_DIR}/../drivers
-    ${LIBWRAP_DIR}/../env
-    ${LIBWRAP_DIR}/../env/iss
-)
+add_library(wrap STATIC ${LIB_SOURCES} ../env/${BOARD}/bsp_write.c ../env/${BOARD}/bsp_read.c)
+target_include_directories(wrap PUBLIC ../include)
+target_link_options(wrap INTERFACE ${WRAP_ARGS})

-ADD_LIBRARY(LIBWRAP_TGC STATIC ${LIBWRAP_SRCS})
-TARGET_COMPILE_OPTIONS(LIBWRAP_TGC PRIVATE -march=${RISCV_ARCH}_zicsr_zifencei -mabi=${RISCV_ABI} "-DBOARD_${BOARD}")
-
-FOREACH(SYM ${LIBWRAP_SYMS})
-    LIST(APPEND WRAP_LDFLAGS "-Wl,--wrap=${SYM}")
-ENDFOREACH()
-
-SET(LIBWRAP_TGC_LDFLAGS ${WRAP_LDFLAGS} "-Wl,--start-group" "-Wl,--end-group" "-L. -lLIBWRAP_TGC")
-
-ENDIF(NOT DEFINED _MK_LIBWRAP)
--- a/libwrap/misc/write_hex.c
+++ b/libwrap/misc/write_hex.c
@@ -2,18 +2,16 @@

 #include <stdint.h>
 #include <unistd.h>
-#include "platform.h"

-void write_hex(int fd, uint32_t hex)
-{
+void write_hex(int fd, uint32_t hex) {
  uint8_t ii;
  uint8_t jj;
  char towrite;
-  write(fd , "0x", 2);
-  for (ii = 8 ; ii > 0; ii--) {
+  write(fd, "0x", 2);
+  for (ii = 8; ii > 0; ii--) {
    jj = ii - 1;
-    uint8_t digit = ((hex & (0xF << (jj*4))) >> (jj*4));
-    towrite = digit < 0xA ? ('0' + digit) : ('A' +  (digit - 0xA));
+    uint8_t digit = ((hex & (0xF << (jj * 4))) >> (jj * 4));
+    towrite = digit < 0xA ? ('0' + digit) : ('A' + (digit - 0xA));
    write(fd, &towrite, 1);
  }
 }
--- a/libwrap/sys/_exit.c
+++ b/libwrap/sys/_exit.c
@@ -1,7 +1,7 @@
 /* See LICENSE of license details. */

-#include "platform.h"
 #include "weak_under_alias.h"
+#include <stdint.h>
 #include <unistd.h>
 #if defined(SEMIHOSTING)
 #include "semihosting.h"
@@ -16,21 +16,17 @@ extern volatile uint32_t fromhost;
 #endif

 void write_hex(int fd, uint32_t hex);
+extern void __libc_fini_array(void);

 void __wrap_exit(int code) {
-  /*#if defined(SEMIHOSTING)
-    sh_exit();
-    return;
-  #endif*/
-  // volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET);
+#ifndef HAVE_NO_INIT_FINI
+  __libc_fini_array();
+#endif
  const char message[] = "\nProgam has exited with code:";
-  //*leds = (~(code));
-
  write(STDERR_FILENO, message, sizeof(message) - 1);
  write_hex(STDERR_FILENO, code);
  write(STDERR_FILENO, "\n", 1);
-  tohost = code + 1;
-  write(STDERR_FILENO, "\x04", 1);
+  tohost = (code << 1) + 1;
  for (;;)
    ;
 }
--- a/libwrap/sys/puts.c
+++ b/libwrap/sys/puts.c
@@ -1,45 +1,15 @@
-/* See LICENSE of license details. */
-
-#include <errno.h>
-#include <stdint.h>
-#include <sys/types.h>
+#include "weak_under_alias.h"
+#include <string.h>
 #include <unistd.h>

-#include "platform.h"
-#include "stub.h"
-#include "weak_under_alias.h"
-#if defined(SEMIHOSTING)
-#include "semihosting.h"
-#endif
+extern ssize_t _bsp_write(int, const void*, size_t);

-int __wrap_puts(const char *s) {
-#if defined(SEMIHOSTING)
-  sh_write0(s);
-  return 0;
-#endif
-  while (*s != '\0') {
-#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
-    while (get_uart_rx_tx_reg_tx_free(uart) == 0)
-      ;
-    uart_write(uart, *s);
-#elif defined(BOARD_iss)
-    *((uint32_t *)0xFFFF0000) = *s;
-#elif defined(BOARD_TGCP)
-    // TODO: implement
-#else
-    while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
-      ;
-    UART0_REG(UART_REG_TXFIFO) = *s;
-
-    if (*s == '\n') {
-      while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
-        ;
-      UART0_REG(UART_REG_TXFIFO) = '\r';
-    }
-#endif
-    ++s;
-  }
-
-  return 0;
+int __wrap_puts(const char* s) {    
+     if(!s) return -1;
+     const char* str = s;
+     while(*str) 
+          ++str;
+     *(char*)str='\n';
+     return _bsp_write(STDOUT_FILENO, s, (str - s)+1);   
 }
-weak_under_alias(puts);
+    weak_under_alias(puts);
--- a/libwrap/sys/read.c
+++ b/libwrap/sys/read.c
@@ -1,62 +1,10 @@
-/* See LICENSE of license details. */
-
-#include <errno.h>
-#include <stdint.h>
-#include <sys/types.h>
+#include "weak_under_alias.h"
 #include <unistd.h>

-#include "platform.h"
-#include "stub.h"
-#include "weak_under_alias.h"
-#if defined(SEMIHOSTING)
-#include "semihosting.h"
-#endif
+extern ssize_t _bsp_read(int fd, void *ptr, size_t len);

 ssize_t __wrap_read(int fd, void *ptr, size_t len) {
-  uint8_t *current = (uint8_t *)ptr;
-#if defined(SEMIHOSTING)
-  int i = sh_read(current, fd, len);
-  return i;
-#endif
-#if defined(BOARD_hifive1)
-  volatile uint32_t *uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
-  volatile uint8_t *uart_rx_cnt =
-      (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
-#elif defined(BOARD_iss)
-  volatile uint32_t *uart_rx = (uint32_t *)0xFFFF0000;
-#elif defined(BOARD_TGCP)
-  // TODO: implement
-#elif !defined(BOARD_ehrenberg) && !defined(BOARD_tgc_vp)
-  volatile uint32_t *uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO);
-  volatile uint8_t *uart_rx_cnt =
-      (uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2);
-#endif
-  ssize_t result = 0;
-  if (isatty(fd)) {
-#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
-    for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len) &&
-                                   (get_uart_rx_tx_reg_rx_avail(uart) > 0);
-         current++) {
-      *current = uart_read(uart);
-      result++;
-    }
-#elif defined(BOARD_iss)
-    for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len);
-         current++) {
-      *current = *uart_rx;
-      result++;
-    }
-#elif defined(BOARD_TGCP)
-    // TODO: implement
-#else
-    for (current = (uint8_t *)ptr;
-         (current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0); current++) {
-      *current = *uart_rx;
-      result++;
-    }
-#endif
-    return result;
-  }
-  return _stub(EBADF);
+  return _bsp_read(fd, ptr, len);
 }
+
 weak_under_alias(read);
--- a/libwrap/sys/write.c
+++ b/libwrap/sys/write.c
@@ -1,72 +1,9 @@
-/* See LICENSE of license details. */
-
-#include <errno.h>
-#include <stdint.h>
-#include <sys/types.h>
-#include <unistd.h>
-#include <stdint.h>
-
-#include "platform.h"
-#include "stub.h"
 #include "weak_under_alias.h"
-#if defined(SEMIHOSTING)
-#include "semihosting.h"
-#endif
-
-extern uint32_t tohost;
+#include <stdint.h>
+#include <unistd.h>

+extern ssize_t _bsp_write(int, const void *, size_t);
 ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
-  const uint8_t *current = (const uint8_t *)ptr;
-#if defined(SEMIHOSTING)
-  if (isatty(fd)) {
-    for (size_t jj = 0; jj < len; jj++) {
-      sh_writec(current[jj]);
-    }
-    return len;
-  } else {
-    sh_write(current, fd);
-    return len;
-  }
-  // return len;
-#elif defined(BOARD_iss)
-  volatile uint64_t payload[4];
-  payload[0]= 64;
-  payload[1]= 0;
-  payload[2]= (uintptr_t)ptr;
-  payload[3]= len;
-  tohost = (uint32_t)payload;
-  return len;
-#endif
-  if (isatty(fd)) {
-    for (size_t jj = 0; jj < len; jj++) {
-#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
-      while (get_uart_rx_tx_reg_tx_free(uart) == 0)
-        ;
-      uart_write(uart, current[jj]);
-      if (current[jj] == '\n') {
-        while (get_uart_rx_tx_reg_tx_free(uart) == 0)
-          ;
-        uart_write(uart, '\r');
-      }
-#elif defined(BOARD_iss)
-      // *((uint32_t *)0xFFFF0000) = current[jj];
-#elif defined(BOARD_TGCP)
-      // TODO: implement
-#else
-      while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
-        ;
-      UART0_REG(UART_REG_TXFIFO) = current[jj];
-
-      if (current[jj] == '\n') {
-        while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
-          ;
-        UART0_REG(UART_REG_TXFIFO) = '\r';
-      }
-#endif
-    }
-    return len;
-  }
-
-  return _stub(EBADF);
+  return _bsp_write(fd, ptr, len);
 }
 weak_under_alias(write);
Author	SHA1	Message	Date
Hongyu Liu	fced281870	adds terminator to char str in wrap_puts	2025-10-24 10:05:55 +02:00
Eyck Jentzsch	703fbf67b4	fixes ROM location	2025-09-15 21:02:23 +02:00
Eyck Jentzsch	59d0a22738	adapts riscv-vp rom to implementation	2025-09-15 20:52:50 +02:00
Eyck Jentzsch	3df19468e9	corrects XIP start addr in risc-v vp	2025-09-14 14:55:23 +02:00
Eyck Jentzsch	bf0e4ec057	extends and relocates ISS RAM	2025-09-12 08:32:47 +02:00
Eyck-Alexander Jentzsch	018e07ecee	removes duplicate 'inline' statement	2025-08-22 15:34:32 +02:00
Eyck-Alexander Jentzsch	fc37441911	corrects setting of mtimecmp in aclint to be as recommended in the spec	2025-08-21 11:47:58 +02:00
Eyck Jentzsch	b5cee82f3e	adds rom linker script	2025-07-30 06:36:41 +02:00
Eyck Jentzsch	20161cc1af	adds RISCV-VP platform	2025-07-30 06:35:53 +02:00
Eyck Jentzsch	0843d92878	adds platform dir to link dirs to find linker script includes	2025-07-30 06:33:58 +02:00
Eyck Jentzsch	a7b4e7b715	fixes moonlight memory layout in link.lds	2025-07-15 07:40:39 +02:00
Hongyu Liu	b69fd19910	updates the flash/ram ORIGIN so that 64bit works	2025-07-04 18:56:29 +02:00
Eyck Jentzsch	25306948c9	Merge branch 'develop' of https://git.minres.com/Firmware/MNRS-BM-BSP.git into develop	2025-07-04 13:18:12 +02:00
Eyck Jentzsch	74fd5b0a2b	replaces strlen function in puts in case not libc is used	2025-07-04 13:16:50 +02:00
Eyck-Alexander Jentzsch	ca36d3ef84	makes no-warn-rwx-segments check if compiler has the option	2025-06-17 19:42:16 +02:00
Eyck-Alexander Jentzsch	a33b51a708	makes start.S, entry.S and link.lds configurable	2025-05-26 20:18:10 +02:00
Eyck Jentzsch	82bd81bb60	move fromhost/tohost for moonlight into ram	2025-05-23 20:24:31 +02:00
Eyck Jentzsch	5353d7d258	fixes a race condition when reading qspi data register	2025-05-23 20:24:02 +02:00
Eyck Jentzsch	b9e5f33cb6	re-applies latest moonlight changes	2025-05-23 20:23:23 +02:00
Eyck-Alexander Jentzsch	99c6214381	changes ISS linker map: moves .srodata to .rodata and increases RAM and stacksize	2025-05-23 10:36:01 +02:00
Eyck-Alexander Jentzsch	6e2a7a12fe	cleans up_exit, adds call to C++ destructors	2025-05-23 09:32:09 +02:00
Eyck-Alexander Jentzsch	2bde14a398	corrects BoardBase in libwrap, as it is only Board now	2025-05-22 17:47:11 +02:00
Eyck-Alexander Jentzsch	f37242efa7	Merge branch 'cmake_flow' into develop	2025-05-22 12:19:52 +02:00
Eyck-Alexander Jentzsch	41d38e698d	cleans up bsp read and write for ISS	2025-05-22 12:10:25 +02:00
Eyck-Alexander Jentzsch	92d01b9db4	adds check for testbench to CMakeList	2025-05-22 12:10:07 +02:00
Hongyu Liu	540397494a	updates CMAKE_C_FLAGS set	2025-04-15 14:30:48 +02:00
Hongyu Liu	853d1c33ec	updates to-/fromhost in link.lds	2025-04-15 12:19:32 +02:00
Eyck Jentzsch	e0807b8cdd	moves to-/fromhost declaration into platform	2025-04-14 17:00:41 +02:00
Eyck Jentzsch	8cb34baacf	moves to-/fromhost past the end of the RAM	2025-04-14 16:34:10 +02:00
Hongyu Liu	db3a2d68d6	adds rv64gc.cmake	2025-04-11 15:37:34 +02:00
Eyck-Alexander Jentzsch	38246a05ce	makes all inline functions static to make building w/o optimization possible	2025-03-28 23:05:08 +01:00
Eyck-Alexander Jentzsch	c3d9e5fa6f	adds proper device based r/w to tgc_vp	2025-03-28 23:03:53 +01:00
Eyck-Alexander Jentzsch	3b95d0a7cd	removes unused build components	2025-03-28 23:03:24 +01:00
Eyck-Alexander Jentzsch	427f8e8b0b	updates tgc_vp by adding bsp specific r/w and updates platform.h paths	2025-03-28 19:03:56 +01:00
Eyck-Alexander Jentzsch	890d4478a3	adds bsp write and read for rtl	2025-03-24 08:28:56 +01:00
Hongyu Liu	7d55172d51	updates the bsp_write and exit	2025-03-21 16:05:01 +01:00
Hongyu Liu	ada4881d33	disables compiler opt for bsp_write in release	2025-03-14 17:51:55 +01:00
Hongyu Liu	3042e0e124	uses tohost in bsp_write	2025-03-11 11:42:28 +01:00
Hongyu Liu	8bb7365819	changes the order of sdata and srodata	2025-03-11 11:35:06 +01:00
Eyck-Alexander Jentzsch	c83b10df38	corrects puts in libwrap	2025-01-17 13:16:49 +01:00
Eyck-Alexander Jentzsch	24b64bce3e	re-adds symbolic link for tgc_vp	2025-01-16 11:17:54 +01:00
Eyck-Alexander Jentzsch	fbe6560e79	makes bsp standalone library	2025-01-16 11:09:40 +01:00
Eyck-Alexander Jentzsch	0464b3b589	adds malloc to libwrap CMake	2025-01-16 11:09:20 +01:00
Eyck-Alexander Jentzsch	242c506e41	ammends toolchainfile	2025-01-07 11:01:22 +01:00
Eyck-Alexander Jentzsch	0a3b25cc6d	updates Make build system with new Board specific writes	2025-01-07 10:45:02 +01:00
Eyck-Alexander Jentzsch	4d15523a74	removes -g switch from toolchain file as it gets set when using Debug anyway, this way it wont be in Release or others	2025-01-06 20:47:03 +01:00
Eyck-Alexander Jentzsch	e652e59dac	removes platform dependency in libwrap	2025-01-06 20:45:20 +01:00
Eyck-Alexander Jentzsch	6cd7ea887a	removes unused CMakeLists	2025-01-06 20:23:10 +01:00
Eyck-Alexander Jentzsch	cef1036169	adds board specific read for iss, changes read implementation	2025-01-06 20:21:21 +01:00
Eyck-Alexander Jentzsch	d9692688b6	changes puts functionality to use new board specific write	2025-01-06 20:20:48 +01:00
Eyck-Alexander Jentzsch	2c063fe9a4	adds toolchain file	2025-01-06 20:19:52 +01:00
Eyck-Alexander Jentzsch	32ff23709f	splits write.c, adds iss implementation and adds CMake build system	2025-01-06 20:19:05 +01:00
Eyck-Alexander Jentzsch	bace1c31c1	moves semihosting away from libwrap	2025-01-06 20:17:40 +01:00
Eyck-Alexander Jentzsch	790379cd78	moves testbench implementations	2025-01-06 20:17:05 +01:00
Eyck-Alexander Jentzsch	7ea13b8993	removes SiFive from bsp	2025-01-06 20:16:29 +01:00
Eyck-Alexander Jentzsch	9ff9727bd6	replaces ehrenberg with new implementations	2025-01-06 20:15:44 +01:00
Hongyu Liu	f419b1a3e6	first version of working cmake	2024-12-20 14:27:45 +01:00
Hongyu Liu	32b9cc78b4	adds first version of cmake	2024-12-17 12:32:21 +01:00