Merge remote-tracking branch 'origin/develop' into main

This commit is contained in:
Stanislaw Kaushanski 2024-04-17 08:27:23 +02:00
commit 87dc0ec230
9 changed files with 87 additions and 555 deletions

View File

@ -1 +0,0 @@
/*.o

116
env/tgc-vp/init.c vendored
View File

@ -1,116 +0,0 @@
#include <stdint.h>
#include <stdio.h>
#include <unistd.h>
#include "platform.h"
#include "encoding.h"
extern int main(int argc, char** argv);
extern void trap_entry();
static unsigned long mtime_lo(void)
{
unsigned long ret;
__asm volatile("rdtime %0":"=r"(ret));
return ret;
}
#if __riscv_xlen==32
static uint32_t mtime_hi(void)
{
unsigned long ret;
__asm volatile("rdtimeh %0":"=r"(ret));
return ret;
}
uint64_t get_timer_value()
{
while (1) {
uint32_t hi = mtime_hi();
uint32_t lo = mtime_lo();
if (hi == mtime_hi())
return ((uint64_t)hi << 32) | lo;
}
}
#elif __riscv_xlen==64
uint64_t get_timer_value()
{
return mtime_lo();
}
#endif
unsigned long get_timer_freq()
{
return 32768;
}
unsigned long get_cpu_freq()
{
return 10000000;
}
void init_pll(void){
}
static void uart_init(size_t baud_rate)
{
GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
}
#ifdef USE_PLIC
extern void handle_m_ext_interrupt();
#endif
#ifdef USE_M_TIME
extern void handle_m_time_interrupt();
#endif
uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
{
if (0){
#ifdef USE_PLIC
// External Machine-Level interrupt from PLIC
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
handle_m_ext_interrupt();
#endif
#ifdef USE_M_TIME
// External Machine-Level interrupt from PLIC
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
handle_m_time_interrupt();
#endif
}
else {
write(1, "trap\n", 5);
_exit(1 + mcause);
}
return epc;
}
void _init()
{
#ifndef NO_INIT
init_pll();
uart_init(115200);
printf("core freq at %d Hz\n", get_cpu_freq());
write_csr(mtvec, &trap_entry);
if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
}
#endif
}
void _fini()
{
}

223
env/tgc-vp/link.lds vendored
View File

@ -1,223 +0,0 @@
OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
{
flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 512M
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 128K
}
PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
ram PT_NULL;
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
.init ORIGIN(flash) :
{
KEEP (*(SORT_NONE(.init)))
*crt0.o(.text .text.*)
} >flash AT>flash :flash
.text :
{
*(.text.init)
*(.text.unlikely .text.*_unlikely .text.unlikely.*)
*(.text.exit .text.exit.*)
*(.text.startup .text.startup.*)
*(.text.hot .text.hot.*)
*(.text .text.*)
*(.stub)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >flash AT>flash :flash
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata :
{
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
} >flash AT>flash :flash
. = ALIGN(4);
/* Thread Local Storage sections */
.tdata :
{
PROVIDE_HIDDEN (__tdata_start = .);
*(.tdata .tdata.* .gnu.linkonce.td.*)
} >flash AT>flash :flash
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >flash AT>flash :flash
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >flash AT>flash :flash
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >flash AT>flash :flash
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >flash AT>flash :flash
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >flash AT>flash :flash
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >flash AT>flash :flash
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >flash AT>flash :flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.srodata :
{
PROVIDE( _gp = . + 0x800 );
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
.data :
{
*(.data .data.*)
*(.gnu.linkonce.d.*)
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
.bss :
{
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >ram AT>ram :ram
. = ALIGN(8);
__BSS_END__ = .;
PROVIDE( _end = . );
PROVIDE( end = . );
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram :ram
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/* DWARF Extension. */
.debug_macro 0 : { *(.debug_macro) }
.debug_addr 0 : { *(.debug_addr) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
}

127
env/tgc-vp/platform.h vendored
View File

@ -1,127 +0,0 @@
// See LICENSE for license details.
#ifndef _ISS_PLATFORM_H
#define _ISS_PLATFORM_H
// Some things missing from the official encoding.h
#define MCAUSE_INT 0x80000000
#define MCAUSE_CAUSE 0x7FFFFFFF
#include "bits.h"
#include "tgc-vp/devices/aon.h"
#include "tgc-vp/devices/clint.h"
#include "tgc-vp/devices/gpio.h"
#include "tgc-vp/devices/otp.h"
#include "tgc-vp/devices/plic.h"
#include "tgc-vp/devices/prci.h"
#include "tgc-vp/devices/pwm.h"
#include "tgc-vp/devices/spi.h"
#include "tgc-vp/devices/uart.h"
/****************************************************************************
* Platform definitions
*****************************************************************************/
// Memory map
#define MASKROM_BASE_ADDR _AC(0x00001000,UL)
#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL)
#define OTP_MMAP_ADDR _AC(0x00020000,UL)
#define CLINT_BASE_ADDR _AC(0x02000000,UL)
#define PLIC_BASE_ADDR _AC(0x0C000000,UL)
#define AON_BASE_ADDR _AC(0x10000000,UL)
#define PRCI_BASE_ADDR _AC(0x10008000,UL)
#define OTP_BASE_ADDR _AC(0x10010000,UL)
#define GPIO_BASE_ADDR _AC(0x10012000,UL)
#define UART0_BASE_ADDR _AC(0x10013000,UL)
#define SPI0_BASE_ADDR _AC(0x10014000,UL)
#define PWM0_BASE_ADDR _AC(0x10015000,UL)
#define UART1_BASE_ADDR _AC(0x10023000,UL)
#define SPI1_BASE_ADDR _AC(0x10024000,UL)
#define PWM1_BASE_ADDR _AC(0x10025000,UL)
#define SPI2_BASE_ADDR _AC(0x10034000,UL)
#define PWM2_BASE_ADDR _AC(0x10035000,UL)
#define SPI0_MMAP_ADDR _AC(0x20000000,UL)
#define MEM_BASE_ADDR _AC(0x80000000,UL)
// IOF masks
#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
#define SPI11_NUM_SS (4)
#define IOF_SPI1_SS0 (2u)
#define IOF_SPI1_SS1 (8u)
#define IOF_SPI1_SS2 (9u)
#define IOF_SPI1_SS3 (10u)
#define IOF_SPI1_MOSI (3u)
#define IOF_SPI1_MISO (4u)
#define IOF_SPI1_SCK (5u)
#define IOF_SPI1_DQ0 (3u)
#define IOF_SPI1_DQ1 (4u)
#define IOF_SPI1_DQ2 (6u)
#define IOF_SPI1_DQ3 (7u)
#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
#define SPI2_NUM_SS (1)
#define IOF_SPI2_SS0 (26u)
#define IOF_SPI2_MOSI (27u)
#define IOF_SPI2_MISO (28u)
#define IOF_SPI2_SCK (29u)
#define IOF_SPI2_DQ0 (27u)
#define IOF_SPI2_DQ1 (28u)
#define IOF_SPI2_DQ2 (30u)
#define IOF_SPI2_DQ3 (31u)
//#define IOF0_I2C_MASK _AC(0x00003000,UL)
#define IOF0_UART0_MASK _AC(0x00030000, UL)
#define IOF_UART0_RX (16u)
#define IOF_UART0_TX (17u)
#define IOF0_UART1_MASK _AC(0x03000000, UL)
#define IOF_UART1_RX (24u)
#define IOF_UART1_TX (25u)
#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
#define IOF1_PWM1_MASK _AC(0x00780000, UL)
#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
// Interrupt numbers
#define INT_RESERVED 0
#define INT_WDOGCMP 1
#define INT_RTCCMP 2
#define INT_UART0_BASE 3
#define INT_UART1_BASE 4
#define INT_SPI0_BASE 5
#define INT_SPI1_BASE 6
#define INT_SPI2_BASE 7
#define INT_GPIO_BASE 8
#define INT_PWM0_BASE 40
#define INT_PWM1_BASE 44
#define INT_PWM2_BASE 48
// Helper functions
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset)
#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset)
#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset)
#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset)
#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset)
#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset)
#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset)
#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset)
#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset)
#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset)
#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset)
#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset)
#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset)
#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset)
// Misc
#include <stdint.h>
void init_pll(void);
unsigned long get_cpu_freq(void);
unsigned long get_timer_freq(void);
uint64_t get_timer_value(void);
#endif /* _ISS_PLATFORM_H */

1
env/tgc_vp vendored Symbolic link
View File

@ -0,0 +1 @@
ehrenberg/

View File

@ -1,20 +1,18 @@
#ifndef _BSP_TIMER_H #ifndef _BSP_TIMER_H
#define _BSP_TIMER_H #define _BSP_TIMER_H
#include <stdint.h>
#include "gen/Apb3Timer.h" #include "gen/Apb3Timer.h"
#include <stdint.h>
#define timer_t apb3timer_t inline void prescaler_init(apb3timer_t *reg, uint16_t value) {
inline void prescaler_init(timer_t* reg, uint16_t value){
set_timer_prescaler(reg, value); set_timer_prescaler(reg, value);
} }
inline void timer_t0__init(timer_t *reg){ inline void timer_t0__init(apb3timer_t *reg) {
set_timer_t0_overflow(reg, 0xffffffff); set_timer_t0_overflow(reg, 0xffffffff);
} }
inline void timer_t1__init(timer_t *reg){ inline void timer_t1__init(apb3timer_t *reg) {
set_timer_t1_overflow(reg, 0xffffffff); set_timer_t1_overflow(reg, 0xffffffff);
} }

View File

@ -1,30 +1,32 @@
/* See LICENSE of license details. */ /* See LICENSE of license details. */
#include <stdint.h>
#include <errno.h> #include <errno.h>
#include <unistd.h> #include <stdint.h>
#include <sys/types.h> #include <sys/types.h>
#include <unistd.h>
#include "platform.h" #include "platform.h"
#include "stub.h" #include "stub.h"
#include "weak_under_alias.h" #include "weak_under_alias.h"
int __wrap_puts(const char *s) int __wrap_puts(const char *s) {
{
while (*s != '\0') { while (*s != '\0') {
#if defined(BOARD_ehrenberg) #if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
while (get_uart_rx_tx_reg_tx_free(uart)==0) ; while (get_uart_rx_tx_reg_tx_free(uart) == 0)
;
uart_write(uart, *s); uart_write(uart, *s);
#elif defined(BOARD_iss) #elif defined(BOARD_iss)
*((uint32_t *)0xFFFF0000) = *s; *((uint32_t *)0xFFFF0000) = *s;
#elif defined(BOARD_TGCP) #elif defined(BOARD_TGCP)
// TODO: implement // TODO: implement
#else #else
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
;
UART0_REG(UART_REG_TXFIFO) = *s; UART0_REG(UART_REG_TXFIFO) = *s;
if (*s == '\n') { if (*s == '\n') {
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
;
UART0_REG(UART_REG_TXFIFO) = '\r'; UART0_REG(UART_REG_TXFIFO) = '\r';
} }
#endif #endif

View File

@ -1,42 +1,39 @@
/* See LICENSE of license details. */ /* See LICENSE of license details. */
#include <stdint.h>
#include <errno.h>
#include <unistd.h>
#include <sys/types.h>
#if defined(BOARD_ehrenberg)
#include "platform.h"
#endif
#include "platform.h" #include "platform.h"
#include "stub.h" #include "stub.h"
#include "weak_under_alias.h" #include "weak_under_alias.h"
#include <errno.h>
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
ssize_t __wrap_read(int fd, void* ptr, size_t len) ssize_t __wrap_read(int fd, void *ptr, size_t len) {
{
uint8_t *current = (uint8_t *)ptr; uint8_t *current = (uint8_t *)ptr;
#if defined(BOARD_hifive1) #if defined(BOARD_hifive1)
volatile uint32_t *uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO); volatile uint32_t *uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2); volatile uint8_t *uart_rx_cnt =
(uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
#elif defined(BOARD_iss) #elif defined(BOARD_iss)
volatile uint32_t *uart_rx = (uint32_t *)0xFFFF0000; volatile uint32_t *uart_rx = (uint32_t *)0xFFFF0000;
#elif defined(BOARD_TGCP) #elif defined(BOARD_TGCP)
// TODO: implement // TODO: implement
#elif !defined(BOARD_ehrenberg) #elif !defined(BOARD_ehrenberg) && !defined(BOARD_tgc_vp)
volatile uint32_t *uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO); volatile uint32_t *uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO);
volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2); volatile uint8_t *uart_rx_cnt =
(uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2);
#endif #endif
ssize_t result = 0; ssize_t result = 0;
if (isatty(fd)) { if (isatty(fd)) {
#if defined(BOARD_ehrenberg) #if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
for (current = (uint8_t *)ptr; for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len) &&
(current < ((uint8_t *)ptr) + len) && (get_uart_rx_tx_reg_rx_avail(uart) > 0); (get_uart_rx_tx_reg_rx_avail(uart) > 0);
current++) { current++) {
*current = uart_read(uart); *current = uart_read(uart);
result++; result++;
} }
#elif defined(BOARD_iss) #elif defined(BOARD_iss)
for (current = (uint8_t *)ptr; for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len);
(current < ((uint8_t *)ptr) + len);
current++) { current++) {
*current = *uart_rx; *current = *uart_rx;
result++; result++;
@ -45,8 +42,7 @@ ssize_t __wrap_read(int fd, void* ptr, size_t len)
// TODO: implement // TODO: implement
#else #else
for (current = (uint8_t *)ptr; for (current = (uint8_t *)ptr;
(current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0); (current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0); current++) {
current ++) {
*current = *uart_rx; *current = *uart_rx;
result++; result++;
} }
@ -56,4 +52,3 @@ ssize_t __wrap_read(int fd, void* ptr, size_t len)
return _stub(EBADF); return _stub(EBADF);
} }
weak_under_alias(read); weak_under_alias(read);

View File

@ -1,33 +1,36 @@
/* See LICENSE of license details. */ /* See LICENSE of license details. */
#include <stdint.h>
#include <errno.h> #include <errno.h>
#include <unistd.h> #include <stdint.h>
#include <sys/types.h> #include <sys/types.h>
#include <unistd.h>
#include "platform.h" #include "platform.h"
#include "stub.h" #include "stub.h"
#include "weak_under_alias.h" #include "weak_under_alias.h"
ssize_t __wrap_write(int fd, const void* ptr, size_t len) ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
{
const uint8_t *current = (const uint8_t *)ptr; const uint8_t *current = (const uint8_t *)ptr;
if (isatty(fd)) { if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) { for (size_t jj = 0; jj < len; jj++) {
#if defined(BOARD_ehrenberg) #if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
while (get_uart_rx_tx_reg_tx_free(uart)==0) ; while (get_uart_rx_tx_reg_tx_free(uart) == 0)
;
uart_write(uart, current[jj]); uart_write(uart, current[jj]);
if (current[jj] == '\n') { if (current[jj] == '\n') {
while (get_uart_rx_tx_reg_tx_free(uart)==0) ; while (get_uart_rx_tx_reg_tx_free(uart) == 0)
;
uart_write(uart, '\r'); uart_write(uart, '\r');
} }
#elif defined(BOARD_iss) #elif defined(BOARD_iss)
*((uint32_t*) 0xFFFF0000) = current[jj]; *((uint32_t*) 0xFFFF0000) = current[jj];
#else #else
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
;
UART0_REG(UART_REG_TXFIFO) = current[jj]; UART0_REG(UART_REG_TXFIFO) = current[jj];
if (current[jj] == '\n') { if (current[jj] == '\n') {
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
;
UART0_REG(UART_REG_TXFIFO) = '\r'; UART0_REG(UART_REG_TXFIFO) = '\r';
} }
#endif #endif