MNRS-BM-BSP/include/ehrenberg/devices/gen/i2s.h

/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-09-10 14:29:50 UTC 
* by peakrdl_mnrs version 1.2.9
*/

#ifndef _BSP_I2S_H
#define _BSP_I2S_H

#include <stdint.h>

typedef struct {
    volatile uint32_t LEFT_CH;
    volatile uint32_t RIGHT_CH;
    volatile uint32_t CONTROL;
    volatile uint32_t STATUS;
    volatile uint32_t I2S_CLOCK_CTRL;
    volatile uint32_t PDM_CLOCK_CTRL;
    volatile uint32_t IE;
    volatile uint32_t IP;
}i2s_t;

#define I2S_LEFT_CH_OFFS 0
#define I2S_LEFT_CH_MASK 0xffffffff
#define I2S_LEFT_CH(V) ((V & I2S_LEFT_CH_MASK) << I2S_LEFT_CH_OFFS)

#define I2S_RIGHT_CH_OFFS 0
#define I2S_RIGHT_CH_MASK 0xffffffff
#define I2S_RIGHT_CH(V) ((V & I2S_RIGHT_CH_MASK) << I2S_RIGHT_CH_OFFS)

#define I2S_CONTROL_MODE_OFFS 0
#define I2S_CONTROL_MODE_MASK 0x3
#define I2S_CONTROL_MODE(V) ((V & I2S_CONTROL_MODE_MASK) << I2S_CONTROL_MODE_OFFS)

#define I2S_CONTROL_DISABLE_LEFT_OFFS 2
#define I2S_CONTROL_DISABLE_LEFT_MASK 0x1
#define I2S_CONTROL_DISABLE_LEFT(V) ((V & I2S_CONTROL_DISABLE_LEFT_MASK) << I2S_CONTROL_DISABLE_LEFT_OFFS)

#define I2S_CONTROL_DISABLE_RIGHT_OFFS 3
#define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1
#define I2S_CONTROL_DISABLE_RIGHT(V) ((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS)

#define I2S_CONTROL_IS_MASTER_OFFS 4
#define I2S_CONTROL_IS_MASTER_MASK 0x1
#define I2S_CONTROL_IS_MASTER(V) ((V & I2S_CONTROL_IS_MASTER_MASK) << I2S_CONTROL_IS_MASTER_OFFS)

#define I2S_CONTROL_SAMPLE_SIZE_OFFS 5
#define I2S_CONTROL_SAMPLE_SIZE_MASK 0x3
#define I2S_CONTROL_SAMPLE_SIZE(V) ((V & I2S_CONTROL_SAMPLE_SIZE_MASK) << I2S_CONTROL_SAMPLE_SIZE_OFFS)

#define I2S_CONTROL_PDM_SCALE_OFFS 7
#define I2S_CONTROL_PDM_SCALE_MASK 0x7
#define I2S_CONTROL_PDM_SCALE(V) ((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS)

#define I2S_STATUS_ENABLED_OFFS 0
#define I2S_STATUS_ENABLED_MASK 0x1
#define I2S_STATUS_ENABLED(V) ((V & I2S_STATUS_ENABLED_MASK) << I2S_STATUS_ENABLED_OFFS)

#define I2S_STATUS_ACTIVE_OFFS 1
#define I2S_STATUS_ACTIVE_MASK 0x1
#define I2S_STATUS_ACTIVE(V) ((V & I2S_STATUS_ACTIVE_MASK) << I2S_STATUS_ACTIVE_OFFS)

#define I2S_STATUS_LEFT_AVAIL_OFFS 2
#define I2S_STATUS_LEFT_AVAIL_MASK 0x1
#define I2S_STATUS_LEFT_AVAIL(V) ((V & I2S_STATUS_LEFT_AVAIL_MASK) << I2S_STATUS_LEFT_AVAIL_OFFS)

#define I2S_STATUS_RIGHT_AVAIL_OFFS 3
#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
#define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)

#define I2S_I2S_CLOCK_CTRL_OFFS 0
#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
#define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)

#define I2S_PDM_CLOCK_CTRL_OFFS 0
#define I2S_PDM_CLOCK_CTRL_MASK 0x3ff
#define I2S_PDM_CLOCK_CTRL(V) ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS)

#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS)

#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS 1
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS)

#define I2S_IP_LEFT_SAMPLE_AVAIL_OFFS 0
#define I2S_IP_LEFT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IP_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IP_LEFT_SAMPLE_AVAIL_MASK) << I2S_IP_LEFT_SAMPLE_AVAIL_OFFS)

#define I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS 1
#define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)

//I2S_LEFT_CH
inline uint32_t get_i2s_left_ch(volatile i2s_t* reg){
    return (reg->LEFT_CH >> 0) & 0xffffffff;
}

//I2S_RIGHT_CH
inline uint32_t get_i2s_right_ch(volatile i2s_t* reg){
    return (reg->RIGHT_CH >> 0) & 0xffffffff;
}

//I2S_CONTROL
inline uint32_t get_i2s_control(volatile i2s_t* reg){
     return reg->CONTROL;
}
inline void set_i2s_control(volatile i2s_t* reg, uint32_t value){
     reg->CONTROL = value;
}
inline uint32_t get_i2s_control_mode(volatile i2s_t* reg){
    return (reg->CONTROL >> 0) & 0x3;
}
inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value){
    reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg){
    return (reg->CONTROL >> 2) & 0x1;
}
inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value){
    reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg){
    return (reg->CONTROL >> 3) & 0x1;
}
inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value){
    reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
}
inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg){
    return (reg->CONTROL >> 4) & 0x1;
}
inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value){
    reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
}
inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg){
    return (reg->CONTROL >> 5) & 0x3;
}
inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value){
    reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
}
inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg){
    return (reg->CONTROL >> 7) & 0x7;
}
inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){
    reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
}

//I2S_STATUS
inline uint32_t get_i2s_status(volatile i2s_t* reg){
     return reg->STATUS;
}
inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg){
    return (reg->STATUS >> 0) & 0x1;
}
inline uint32_t get_i2s_status_active(volatile i2s_t* reg){
    return (reg->STATUS >> 1) & 0x1;
}
inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg){
    return (reg->STATUS >> 2) & 0x1;
}
inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){
    return (reg->STATUS >> 3) & 0x1;
}

//I2S_I2S_CLOCK_CTRL
inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){
     return reg->I2S_CLOCK_CTRL;
}
inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value){
     reg->I2S_CLOCK_CTRL = value;
}
inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg){
    return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff;
}
inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value){
    reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
}

//I2S_PDM_CLOCK_CTRL
inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg){
     return reg->PDM_CLOCK_CTRL;
}
inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value){
     reg->PDM_CLOCK_CTRL = value;
}
inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg){
    return (reg->PDM_CLOCK_CTRL >> 0) & 0x3ff;
}
inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint16_t value){
    reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0x3ffU << 0)) | (value << 0);
}

//I2S_IE
inline uint32_t get_i2s_ie(volatile i2s_t* reg){
     return reg->IE;
}
inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value){
     reg->IE = value;
}
inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg){
    return (reg->IE >> 0) & 0x1;
}
inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value){
    reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg){
    return (reg->IE >> 1) & 0x1;
}
inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value){
    reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}

//I2S_IP
inline uint32_t get_i2s_ip(volatile i2s_t* reg){
     return reg->IP;
}
inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg){
    return (reg->IP >> 0) & 0x1;
}
inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg){
    return (reg->IP >> 1) & 0x1;
}

#endif /* _BSP_I2S_H */