WIP
This commit is contained in:
parent
70ee11ad3d
commit
749fab2c01
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@ -14,6 +14,6 @@ add_custom_target(fw-dhrystone ALL
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USES_TERMINAL
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USES_TERMINAL
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
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add_custom_target(fw-coremark ALL
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add_custom_target(fw-coremark ALL
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COMMAND make -C ${riscvfw_SOURCE_DIR}/benchmarks/coremark/cm PORT_DIR=../tgc BOARD=${BOARD} ISA=${ISA}
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COMMAND make -C ${riscvfw_SOURCE_DIR}/benchmarks/coremark BOARD=${BOARD} ISA=${ISA}
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USES_TERMINAL
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USES_TERMINAL
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
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@ -1 +1 @@
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Subproject commit 33898756434cc490557540dadbfc9bf1f0626d4d
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Subproject commit 9a78fe247376c056cac0e6f716b8ee2a34f46c1d
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@ -1,3 +1,4 @@
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*.o
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*.o
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*.elf
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*.elf
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*.log
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*.log
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/coremark.*
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@ -0,0 +1,36 @@
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TARGET := coremark
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ISA?=imc
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ITERATIONS?=0
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ASM_SRCS :=
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C_SRCS := core_list_join.c core_main.c core_matrix.c core_state.c core_util.c core_portme.c ee_printf.c
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HEADERS := cm/coremark.h
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vpath %.c cm
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BOARD?=iss
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LINK_TARGET=link
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RISCV_ARCH:=rv32$(ISA)
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ifeq ($(ISA),e)
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RISCV_ABI:=ilp32e
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else
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RISCV_ABI:=ilp32
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endif
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PORT_CFLAGS = -DPERFORMANCE_RUN=1 -DCLOCKS_PER_SEC=10000000 -Wno-pointer-to-int-cast -Wno-int-to-pointer-cast
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PORT_CFLAGS+= -g -O3 -fno-common -funroll-loops -finline-functions -falign-functions=16 -falign-jumps=4 -falign-loops=4 -finline-limit=1000 -fno-if-conversion2 -fselective-scheduling -fno-crossjumping -freorder-blocks-and-partition
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FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
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CFLAGS = $(PORT_CFLAGS) -I. -Icm -DFLAGS_STR=\"$(FLAGS_STR)\"
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CFLAGS += -DITERATIONS=$(ITERATIONS)
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LDFLAGS := -g -Wl,--wrap=scanf -Wl,--wrap=printf -Wl,--wrap=exit -lgcc -lm
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TOOL_DIR=$(dir $(compiler))
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BSP_BASE = ../../bare-metal-bsp
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include $(BSP_BASE)/env/common-gcc.mk
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#riscv64-unknown-elf-gcc -march=rv32imc_zicsr_zifencei -mabi=ilp32 -O3 -DCLOCKS_PER_SEC=10000000 -nostdlib -nostartfiles -nodefaultlibs -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -flto -g -DBOARD_TGCP -I../tgc -I. -DFLAGS_STR=\""-march=rv32imc_zicsr_zifencei -mabi=ilp32 -O3 -DCLOCKS_PER_SEC=10000000 -nostdlib -nostartfiles -nodefaultlibs -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -flto -g -DBOARD_TGCP -DPERFORMANCE_RUN=1 -T ../../../bare-metal-bsp/env/TGCP/link.lds"\" -I../../../bare-metal-bsp/env/TGCP -DITERATIONS=0 -DPERFORMANCE_RUN=1 -c ../tgc/ee_printf.c -o ee_printf.o
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#riscv64-unknown-elf-gcc -march=rv32imc_zicsr_zifencei -mabi=ilp32 -g ./core_list_join.o ./core_main.o ./core_matrix.o ./core_state.o ./core_util.o ./core_portme.o ./ee_printf.o -o ./coremark.elf -T ../../../bare-metal-bsp/env/TGCP/link.lds
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@ -1,104 +0,0 @@
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# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# Original Author: Shay Gal-on
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#File : core_portme.mak
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ISA?=imc
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BOARD?=iss
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RISCV_ARCH:=rv32$(ISA)_zicsr_zifencei
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ifeq ($(ISA),e)
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RISCV_ABI:=ilp32e
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else
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RISCV_ABI:=ilp32
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endif
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BSP_BASE = ../../../bare-metal-bsp
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LINKER_SCRIPT=link.lds
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TRIPLET?=riscv64-unknown-elf
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# Flag : OUTFLAG
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# Use this flag to define how to to get an executable (e.g -o)
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OUTFLAG= -o
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# Flag : CC
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# Use this flag to define compiler to use
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CC = $(TRIPLET)-gcc
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# Flag : LD
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# Use this flag to define compiler to use
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LD = $(TRIPLET)-gcc
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# Flag : AS
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# Use this flag to define compiler to use
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AS = $(TRIPLET)-as
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# Flag : CFLAGS
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# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags"
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PORT_CFLAGS = -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -O3 -DCLOCKS_PER_SEC=10000000 -nostdlib -nostartfiles -nodefaultlibs \
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-funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -flto -g -DBOARD_$(BOARD)
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FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
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CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\" -I$(BSP_BASE)/env/$(BOARD)
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#Flag : LFLAGS_END
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# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts).
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# Note : On certain platforms, the default clock_gettime implementation is supported but requires linking of librt.
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SEPARATE_COMPILE=1
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# Flag : SEPARATE_COMPILE
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# You must also define below how to create an object file, and how to link.
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OBJOUT = -o
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LFLAGS = -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -g
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#--specs=nano.specs -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
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ASFLAGS =
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OFLAG = -o
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COUT = -c
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LFLAGS_END = -T $(BSP_BASE)/env/$(BOARD)/$(LINKER_SCRIPT)
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# Flag : PORT_SRCS
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# Port specific source files can be added here
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# You may also need cvt.c if the fcvt functions are not provided as intrinsics by your compiler!
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PORT_SRCS = $(PORT_DIR)/core_portme.c $(PORT_DIR)/ee_printf.c
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vpath %.c $(PORT_DIR)
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vpath %.s $(PORT_DIR)
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PORT_OBJS = core_portme.o ee_printf.o
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# Flag : LOAD
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# For a simple port, we assume self hosted compile and run, no load needed.
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# Flag : RUN
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# For a simple port, we assume self hosted compile and run, simple invocation of the executable
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LOAD = echo ""
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RUN = echo ""
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OEXT = .o
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EXE = .elf
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$(OPATH)$(PORT_DIR)/%$(OEXT) : %.c
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$(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@
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$(OPATH)%$(OEXT) : %.c
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$(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@
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$(OPATH)$(PORT_DIR)/%$(OEXT) : %.s
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$(AS) $(ASFLAGS) $< $(OBJOUT) $@
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# Target : port_pre% and port_post%
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# For the purpose of this simple port, no pre or post steps needed.
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.PHONY : port_prebuild port_postbuild port_prerun port_postrun port_preload port_postload
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port_pre% port_post% :
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# FLAG : OPATH
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# Path to the output folder. Default - current folder.
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OPATH = ./
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MKDIR = mkdir -p
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dist-clean: clean
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rm -f *.o
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@ -1,241 +0,0 @@
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OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
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OUTPUT_ARCH(riscv)
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MEMORY
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{
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RAM (rwx) : ORIGIN = 0x0, LENGTH = 128M
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}
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ENTRY(_start)
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SECTIONS
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{
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/* Read-only sections, merged into text segment: */
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.interp : { *(.interp) }
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.note.gnu.build-id : { *(.note.gnu.build-id) }
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.hash : { *(.hash) }
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.gnu.hash : { *(.gnu.hash) }
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.rela.dyn :
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*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
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PROVIDE_HIDDEN (__rela_iplt_start = .);
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PROVIDE_HIDDEN (__rela_iplt_end = .);
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}
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{
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{
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} > RAM
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{
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}
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{
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.sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
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.eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) }
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.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) }
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.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }
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.gnu_extab : ONLY_IF_RO { *(.gnu_extab*) }
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/* These sections are generated by the Sun/Oracle C++ compiler. */
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.exception_ranges : ONLY_IF_RO { *(.exception_ranges*) }
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/* Adjust the address for the data segment. We want to adjust up to
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the same address within the page on the next page up. */
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. = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));
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/* Exception handling */
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.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) }
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.gnu_extab : ONLY_IF_RW { *(.gnu_extab) }
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.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
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/* Thread Local Storage sections */
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.tdata :
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{
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PROVIDE_HIDDEN (__tdata_start = .);
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}
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.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
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{
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{
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KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
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{
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doesn't matter which directory crtbegin.o
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KEEP (*crtbegin.o(.ctors))
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KEEP (*crtbegin?.o(.ctors))
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/* We don't want to include the .ctor section from
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end of ctors marker and it must be last */
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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}
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{
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
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KEEP (*(.dtors))
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}
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.jcr : { KEEP (*(.jcr)) }
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.data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) }
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. = DATA_SEGMENT_RELRO_END (0, .);
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.data :
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||||||
{
|
|
||||||
__DATA_BEGIN__ = .;
|
|
||||||
*(.data .data.* .gnu.linkonce.d.*)
|
|
||||||
SORT(CONSTRUCTORS)
|
|
||||||
}
|
|
||||||
.data1 : { *(.data1) }
|
|
||||||
.got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) }
|
|
||||||
/* We want the small data sections together, so single-instruction offsets
|
|
||||||
can access them all, and initialized data all before uninitialized, so
|
|
||||||
we can shorten the on-disk segment size. */
|
|
||||||
.sdata :
|
|
||||||
{
|
|
||||||
__SDATA_BEGIN__ = .;
|
|
||||||
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)
|
|
||||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
|
|
||||||
}
|
|
||||||
_edata = .; PROVIDE (edata = .);
|
|
||||||
. = .;
|
|
||||||
__bss_start = .;
|
|
||||||
.sbss :
|
|
||||||
{
|
|
||||||
*(.dynsbss)
|
|
||||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
|
||||||
*(.scommon)
|
|
||||||
}
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
*(.dynbss)
|
|
||||||
*(.bss .bss.* .gnu.linkonce.b.*)
|
|
||||||
*(COMMON)
|
|
||||||
/* Align here to ensure that the .bss section occupies space up to
|
|
||||||
_end. Align after .bss to ensure correct alignment even if the
|
|
||||||
.bss section disappears because there are no input sections.
|
|
||||||
FIXME: Why do we need it? When there is no .bss section, we do not
|
|
||||||
pad the .data section. */
|
|
||||||
. = ALIGN(. != 0 ? 32 / 8 : 1);
|
|
||||||
}
|
|
||||||
. = ALIGN(32 / 8);
|
|
||||||
. = SEGMENT_START("ldata-segment", .);
|
|
||||||
. = ALIGN(32 / 8);
|
|
||||||
__BSS_END__ = .;
|
|
||||||
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,
|
|
||||||
MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
|
|
||||||
_end = .; PROVIDE (end = .);
|
|
||||||
. = DATA_SEGMENT_END (.);
|
|
||||||
/* Stabs debugging sections. */
|
|
||||||
.stab 0 : { *(.stab) }
|
|
||||||
.stabstr 0 : { *(.stabstr) }
|
|
||||||
.stab.excl 0 : { *(.stab.excl) }
|
|
||||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
|
||||||
.stab.index 0 : { *(.stab.index) }
|
|
||||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
|
||||||
.comment 0 : { *(.comment) }
|
|
||||||
.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
|
|
||||||
/* DWARF debug sections.
|
|
||||||
Symbols in the DWARF debugging sections are relative to the beginning
|
|
||||||
of the section so we begin them at 0. */
|
|
||||||
/* DWARF 1 */
|
|
||||||
.debug 0 : { *(.debug) }
|
|
||||||
.line 0 : { *(.line) }
|
|
||||||
/* GNU DWARF 1 extensions */
|
|
||||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
|
||||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
|
||||||
/* DWARF 1.1 and DWARF 2 */
|
|
||||||
.debug_aranges 0 : { *(.debug_aranges) }
|
|
||||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
|
||||||
/* DWARF 2 */
|
|
||||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
|
||||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
|
||||||
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
|
|
||||||
.debug_frame 0 : { *(.debug_frame) }
|
|
||||||
.debug_str 0 : { *(.debug_str) }
|
|
||||||
.debug_loc 0 : { *(.debug_loc) }
|
|
||||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
|
||||||
/* SGI/MIPS DWARF 2 extensions */
|
|
||||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
|
||||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
|
||||||
.debug_typenames 0 : { *(.debug_typenames) }
|
|
||||||
.debug_varnames 0 : { *(.debug_varnames) }
|
|
||||||
/* DWARF 3 */
|
|
||||||
.debug_pubtypes 0 : { *(.debug_pubtypes) }
|
|
||||||
.debug_ranges 0 : { *(.debug_ranges) }
|
|
||||||
/* DWARF Extension. */
|
|
||||||
.debug_macro 0 : { *(.debug_macro) }
|
|
||||||
.debug_addr 0 : { *(.debug_addr) }
|
|
||||||
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
|
|
||||||
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
|
|
||||||
}
|
|
||||||
Loading…
Reference in New Issue