683 lines
26 KiB
C++
683 lines
26 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Contributors:
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// eyck@minres.com - initial API and implementation
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////////////////////////////////////////////////////////////////////////////////
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#include <iss/iss.h>
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#include <iss/debugger/gdb_session.h>
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#include <easylogging++.h>
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#include <memory>
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#include <cstring>
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#include "iss/vm_base.h"
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#include "iss/arch/CORE_DEF_NAME.h"
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#include "iss/arch/riscv_core.h"
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#include "iss/debugger/server.h"
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#include <boost/format.hpp>
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namespace iss {
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namespace CORE_DEF_NAME {
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using namespace iss::arch;
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using namespace llvm;
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using namespace iss::debugger;
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template<typename ARCH>
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struct vm_impl;
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template<typename ARCH>
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struct target_adapter: public target_adapter_base {
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target_adapter(server_if* srv, vm_impl<ARCH>* vm)
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: target_adapter_base(srv)
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, vm(vm)
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{
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}
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/*============== Thread Control ===============================*/
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/* Set generic thread */
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status set_gen_thread(rp_thread_ref& thread) override;
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/* Set control thread */
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status set_ctrl_thread(rp_thread_ref& thread) override;
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/* Get thread status */
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status is_thread_alive(rp_thread_ref& thread, bool& alive) override;
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/*============= Register Access ================================*/
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/* Read all registers. buf is 4-byte aligned and it is in
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target byte order. If register is not available
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corresponding bytes in avail_buf are 0, otherwise
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avail buf is 1 */
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status read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) override;
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/* Write all registers. buf is 4-byte aligned and it is in target
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byte order */
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status write_registers(const std::vector<uint8_t>& data) override;
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/* Read one register. buf is 4-byte aligned and it is in
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target byte order. If register is not available
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corresponding bytes in avail_buf are 0, otherwise
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avail buf is 1 */
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status read_single_register(unsigned int reg_no, std::vector<uint8_t>& buf, std::vector<uint8_t>& avail_buf) override;
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/* Write one register. buf is 4-byte aligned and it is in target byte
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order */
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status write_single_register(unsigned int reg_no, const std::vector<uint8_t>& buf) override;
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/*=================== Memory Access =====================*/
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/* Read memory, buf is 4-bytes aligned and it is in target
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byte order */
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status read_mem(uint64_t addr, std::vector<uint8_t>& buf) override;
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/* Write memory, buf is 4-bytes aligned and it is in target
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byte order */
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status write_mem(uint64_t addr, const std::vector<uint8_t>& buf) override;
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status process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) override;
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status thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, size_t& num, bool& done) override;
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status current_thread_query(rp_thread_ref& thread) override;
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status offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) override;
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status crc_query(uint64_t addr, size_t len, uint32_t& val) override;
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status raw_query(std::string in_buf, std::string& out_buf) override;
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status threadinfo_query(int first, std::string& out_buf) override;
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status threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) override;
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status packetsize_query(std::string& out_buf) override;
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status add_break(int type, uint64_t addr, unsigned int length) override;
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status remove_break(int type, uint64_t addr, unsigned int length) override;
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status resume_from_addr(bool step, int sig, uint64_t addr) override;
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protected:
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static inline constexpr addr_t map_addr(const addr_t& i){
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return i;
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}
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vm_impl<ARCH>* vm;
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rp_thread_ref thread_idx;
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};
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template<typename ARCH>
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struct vm_impl: public vm::vm_base<ARCH> {
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using super = typename vm::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using addr_t = typename super::addr_t ;
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vm_impl();
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vm_impl(ARCH& core, bool dump=false);
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void enableDebug(bool enable) {
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super::sync_exec=super::ALL_SYNC;
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}
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target_adapter_if* accquire_target_adapter(server_if* srv){
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debugger_if::dbg_enabled=true;
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if(vm::vm_base<ARCH>::tgt_adapter==nullptr)
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vm::vm_base<ARCH>::tgt_adapter=new target_adapter<ARCH>(srv, this);
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return vm::vm_base<ARCH>::tgt_adapter;
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}
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protected:
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template<typename T> inline
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llvm::ConstantInt* size(T type){
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return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
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}
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inline llvm::Value * gen_choose(llvm::Value * cond, llvm::Value * trueVal, llvm::Value * falseVal, unsigned size) const {
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return this->gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
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}
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std::tuple<vm::continuation_e, llvm::BasicBlock*> gen_single_inst_behavior(virt_addr_t&, unsigned int&, llvm::BasicBlock*) override;
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void gen_leave_behavior(llvm::BasicBlock* leave_blk) override;
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void gen_raise_trap(uint16_t trap_id, uint16_t cause);
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void gen_leave_trap(unsigned lvl);
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void gen_wait(unsigned type);
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void gen_trap_behavior(llvm::BasicBlock*) override;
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void gen_trap_check(llvm::BasicBlock* bb);
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inline
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void gen_set_pc(virt_addr_t pc, unsigned reg_num){
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llvm::Value* next_pc_v = this->builder->CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val), this->get_type(traits<ARCH>::XLEN));
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this->builder->CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
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}
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inline
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llvm::Value* get_reg_ptr(unsigned i){
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void* ptr = this->core.get_regs_base_ptr()+traits<ARCH>::reg_byte_offset(i);
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llvm::PointerType* ptrType=nullptr;
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switch (traits<ARCH>::reg_bit_width(i)>>3) {
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case 8:
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ptrType=llvm::Type::getInt64PtrTy(this->mod->getContext());
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break;
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case 4:
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ptrType=llvm::Type::getInt32PtrTy(this->mod->getContext());
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break;
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case 2:
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ptrType=llvm::Type::getInt16PtrTy(this->mod->getContext());
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break;
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case 1:
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ptrType=llvm::Type::getInt8PtrTy(this->mod->getContext());
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break;
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default:
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throw std::runtime_error("unsupported access with");
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break;
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}
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return llvm::ConstantExpr::getIntToPtr(
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llvm::ConstantInt::get(this->mod->getContext(), llvm::APInt(
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8/*bits*/ * sizeof(uint8_t*),
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reinterpret_cast<uint64_t>(ptr)
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)),
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ptrType);
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}
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inline
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void gen_set_pc(virt_addr_t pc){
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llvm::Value* pc_l = this->builder->CreateSExt(this->gen_const(traits<ARCH>::caddr_bit_width, (unsigned)pc), this->get_type(traits<ARCH>::caddr_bit_width));
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super::gen_set_reg(traits<ARCH>::PC, pc_l);
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}
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// some compile time constants
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enum {MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111};
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enum {EXTR_MASK16 = MASK16>>2, EXTR_MASK32 = MASK32>>2};
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enum {LUT_SIZE = 1<< bit_count(EXTR_MASK32), LUT_SIZE_C = 1<<bit_count(EXTR_MASK16)};
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using this_class = vm_impl<ARCH>;
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using compile_func = std::tuple<vm::continuation_e, llvm::BasicBlock*> (this_class::*)(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb);
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compile_func lut[LUT_SIZE];
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std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
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std::array<compile_func, LUT_SIZE> lut_11;
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compile_func* qlut[4];// = {lut_00, lut_01, lut_10, lut_11};
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const uint32_t lutmasks[4]={EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32};
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void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[], compile_func f){
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if(pos<0){
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lut[idx]=f;
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} else {
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auto bitmask = 1UL<<pos;
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if((mask & bitmask)==0){
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expand_bit_mask(pos-1, mask, value, valid, idx, lut, f);
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} else {
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if((valid & bitmask) == 0) {
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expand_bit_mask(pos-1, mask, value, valid, (idx<<1), lut, f);
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expand_bit_mask(pos-1, mask, value, valid, (idx<<1)+1, lut, f);
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} else {
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auto new_val = idx<<1;
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if((value&bitmask)!=0)
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new_val++;
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expand_bit_mask(pos-1, mask, value, valid, new_val, lut, f);
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}
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}
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}
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}
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inline uint32_t extract_fields(uint32_t val){
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return extract_fields(29, val>>2, lutmasks[val&0x3], 0);
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}
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uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val){
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if(pos>=0) {
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auto bitmask = 1UL<<pos;
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if((mask & bitmask)==0){
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lut_val = extract_fields(pos-1, val, mask, lut_val);
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} else {
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auto new_val = lut_val<<1;
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if((val&bitmask)!=0)
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new_val++;
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lut_val = extract_fields(pos-1, val, mask, new_val);
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}
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}
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return lut_val;
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}
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct InstructionDesriptor {
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size_t length;
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uint32_t value;
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uint32_t mask;
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compile_func op;
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};
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/* «start generated code» */
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InstructionDesriptor instr_descr[0] = {};
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/* «end generated code» */
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/****************************************************************************
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* end opcode definitions
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****************************************************************************/
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std::tuple<vm::continuation_e, llvm::BasicBlock*> illegal_intruction(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
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//this->gen_sync(iss::PRE_SYNC);
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this->builder->CreateStore(
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this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
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get_reg_ptr(traits<ARCH>::PC), true);
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this->builder->CreateStore(
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this->builder->CreateAdd(
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this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
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this->gen_const(64U, 1)),
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get_reg_ptr(traits<ARCH>::ICOUNT), true);
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if(this->debugging_enabled()) this->gen_sync(iss::PRE_SYNC);
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pc=pc+((instr&3) == 3?4:2);
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this->gen_raise_trap(0, 2); // illegal instruction trap
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this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
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this->gen_trap_check(this->leave_blk);
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return std::make_tuple(iss::vm::BRANCH, nullptr);
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}
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};
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template<typename CODE_WORD>
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void debug_fn(CODE_WORD insn){
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volatile CODE_WORD x=insn;
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insn=2*x;
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}
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template<typename ARCH>
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vm_impl<ARCH>::vm_impl(){
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this(new ARCH());
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}
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template<typename ARCH>
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vm_impl<ARCH>::vm_impl(ARCH& core, bool dump) : vm::vm_base<ARCH>(core, dump) {
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qlut[0] = lut_00.data();
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qlut[1] = lut_01.data();
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qlut[2] = lut_10.data();
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qlut[3] = lut_11.data();
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for(auto instr: instr_descr){
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auto quantrant = instr.value&0x3;
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expand_bit_mask(29, lutmasks[quantrant], instr.value>>2, instr.mask>>2, 0, qlut[quantrant], instr.op);
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}
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this->sync_exec=static_cast<sync_type>(this->sync_exec|core.needed_sync());
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}
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template<typename ARCH>
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std::tuple<vm::continuation_e, llvm::BasicBlock*> vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t& pc, unsigned int& inst_cnt, llvm::BasicBlock* this_block){
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// we fetch at max 4 byte, alignment is 2
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code_word_t insn = 0;
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iss::addr_t paddr;
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const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
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try {
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uint8_t* const data = (uint8_t*)&insn;
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paddr=this->core.v2p(pc);
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if((pc.val&upper_bits) != ((pc.val+2)&upper_bits)){ // we may cross a page boundary
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auto res = this->core.read_mem(paddr, 2, data);
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if(res!=iss::Ok)
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throw trap_access(1, pc.val);
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if((insn & 0x3) == 0x3){ // this is a 32bit instruction
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res = this->core.read_mem(this->core.v2p(pc+2), 2, data+2);
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}
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} else {
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auto res = this->core.read_mem(paddr, 4, data);
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if(res!=iss::Ok)
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throw trap_access(1, pc.val);
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}
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} catch(trap_access& ta){
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throw trap_access(ta.id, pc.val);
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}
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if(insn==0x0000006f)
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throw vm::simulation_stopped(0);
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// curr pc on stack
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typename vm_impl<ARCH>::processing_pc_entry addr(*this, pc, paddr);
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++inst_cnt;
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auto lut_val = extract_fields(insn);
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auto f = qlut[insn&0x3][lut_val];
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if (f==nullptr){
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f=&this_class::illegal_intruction;
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}
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return (this->*f)(pc, insn, this_block);
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}
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template<typename ARCH>
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void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock* leave_blk){
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this->builder->SetInsertPoint(leave_blk);
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this->builder->CreateRet(this->builder->CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
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}
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template<typename ARCH>
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void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause){
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auto* TRAP_val = this->gen_const(traits<ARCH>::XLEN, 0x80<<24| (cause<<16) | trap_id );
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this->builder->CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
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}
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template<typename ARCH>
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void vm_impl<ARCH>::gen_leave_trap(unsigned lvl){
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std::vector<llvm::Value*> args {
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this->core_ptr,
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llvm::ConstantInt::get(getContext(), llvm::APInt(64, lvl)),
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};
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this->builder->CreateCall(this->mod->getFunction("leave_trap"), args);
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auto* PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl<<8)+0x41, traits<ARCH>::XLEN/8);
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this->builder->CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
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}
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template<typename ARCH>
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void vm_impl<ARCH>::gen_wait(unsigned type){
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std::vector<llvm::Value*> args {
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this->core_ptr,
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llvm::ConstantInt::get(getContext(), llvm::APInt(64, type)),
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};
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this->builder->CreateCall(this->mod->getFunction("wait"), args);
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}
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template<typename ARCH>
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void vm_impl<ARCH>::gen_trap_behavior(llvm::BasicBlock* trap_blk){
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this->builder->SetInsertPoint(trap_blk);
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auto* trap_state_val = this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
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std::vector<llvm::Value*> args {
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this->core_ptr,
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this->adj_to64(trap_state_val),
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this->adj_to64(this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))
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};
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this->builder->CreateCall(this->mod->getFunction("enter_trap"), args);
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auto* trap_addr_val = this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
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this->builder->CreateRet(trap_addr_val);
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}
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template<typename ARCH> inline
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void vm_impl<ARCH>::gen_trap_check(llvm::BasicBlock* bb){
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auto* v = this->builder->CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
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this->gen_cond_branch(
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this->builder->CreateICmp(
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ICmpInst::ICMP_EQ,
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v,
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llvm::ConstantInt::get(getContext(), llvm::APInt(v->getType()->getIntegerBitWidth(), 0))),
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bb,
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this->trap_blk, 1);
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}
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} // namespace CORE_DEF_NAME
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#define CREATE_FUNCS(ARCH) \
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template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, unsigned short port, bool dump) {\
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std::unique_ptr<CORE_DEF_NAME::vm_impl<ARCH> > ret = std::make_unique<CORE_DEF_NAME::vm_impl<ARCH> >(*core, dump);\
|
|
debugger::server<debugger::gdb_session>::run_server(ret.get(), port);\
|
|
return ret;\
|
|
}\
|
|
template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, unsigned short port, bool dump) {\
|
|
return create<ARCH>(new arch::riscv_core<ARCH>(), port, dump); /* FIXME: memory leak!!!!!!! */\
|
|
}\
|
|
template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, bool dump) {\
|
|
return std::make_unique<CORE_DEF_NAME::vm_impl<ARCH> >(*core, dump); /* FIXME: memory leak!!!!!!! */ \
|
|
}\
|
|
template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, bool dump) { \
|
|
return create<ARCH>(new arch::riscv_core<ARCH>(), dump);\
|
|
}
|
|
|
|
CREATE_FUNCS(arch::CORE_DEF_NAME)
|
|
|
|
namespace CORE_DEF_NAME {
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::set_gen_thread(rp_thread_ref& thread) {
|
|
thread_idx=thread;
|
|
return Ok;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::set_ctrl_thread(rp_thread_ref& thread) {
|
|
thread_idx=thread;
|
|
return Ok;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::is_thread_alive(rp_thread_ref& thread, bool& alive) {
|
|
alive=1;
|
|
return Ok;
|
|
}
|
|
|
|
/* List threads. If first is non-zero then start from the first thread,
|
|
* otherwise start from arg, result points to array of threads to be
|
|
* filled out, result size is number of elements in the result,
|
|
* num points to the actual number of threads found, done is
|
|
* set if all threads are processed.
|
|
*/
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num,
|
|
size_t& num, bool& done) {
|
|
if(first==0){
|
|
result.clear();
|
|
result.push_back(thread_idx);
|
|
num=1;
|
|
done=true;
|
|
return Ok;
|
|
} else
|
|
return NotSupported;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::current_thread_query(rp_thread_ref& thread) {
|
|
thread=thread_idx;
|
|
return Ok;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
|
|
LOG(TRACE)<<"reading target registers";
|
|
//return idx<0?:;
|
|
data.clear();
|
|
avail.clear();
|
|
std::vector<uint8_t> reg_data;
|
|
for(size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no){
|
|
auto reg_bit_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no));
|
|
auto reg_width=reg_bit_width/8;
|
|
reg_data.resize(reg_width);
|
|
vm->get_arch()->get_reg(reg_no, reg_data);
|
|
for(size_t j=0; j<reg_data.size(); ++j){
|
|
data.push_back(reg_data[j]);
|
|
avail.push_back(0xff);
|
|
}
|
|
}
|
|
// work around fill with F type registers
|
|
if(arch::traits<ARCH>::NUM_REGS < 65){
|
|
auto reg_width=sizeof(typename arch::traits<ARCH>::reg_t);
|
|
for(size_t reg_no = 0; reg_no < 33; ++reg_no){
|
|
for(size_t j=0; j<reg_width; ++j){
|
|
data.push_back(0x0);
|
|
avail.push_back(0x00);
|
|
}
|
|
}
|
|
}
|
|
return Ok;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::write_registers(const std::vector<uint8_t>& data) {
|
|
size_t data_index=0;
|
|
auto reg_count=arch::traits<ARCH>::NUM_REGS;
|
|
std::vector<uint8_t> reg_data;
|
|
for(size_t reg_no = 0; reg_no < reg_count; ++reg_no){
|
|
auto reg_bit_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no));
|
|
auto reg_width=reg_bit_width/8;
|
|
vm->get_arch()->set_reg(reg_no, std::vector<uint8_t>(data.begin()+data_index, data.begin()+data_index+reg_width));
|
|
data_index+=reg_width;
|
|
}
|
|
return Ok;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
|
|
if(reg_no<65){
|
|
//auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no))/8;
|
|
data.resize(0);
|
|
vm->get_arch()->get_reg(reg_no, data);
|
|
avail.resize(data.size());
|
|
std::fill(avail.begin(), avail.end(), 0xff);
|
|
} else {
|
|
typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_READ, traits<ARCH>::CSR, reg_no-65);
|
|
data.resize(sizeof(typename traits<ARCH>::reg_t));
|
|
avail.resize(sizeof(typename traits<ARCH>::reg_t));
|
|
std::fill(avail.begin(), avail.end(), 0xff);
|
|
vm->get_arch()->read_mem(a, data.size(), data.data());
|
|
}
|
|
return data.size()>0?Ok:Err;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t>& data) {
|
|
if(reg_no<65)
|
|
vm->get_arch()->set_reg(reg_no, data);
|
|
else {
|
|
typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_WRITE, traits<ARCH>::CSR, reg_no-65);
|
|
vm->get_arch()->write_mem(a, data.size(), data.data());
|
|
}
|
|
return Ok;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t>& data) {
|
|
auto a=map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
|
|
auto f = [&]()->status {
|
|
return vm->get_arch()->read_mem(a, data.size(), data.data());
|
|
};
|
|
return srv->execute_syncronized(f);
|
|
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t>& data) {
|
|
auto a=map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
|
|
return srv->execute_syncronized(&arch_if::write_mem, vm->get_arch(), a, data.size(), data.data());
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) {
|
|
return NotSupported;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) {
|
|
text=0;
|
|
data=0;
|
|
bss=0;
|
|
return Ok;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t& val) {
|
|
return NotSupported;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::raw_query(std::string in_buf, std::string& out_buf) {
|
|
return NotSupported;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::threadinfo_query(int first, std::string& out_buf) {
|
|
if(first){
|
|
std::stringstream ss;
|
|
ss<<"m"<<std::hex<<thread_idx.val;
|
|
out_buf=ss.str();
|
|
} else {
|
|
out_buf="l";
|
|
}
|
|
return Ok;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) {
|
|
char buf[20];
|
|
memset(buf, 0, 20);
|
|
sprintf (buf, "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
|
|
out_buf=buf;
|
|
return Ok;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::packetsize_query(std::string& out_buf) {
|
|
out_buf="PacketSize=1000";
|
|
return Ok;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
|
|
auto saddr=map_addr({iss::CODE, iss::PHYSICAL, addr});
|
|
auto eaddr=map_addr({iss::CODE, iss::PHYSICAL, addr+length});
|
|
target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val-saddr.val);
|
|
LOG(TRACE)<<"Adding breakpoint with handle "<<target_adapter_base::bp_count<<" for addr 0x"<<std::hex<<saddr.val<<std::dec;
|
|
LOG(TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
|
|
return Ok;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
|
|
auto saddr=map_addr({iss::CODE, iss::PHYSICAL, addr});
|
|
unsigned handle=target_adapter_base::bp_lut.getEntry(saddr.val);
|
|
// TODO: check length of addr range
|
|
if(handle){
|
|
LOG(TRACE)<<"Removing breakpoint with handle "<<handle<<" for addr 0x"<<std::hex<<saddr.val<<std::dec;
|
|
target_adapter_base::bp_lut.removeEntry(handle);
|
|
LOG(TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
|
|
return Ok;
|
|
}
|
|
LOG(TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
|
|
return Err;
|
|
}
|
|
|
|
template<typename ARCH>
|
|
status target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr) {
|
|
unsigned reg_no = arch::traits<ARCH>::PC;
|
|
std::vector<uint8_t> data(8);
|
|
*(reinterpret_cast<uint64_t*>(&data[0]))=addr;
|
|
vm->get_arch()->set_reg(reg_no, data);
|
|
return resume_from_current(step, sig);
|
|
}
|
|
} // namespace CORE_DEF_NAME
|
|
} // namespace iss
|