DBT-RISE-TGC/incl/iss/arch
Eyck Jentzsch 0aea1d0177 remove mcounteren in M-mode only wrapper 2022-03-27 17:21:46 +02:00
..
.gitignore update names 2021-05-13 15:54:48 +02:00
hwl.h add hardware loop CSR access 2022-03-25 11:33:44 +01:00
riscv_hart_common.h add TCM 2022-03-27 15:38:18 +02:00
riscv_hart_m_p.h remove mcounteren in M-mode only wrapper 2022-03-27 17:21:46 +02:00
riscv_hart_msu_vp.h add hardware loop CSR access 2022-03-25 11:33:44 +01:00
riscv_hart_mu_p.h add TCM 2022-03-27 15:38:18 +02:00
tgc_c.h fix compiler warning for reduced number of registers 2022-03-14 15:38:05 +01:00
tgc_mapper.h add TCM 2022-03-27 15:38:18 +02:00