rework core definitions

gen_input/TGC_B.core_desc

@@ -0,0 +1,16 @@
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
+
+Core TGC_B provides RV32I {
+	architectural_state {
+        unsigned XLEN=32;
+        unsigned PCLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000000000100000000;
+        unsigned PGSIZE = 0x1000; //1 << 12;
+        unsigned PGMASK = 0xfff; //PGSIZE-1
+	}
+}
+

gen_input/TGC_C.core_desc

@@ -0,0 +1,15 @@
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
+
+Core TGC_C provides RV32I, RV32M, RV32IC {
+    architectural_state {
+        unsigned XLEN=32;
+        unsigned PCLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned PGSIZE = 0x1000; //1 << 12;
+        unsigned PGMASK = 0xfff; //PGSIZE-1
+    }
+}

gen_input/TGC_D.core_desc

@@ -0,0 +1,13 @@
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
+
+Core TGC_D provides RV32I, RV32M, RV32IC {
+    architectural_state {
+        unsigned XLEN=32;
+        unsigned PCLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000001000100000100;
+    }
+}

gen_input/TGC_D_XRB_MAC.core_desc

@@ -0,0 +1,73 @@
+import "CoreDSL-Instruction-Set-Description/RISCVBase.core_desc"
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
+
+InstructionSet X_RB_MAC extends RISCVBase {
+  architectural_state {
+    register unsigned<64> ACC;
+  }
+
+  instructions {
+    RESET_ACC { // v-- funct7       v-- funct3
+      encoding: 7'd0 :: 10'b0 :: 3'd0 :: 5'b0 :: 7'b0001011;
+      behavior: ACC = 0;
+    }
+    
+    GET_ACC_LO {
+      encoding: 7'd1 :: 10'b0 :: 3'd0 :: rd[4:0] :: 7'b0001011;
+      behavior: if (rd != 0) X[rd] = ACC[31:0];
+    }
+    
+    GET_ACC_HI {
+      encoding: 7'd2 :: 10'b0 :: 3'd0 :: rd[4:0] :: 7'b0001011;
+      behavior: if (rd != 0) X[rd] = ACC[63:32];
+    }
+    
+    MACU_32 {
+      encoding: 7'd0 :: rs2[4:0] :: rs1[4:0] :: 3'd1 :: 5'b0 :: 7'b0001011;
+      behavior: {
+        unsigned<64> mul = X[rs1]    * X[rs2];
+        unsigned<33> add = mul[31:0] + ACC[31:0];
+        ACC = add[31:0];
+      }
+    }
+    
+    MACS_32 {
+      encoding: 7'd1 :: rs2[4:0] :: rs1[4:0] :: 3'd1 :: 5'b0 :: 7'b0001011;
+      behavior: {
+        signed<64> mul = ((signed) X[rs1])    * ((signed) X[rs2]);
+        signed<33> add = ((signed) mul[31:0]) + ((signed) ACC[31:0]);
+        ACC = add[31:0]; // bit range always yields unsigned type
+      }
+    }
+    
+    MACU_64 {
+      encoding: 7'd0 :: rs2[4:0] :: rs1[4:0] :: 3'd2 :: 5'b0 :: 7'b0001011;
+      behavior: {
+        unsigned<64> mul = X[rs1] * X[rs2];
+        unsigned<65> add = mul    + ACC;
+        ACC = add[63:0];
+      }
+    }
+    
+    MACS_64 {
+      encoding: 7'd1 :: rs2[4:0] :: rs1[4:0] :: 3'd2 :: 5'b0 :: 7'b0001011;
+      behavior: {
+        signed<64> mul = ((signed) X[rs1]) * ((signed) X[rs2]);
+        signed<65> add =           mul     + ((signed) ACC);
+        ACC = add[63:0];
+      }
+    }
+  }
+}
+
+Core TGC_D_XRB_MAC provides RV32I, RV32M, RV32IC, X_RB_MAC {
+    architectural_state {
+        unsigned XLEN=32;
+        unsigned PCLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000001000100000100;
+    }
+}

gen_input/TGFS.core_desc

@@ -1,37 +0,0 @@
-import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
-import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
-import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
-
-Core TGC_B provides RV32I {
-	architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000000000100000000;
-        unsigned PGSIZE = 0x1000; //1 << 12;
-        unsigned PGMASK = 0xfff; //PGSIZE-1
-	}
-}
-
-Core TGC_C provides RV32I, RV32M, RV32IC {
-    architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
-        unsigned PGSIZE = 0x1000; //1 << 12;
-        unsigned PGMASK = 0xfff; //PGSIZE-1
-    }
-}
-
-Core TGC_D provides RV32I, RV32M, RV32IC {
-    architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
-    }
-}