DBT-RISE/DBT-RISE-TGC
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base: DBT-RISE:main
Branches Tags
DBT-RISE:main
DBT-RISE:develop
DBT-RISE:feature/eve_checkin
DBT-RISE:feature/htif
DBT-RISE:feature/iss_factory
DBT-RISE:feature/core_factory
DBT-RISE:Trace_enhancement
DBT-RISE:feature/reduced_output
DBT-RISE:msvc_compat
DBT-RISE:hotfix/latest_scc
DBT-RISE:feature/interpreter
..
compare: DBT-RISE:feature/interpreter
Branches Tags
DBT-RISE:develop
DBT-RISE:feature/eve_checkin
DBT-RISE:main
DBT-RISE:feature/htif
DBT-RISE:feature/iss_factory
DBT-RISE:feature/core_factory
DBT-RISE:Trace_enhancement
DBT-RISE:feature/reduced_output
DBT-RISE:msvc_compat
DBT-RISE:hotfix/latest_scc
DBT-RISE:feature/interpreter

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605 changed files with 100660 additions and 83900 deletions
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13
.clang-format
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@ -1,3 +1,4 @@
---
Language: Cpp
# BasedOnStyle: LLVM
# should be in line with IndentWidth
@ -12,8 +13,8 @@ AllowAllParametersOfDeclarationOnNextLine: true
AllowShortBlocksOnASingleLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: All
AllowShortIfStatementsOnASingleLine: false
AllowShortLoopsOnASingleLine: false
AllowShortIfStatementsOnASingleLine: true
AllowShortLoopsOnASingleLine: true
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
@ -38,8 +39,8 @@ BreakBeforeTernaryOperators: true
BreakConstructorInitializersBeforeComma: true
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: true
ColumnLimit: 140
CommentPragmas: '^( IWYU pragma:| @suppress)'
ColumnLimit: 120
CommentPragmas: '^ IWYU pragma:'
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ConstructorInitializerIndentWidth: 0
ContinuationIndentWidth: 4
@ -75,13 +76,13 @@ PenaltyBreakFirstLessLess: 120
PenaltyBreakString: 1000
PenaltyExcessCharacter: 1000000
PenaltyReturnTypeOnItsOwnLine: 60
PointerAlignment: Left
PointerAlignment: Right
ReflowComments: true
SortIncludes: true
SpaceAfterCStyleCast: false
SpaceAfterTemplateKeyword: true
SpaceBeforeAssignmentOperators: true
SpaceBeforeParens: Never
SpaceBeforeParens: ControlStatements
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: false

5
.gitignore vendored
View File

@ -1,6 +1,5 @@
.DS_Store
/*.il
/.settings
/avr-instr.html
/blink.S
/flash.*
@ -15,6 +14,7 @@
/*.ods
/build*/
/*.logs
language.settings.xml
/*.gtkw
/Debug wo LLVM/
/*.txdb
@ -30,5 +30,4 @@
/.gdbinit
/*.out
/dump.json
/*.yaml
/*.json
/src-gen/

1
.project
View File

@ -23,5 +23,6 @@
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
<nature>org.eclipse.linuxtools.tmf.project.nature</nature>
</natures>
</projectDescription>

73
.settings/org.eclipse.cdt.codan.core.prefs Normal file
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@ -0,0 +1,73 @@
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13
.settings/org.eclipse.cdt.core.prefs Normal file
View File

@ -0,0 +1,13 @@
eclipse.preferences.version=1
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37
.settings/org.eclipse.cdt.managedbuilder.core.prefs Normal file
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@ -0,0 +1,37 @@
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environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/LIBRARY_PATH/delimiter=\:
environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/LIBRARY_PATH/operation=remove
environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true

363
CMakeLists.txt
View File

@ -1,270 +1,147 @@
cmake_minimum_required(VERSION 3.18)
list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake)
cmake_minimum_required(VERSION 3.12)
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/../cmake) # main (top) cmake dir
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake) # project specific cmake dir
# ##############################################################################
#
# ##############################################################################
project(dbt-rise-tgc VERSION 1.0.0)
# CMake useful variables
set(CMAKE_RUNTIME_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/bin")
set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib")
set(CMAKE_LIBRARY_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib")
include(GNUInstallDirs)
include(flink)
# Set the name of your project here
project("riscv")
find_package(elfio QUIET)
find_package(jsoncpp)
find_package(Boost COMPONENTS coroutine REQUIRED)
include(Common)
conan_basic_setup()
find_package(Boost COMPONENTS program_options system thread filesystem REQUIRED)
# This sets the include directory for the reference project. This is the -I flag in gcc.
include_directories(
${PROJECT_SOURCE_DIR}/incl
${SOFTFLOAT_INCLUDE_DIRS}
${LLVM_INCLUDE_DIRS}
)
add_dependent_subproject(dbt-core)
include_directories(
${PROJECT_SOURCE_DIR}/incl
${PROJECT_SOURCE_DIR}/../external/elfio
${PROJECT_SOURCE_DIR}/../external/libGIS
${Boost_INCLUDE_DIRS}
)
# Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH)
set(CMAKE_MACOSX_RPATH ON)
set(CMAKE_SKIP_BUILD_RPATH FALSE)
set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE)
set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib")
set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE)
add_subdirectory(softfloat)
set(LIB_SOURCES
src/iss/plugin/instruction_count.cpp
src/iss/arch/tgc5c.cpp
src/vm/interp/vm_tgc5c.cpp
src/vm/fp_functions.cpp
src/iss/debugger/csr_names.cpp
src/iss/semihosting/semihosting.cpp
)
if(WITH_TCC)
list(APPEND LIB_SOURCES
src/vm/tcc/vm_tgc5c.cpp
)
endif()
if(WITH_LLVM)
list(APPEND LIB_SOURCES
src/vm/llvm/vm_tgc5c.cpp
src/vm/llvm/fp_impl.cpp
)
endif()
if(WITH_ASMJIT)
list(APPEND LIB_SOURCES
src/vm/asmjit/vm_tgc5c.cpp
)
endif()
# library files
FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
FILE(GLOB GEN_YAML_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/contrib/instr/*.yaml)
list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
FILE(GLOB RiscVSCHeaders ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*.h ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*/*.h)
set(LIB_HEADERS ${RiscVSCHeaders} )
set(LIB_SOURCES
#src/iss/rv32gc.cpp
src/iss/rv32imac.cpp
#src/iss/rv64i.cpp
#src/iss/rv64gc.cpp
src/iss/mnrv32.cpp
src/vm/llvm/fp_functions.cpp
src/vm/llvm/vm_mnrv32.cpp
#src/vm/llvm/vm_rv32gc.cpp
#src/vm/llvm/vm_rv32imac.cpp
#src/vm/llvm/vm_rv64i.cpp
#src/vm/llvm/vm_rv64gc.cpp
src/vm/tcc/vm_mnrv32.cpp
src/vm/interp/vm_mnrv32.cpp
src/plugin/instruction_count.cpp
src/plugin/cycle_estimate.cpp)
foreach(FILEPATH ${GEN_ISS_SOURCES})
get_filename_component(CORE ${FILEPATH} NAME_WE)
string(TOUPPER ${CORE} CORE)
list(APPEND LIB_DEFINES CORE_${CORE})
endforeach()
message(STATUS "Core defines are ${LIB_DEFINES}")
if(WITH_LLVM)
FILE(GLOB LLVM_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp)
list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
endif()
if(WITH_TCC)
FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/tcc/vm_*.cpp)
list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
endif()
if(WITH_ASMJIT)
FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/asmjit/vm_*.cpp)
list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
endif()
if(TARGET yaml-cpp::yaml-cpp)
list(APPEND LIB_SOURCES
src/iss/plugin/cycle_estimate.cpp
src/iss/plugin/instruction_count.cpp
)
endif()
# Define two variables in order not to repeat ourselves.
set(LIBRARY_NAME riscv)
# Define the library
add_library(${PROJECT_NAME} SHARED ${LIB_SOURCES})
if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
endif()
target_include_directories(${PROJECT_NAME} PUBLIC src)
target_include_directories(${PROJECT_NAME} PUBLIC src-gen)
target_force_link_libraries(${PROJECT_NAME} PRIVATE dbt-rise-core)
# only re-export the include paths
get_target_property(DBT_CORE_INCL dbt-rise-core INTERFACE_INCLUDE_DIRECTORIES)
target_include_directories(${PROJECT_NAME} INTERFACE ${DBT_CORE_INCL})
get_target_property(DBT_CORE_DEFS dbt-rise-core INTERFACE_COMPILE_DEFINITIONS)
if(NOT(DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND))
target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
endif()
target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine)
if(TARGET yaml-cpp::yaml-cpp)
target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS)
target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp)
endif()
if(WITH_LLVM)
find_package(LLVM)
target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS})
target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS})
if(BUILD_SHARED_LIBS)
target_link_libraries(${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES})
endif()
endif()
set_target_properties(${PROJECT_NAME} PROPERTIES
VERSION ${PROJECT_VERSION}
FRAMEWORK FALSE
add_library(${LIBRARY_NAME} ${LIB_SOURCES})
SET(${LIBRARY_NAME} -Wl,-whole-archive -l${LIBRARY_NAME} -Wl,-no-whole-archive)
target_link_libraries(${LIBRARY_NAME} softfloat dbt-core scc-util)
set_target_properties(${LIBRARY_NAME} PROPERTIES
VERSION ${VERSION} # ${VERSION} was defined in the main CMakeLists.
FRAMEWORK FALSE
PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
)
install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib
RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries
LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib
FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
)
install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss COMPONENT ${PROJECT_NAME}
DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # target directory
FILES_MATCHING # install only matched files
PATTERN "*.h" # select header files
)
install(FILES ${GEN_YAML_SOURCES} DESTINATION share/tgc-vp)
# ##############################################################################
#
# ##############################################################################
set(CMAKE_INSTALL_RPATH $ORIGIN/../${CMAKE_INSTALL_LIBDIR})
project(tgc-sim)
find_package(Boost COMPONENTS program_options thread REQUIRED)
add_executable(${PROJECT_NAME} src/main.cpp)
if(TARGET ${CORE_NAME}_cpp)
list(APPEND TGC_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
else()
FILE(GLOB TGC_SOURCES
${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp
${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp
)
list(APPEND TGC_SOURCES ${GEN_SOURCES})
if(SystemC_FOUND)
set(SC_LIBRARY_NAME riscv_sc)
add_library(${SC_LIBRARY_NAME} src/sysc/core_complex.cpp)
add_definitions(-DWITH_SYSTEMC)
include_directories(${SystemC_INCLUDE_DIRS})
include_directories(${CCI_INCLUDE_DIRS})
if(SCV_FOUND)
add_definitions(-DWITH_SCV)
include_directories(${SCV_INCLUDE_DIRS})
endif()
target_link_libraries(${SC_LIBRARY_NAME} ${LIBRARY_NAME})
target_link_libraries(${SC_LIBRARY_NAME} dbt-core)
target_link_libraries(${SC_LIBRARY_NAME} softfloat)
target_link_libraries(${SC_LIBRARY_NAME} scc)
target_link_libraries(${SC_LIBRARY_NAME} external)
target_link_libraries(${SC_LIBRARY_NAME} ${llvm_libs})
target_link_libraries(${SC_LIBRARY_NAME} ${Boost_LIBRARIES} )
set_target_properties(${SC_LIBRARY_NAME} PROPERTIES
VERSION ${VERSION} # ${VERSION} was defined in the main CMakeLists.
FRAMEWORK FALSE
PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
)
endif()
foreach(F IN LISTS TGC_SOURCES)
if(${F} MATCHES ".*/arch/([^/]*)\.cpp")
string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
endif()
endforeach()
project("riscv-sim")
# if(WITH_LLVM)
# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
# #target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
# endif()
# if(WITH_TCC)
# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
# endif()
target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc fmt::fmt)
# This is a make target, so you can do a "make riscv-sc"
set(APPLICATION_NAME riscv-sim)
if(TARGET Boost::program_options)
target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options)
else()
target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY})
endif()
add_executable(${APPLICATION_NAME} src/main.cpp)
target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS})
if(Tcmalloc_FOUND)
target_link_libraries(${PROJECT_NAME} PUBLIC ${Tcmalloc_LIBRARIES})
# Links the target exe against the libraries
target_link_libraries(${APPLICATION_NAME} ${LIBRARY_NAME})
target_link_libraries(${APPLICATION_NAME} jsoncpp)
target_link_libraries(${APPLICATION_NAME} dbt-core)
target_link_libraries(${APPLICATION_NAME} external)
target_link_libraries(${APPLICATION_NAME} ${llvm_libs})
target_link_libraries(${APPLICATION_NAME} ${Boost_LIBRARIES} )
if (Tcmalloc_FOUND)
target_link_libraries(${APPLICATION_NAME} ${Tcmalloc_LIBRARIES})
endif(Tcmalloc_FOUND)
install(TARGETS tgc-sim
EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib
RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries
LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib
FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
# Says how and where to install software
# Targets:
# * <prefix>/lib/<libraries>
# * header location after install: <prefix>/include/<project>/*.h
# * headers can be included by C++ code `#<project>/Bar.hpp>`
install(TARGETS ${LIBRARY_NAME} ${APPLICATION_NAME}
EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
ARCHIVE DESTINATION lib COMPONENT libs # static lib
RUNTIME DESTINATION bin COMPONENT libs # binaries
LIBRARY DESTINATION lib COMPONENT libs # shared lib
FRAMEWORK DESTINATION bin COMPONENT libs # for mac
PUBLIC_HEADER DESTINATION incl/${PROJECT_NAME} COMPONENT devel # headers for mac (note the different component -> different package)
INCLUDES DESTINATION incl # headers
)
if(BUILD_TESTING)
# ... CMake code to create tests ...
add_test(NAME tgc-sim-interp
COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend interp)
if(WITH_TCC)
add_test(NAME tgc-sim-tcc
COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend tcc)
endif()
if(WITH_LLVM)
add_test(NAME tgc-sim-llvm
COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend llvm)
endif()
if(WITH_ASMJIT)
add_test(NAME tgc-sim-asmjit
COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend asmjit)
endif()
endif()
# ##############################################################################
#
# ##############################################################################
if(TARGET scc-sysc)
project(dbt-rise-tgc_sc VERSION 1.0.0)
set(LIB_SOURCES
src/sysc/core_complex.cpp
src/sysc/register_tgc_c.cpp
)
FILE(GLOB GEN_SC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/sysc/register_*.cpp)
list(APPEND LIB_SOURCES ${GEN_SC_SOURCES})
add_library(${PROJECT_NAME} ${LIB_SOURCES})
target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
# SYSTEM PACKAGING (RPM, TGZ, ...)
# _____________________________________________________________________________
foreach(F IN LISTS TGC_SOURCES)
if(${F} MATCHES ".*/arch/([^/]*)\.cpp")
string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
endif()
endforeach()
#include(CPackConfig)
target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
#
# CMAKE PACKAGING (for other CMake projects to use this one easily)
# _____________________________________________________________________________
# if(WITH_LLVM)
# target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
# endif()
set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
set_target_properties(${PROJECT_NAME} PROPERTIES
VERSION ${PROJECT_VERSION}
FRAMEWORK FALSE
PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
)
install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib
RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries
LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib
FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc # headers for mac (note the different component -> different package)
INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
)
endif()
project(elfio-test)
find_package(Boost COMPONENTS program_options thread REQUIRED)
add_executable(${PROJECT_NAME} src/elfio.cpp)
target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)
#include(PackageConfigurator)

119
CMakeLists.txt.orig Normal file
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@ -0,0 +1,119 @@
cmake_minimum_required(VERSION 3.3)
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake ${CMAKE_CURRENT_SOURCE_DIR}/sc-components/cmake)
set(ENABLE_SCV TRUE CACHE BOOL "Enable use of SCV")
set(ENABLE_SHARED TRUE CACHE BOOL "Build shared libraries")
include(GitFunctions)
get_branch_from_git()
# if we are not on master or develop set the submodules to develop
IF(NOT ${GIT_BRANCH} MATCHES "master")
IF(NOT ${GIT_BRANCH} MATCHES "develop")
message(STATUS "main branch is '${GIT_BRANCH}', setting submodules to 'develop'")
set(GIT_BRANCH develop)
endif()
endif()
### set the directory names of the submodules
set(GIT_SUBMODULES elfio libGIS sc-components dbt-core)
set(GIT_SUBMODULE_DIR_sc-components .)
set(GIT_SUBMODULE_DIR_dbt-core .)
### set each submodules's commit or tag that is to be checked out
### (leave empty if you want master)
#set(GIT_SUBMODULE_VERSION_sc-comp 3af6b9836589b082c19d9131c5d0b7afa8ddd7cd)
set(GIT_SUBMODULE_BRANCH_sc-components ${GIT_BRANCH})
set(GIT_SUBMODULE_BRANCH_dbt-core ${GIT_BRANCH})
include(GNUInstallDirs)
include(Submodules)
include(Conan)
#enable_testing()
set(CMAKE_CXX_STANDARD 14)
set(CMAKE_CXX_STANDARD_REQUIRED ON)
set(CMAKE_CXX_EXTENSIONS OFF)
set(CMAKE_POSITION_INDEPENDENT_CODE ON)
include(CheckCXXCompilerFlag)
CHECK_CXX_COMPILER_FLAG("-march=native" COMPILER_SUPPORTS_MARCH_NATIVE)
if(COMPILER_SUPPORTS_MARCH_NATIVE)
if("${CMAKE_BUILD_TYPE}" STREQUAL "")
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=native")
elseif(NOT(${CMAKE_BUILD_TYPE} STREQUAL "RelWithDebInfo"))
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=native")
endif()
endif()
if ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU" OR "${CMAKE_CXX_COMPILER_ID}" STREQUAL "Clang")
set(warnings "-Wall -Wextra -Werror")
#set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D_GLIBCXX_USE_CXX11_ABI=0")
set(CMAKE_CXX_FLAGS_RELEASE "-O3 -DNDEBUG")
set(CMAKE_C_FLAGS_RELEASE "-O3 -DNDEBUG")
elseif ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
set(warnings "/W4 /WX /EHsc")
endif()
setup_conan()
# This line finds the boost lib and headers.
set(Boost_NO_BOOST_CMAKE ON) # Don't do a find_package in config mode before searching for a regular boost install.
find_package(Boost COMPONENTS program_options system thread filesystem REQUIRED)
if(DEFINED ENV{LLVM_HOME})
find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
endif(DEFINED ENV{LLVM_HOME})
find_package(LLVM REQUIRED CONFIG)
message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
find_package(Threads)
find_package(Tcmalloc)
find_package(ZLIB)
find_package(SystemC)
if(SystemC_FOUND)
message(STATUS "SystemC headers at ${SystemC_INCLUDE_DIRS}")
message(STATUS "SystemC library at ${SystemC_LIBRARY_DIRS}")
if(SCV_FOUND)
message(STATUS "SCV headers at ${SCV_INCLUDE_DIRS}")
message(STATUS "SCV library at ${SCV_LIBRARY_DIRS}")
endif(SCV_FOUND)
if(CCI_FOUND)
message(STATUS "CCI headers at ${CCI_INCLUDE_DIRS}")
message(STATUS "CCI library at ${CCI_LIBRARY_DIRS}")
endif()
endif(SystemC_FOUND)
set(PROJECT_3PARTY_DIRS external)
include(clang-format)
set(ENABLE_CLANG_TIDY OFF CACHE BOOL "Add clang-tidy automatically to builds")
if (ENABLE_CLANG_TIDY)
find_program (CLANG_TIDY_EXE NAMES "clang-tidy" PATHS /usr/local/opt/llvm/bin )
if (CLANG_TIDY_EXE)
message(STATUS "clang-tidy found: ${CLANG_TIDY_EXE}")
set(CLANG_TIDY_CHECKS "-*,modernize-*")
set(CMAKE_CXX_CLANG_TIDY "${CLANG_TIDY_EXE};-checks=${CLANG_TIDY_CHECKS};-header-filter='${CMAKE_SOURCE_DIR}/*';-fix"
CACHE STRING "" FORCE)
else()
message(AUTHOR_WARNING "clang-tidy not found!")
set(CMAKE_CXX_CLANG_TIDY "" CACHE STRING "" FORCE) # delete it
endif()
endif()
# Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0)
set(VERSION_MAJOR "1")
set(VERSION_MINOR "0")
set(VERSION_PATCH "0")
set(VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH})
add_subdirectory(external)
add_subdirectory(dbt-core)
add_subdirectory(sc-components)
add_subdirectory(softfloat)
GET_DIRECTORY_PROPERTY(SOFTFLOAT_INCLUDE_DIRS DIRECTORY softfloat DEFINITION SOFTFLOAT_INCLUDE_DIRS)
add_subdirectory(riscv)
add_subdirectory(platform)
message(STATUS "Build Type: ${CMAKE_BUILD_TYPE}")

16
README.md
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@ -1,16 +1,18 @@
# DBT-RISE-TGFS
Core of an instruction set simulator based on DBT-RISE implementing Minres The Good Folks Series cores. The project is hosted at https://git.minres.com/DBT-RISE/DBT-RISE-TGFS .
# DBT-RISE-RISCV
Core of an instruction set simulator based on DBT-RISE implementing the RISC-V ISA. The project is hosted at https://git.minres.com/DBT-RISE/DBT-RISE-RISCV .
This repo contains only the code of the RISC-V ISS and can only be used with the DBT_RISE. A complete VP using this ISS can be found at https://git.minres.com/VP/Ecosystem-VP ~~which models SiFives FE310 controlling a brushless DC (BLDC) motor~~.
This repo contains only the code of the RISC-V ISS and can only be used with the DBT_RISE. A complete VP using this ISS can be found at https://git.minres.com/VP/RISCV-VP which models SiFives FE310 controlling a brushless DC (BLDC) motor.
This library provide the infrastructure to build RISC-V ISS. Currently part of the library are the following implementations adhering to version 2.2 of the 'The RISC-V Instruction Set Manual Volume I: User-Level ISA':
* RV32I (TGF-B)
* RV32MIC (TGF-C)
* RV32IMAC
* RV32GC
* RC64I
* RV64GC
All pass the respective compliance tests. Along with those ISA implementations there is a wrapper (riscv_hart_m_p.h) implementing the Machine privileged mode as of privileged spec 1.10. The main.cpp in src allows to build a stand-alone ISS when integrated into a top-level project. For further information please have a look at [https://git.minres.com/VP/RISCV-VP](https://git.minres.com/VP/RISCV-VP).
All pass the respective compliance tests. Along with those ISA implementations there is a wrapper implementing the M/S/U modes inlcuding virtual memory management and CSRs as of privileged spec 1.10. The main.cpp in src allows to build a standalone ISS when integrated into a top-level project. For further information please have a look at [https://git.minres.com/VP/RISCV-VP](https://git.minres.com/VP/RISCV-VP).
Last but not least an SystemC wrapper is provided which allows easy integration into SystemC based virtual platforms.
Since DBT-RISE uses a generative approach other needed combinations or custom extension can be generated. For further information please contact [info@minres.com](mailto:info@minres.com).
Since DBT-RISE uses a generative approch other needed combinations or custom extension can be generated. For further information please contact [info@minres.com](mailto:info@minres.com).

35
cmake/flink.cmake
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@ -1,35 +0,0 @@
# according to https://github.com/horance-liu/flink.cmake/tree/master
# SPDX-License-Identifier: Apache-2.0
include(CMakeParseArguments)
function(target_do_force_link_libraries target visibility lib)
if(MSVC)
target_link_libraries(${target} ${visibility} "/WHOLEARCHIVE:${lib}")
elseif(APPLE)
target_link_libraries(${target} ${visibility} -Wl,-force_load ${lib})
else()
target_link_libraries(${target} ${visibility} -Wl,--whole-archive ${lib} -Wl,--no-whole-archive)
endif()
endfunction()
function(target_force_link_libraries target)
cmake_parse_arguments(FLINK
""
""
"PUBLIC;INTERFACE;PRIVATE"
${ARGN}
)
foreach(lib IN LISTS FLINK_PUBLIC)
target_do_force_link_libraries(${target} PUBLIC ${lib})
endforeach()
foreach(lib IN LISTS FLINK_INTERFACE)
target_do_force_link_libraries(${target} INTERFACE ${lib})
endforeach()
foreach(lib IN LISTS FLINK_PRIVATE)
target_do_force_link_libraries(${target} PRIVATE ${lib})
endforeach()
endfunction()

1
contrib/instr/.gitignore vendored
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@ -1 +0,0 @@
/*.yaml

624
contrib/instr/TGC5C_instr.yaml
View File

@ -1,624 +0,0 @@
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branch: false
delay: 1

650
contrib/instr/TGC5C_slow.yaml
View File

@ -1,650 +0,0 @@
RV32I:
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index: 42
mask: 28799
size: 32
CSRRWI:
branch: false
delay: 1
encoding: 20595
index: 45
mask: 28799
size: 32
Zifencei:
FENCE_I:
attributes:
- - name:flush
branch: false
delay: 1
encoding: 4111
index: 48
mask: 28799
size: 32

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/results
/cwr
/*.xml

43
contrib/pa/README.md
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# Notes
* requires conan version 1.59
* requires decent cmake version 3.23
Setup for tcsh:
```
git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
cd TGC-ISS/
setenv TGFS_INSTALL_ROOT `pwd`/install
setenv COWAREHOME <your SNPS PA installation>
setenv SNPSLMD_LICENSE_FILE <your SNPS PA license file>
source $COWAREHOME/SLS/linux/setup.csh pae
setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
setenv PATH $COWAREHOME/common/bin/:${PATH}
setenv CC $COWAREHOME/SLS/linux/common/bin/gcc
setenv CXX $COWAREHOME/SLS/linux/common/bin/g++
cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
-DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
cmake --build build/PA --target install -j16
cd dbt-rise-tgc/contrib/pa
# import the TGC core itself
pct tgc_import_tb.tcl
```
Setup for bash:
```
git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
cd TGC-ISS/
export TGFS_INSTALL_ROOT `pwd`/install
module load tools/pa/T-2022.06
export SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM=1
export CC=$COWAREHOME/SLS/linux/common/bin/gcc
export CXX=$COWAREHOME/SLS/linux/common/bin/g++
cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
-DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
cmake --build build/PA --target install -j16
cd dbt-rise-tgc/contrib/pa
# import the TGC core itself
pct tgc_import_tb.tcl
```

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contrib/pa/build.tcl
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namespace eval Specification {
proc buildproc { args } {
global env
variable installDir
variable compiler
variable compiler [::scsh::get_backend_compiler]
# set target $machine
set target [::scsh::machine]
set linkerOptions ""
set preprocessorOptions ""
set libversion $compiler
switch -exact -- $target {
"linux" {
set install_dir $::env(TGFS_INSTALL_ROOT)
set incldir "${install_dir}/include"
set libdir "${install_dir}/lib64"
set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
# Set the Linker paths.
set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc -lscc-sysc"]
}
default {
puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"
return
}
}
::scsh::cwr_append_ipsimbld_opts preprocessor "$preprocessorOptions"
::scsh::cwr_append_ipsimbld_opts linker "$linkerOptions"
}
::scsh::add_build_callback [namespace current]::buildproc
}

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#include "sysc/core_complex.h"
void modules() { sysc::tgfs::core_complex i_core_complex("core_complex"); }

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#############################################################################
#
#############################################################################
proc getScriptDirectory {} {
set dispScriptFile [file normalize [info script]]
set scriptFolder [file dirname $dispScriptFile]
return $scriptFolder
}
set hardware /HARDWARE/HW/HW
set scriptDir [getScriptDirectory]
set top_design_name core_complex
set encap_name sysc::tgfs::${top_design_name}
set clocks clk_i
set resets rst_i
set model_prefix "i_"
set model_postfix ""
::pct::new_project
::pct::open_library TLM2_PL
::pct::clear_systemc_defines
::pct::clear_systemc_include_path
::pct::add_to_systemc_include_path $::env(TGFS_INSTALL_ROOT)/include
::pct::set_import_protocol_generation_flag false
::pct::set_update_existing_encaps_flag true
::pct::set_dynamic_port_arrays_flag true
::pct::set_import_scml_properties_flag true
::pct::set_import_encap_prop_as_extra_prop_flag true
::pct::load_modules --set-category modules ${scriptDir}/tgc_import.cc
# Set Port Protocols correctly
set block ${top_design_name}
foreach clock ${clocks} {
::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${clock} SYSTEM_LIBRARY:CLOCK
}
foreach reset ${resets} {
::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
}
#::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
# Set compile settings and look
set block SYSTEM_LIBRARY:${top_design_name}
::pct::set_encap_build_script $block/${encap_name} $scriptDir/build.tcl
::pct::set_background_color_rgb $block 255 255 255 255
::pct::create_instance SYSTEM_LIBRARY:${top_design_name} ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${encap_name} ${encap_name}()
::pct::set_bounds i_${top_design_name} 200 300 100 400
::pct::set_image i_${top_design_name} "$scriptDir/minres.png" center center false true
# export the result as component
::pct::export_system_library ${top_design_name} ${top_design_name}.xml

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contrib/pa/tgc_import_tb.tcl
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source tgc_import.tcl
set hardware /HARDWARE/HW/HW
set FW_name ${scriptDir}/hello.elf
puts "instantiate testbench elements"
::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
::pct::set_param_value i_Memory_Generic/MEM:protocol {Protocol Common Parameters} address_width 30
::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/LT/clock_period_in_ns 1
::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/read/cmd_accept_cycles 1
::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/write/cmd_accept_cycles 1
::pct::set_bounds i_Memory_Generic 1000 300 100 100
::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
::BLWizard::generateFramework i_Bus SBLTLM2FT * {} \
{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
::pct::set_bounds i_Bus 700 300 100 400
::pct::create_connection C_ibus i_core_complex/ibus i_Bus/i_core_complex_ibus
::pct::set_location_on_owner i_Bus/i_core_complex_ibus 10
::pct::create_connection C_dbus i_core_complex/dbus i_Bus/i_core_complex_dbus
::pct::set_location_on_owner i_Bus/i_core_complex_dbus 10
::pct::create_connection C_mem i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
puts "instantiating clock manager"
set clock "Clk"
::hw::create_hw_instance "" GenericIPlib:ClockGenerator ${clock}_clock
::pct::set_bounds ${clock}_clock 100 100 100 100
::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period 1000
::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period_unit sc_core::SC_PS
puts "instantiating reset manager"
set reset "Rst"
::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset
::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 0
::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS
::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
::pct::set_bounds ${reset}_reset 300 100 100 100
puts "connecting reset/clock"
::pct::create_connection C_clk . Clk_clock/CLK i_core_complex/clk_i
::pct::add_ports_to_connection C_clk i_Bus/Clk
::pct::add_ports_to_connection C_clk i_Memory_Generic/CLK
::pct::create_connection C_rst . Rst_reset/RST i_core_complex/rst_i
::pct::add_ports_to_connection C_rst i_Bus/Rst
puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
::pct::set_param_value $hardware/i_${top_design_name} {Extra properties} elf_file ${FW_name}
::pct::set_address $hardware/i_${top_design_name}/ibus:i_Memory_Generic/MEM 0x0
::pct::set_address $hardware/i_${top_design_name}/dbus:i_Memory_Generic/MEM 0x0
::BLWizard::updateFramework i_Bus {} { common_configuration:BackBone:/advanced/num_resources_per_target:1 }
::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
::pct::create_simulation_build_config Debug
::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
# add build settings and save design for next steps
#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
#::simulation::run_simulation Simulation
#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
#::pct::export_system "export"
#::cd "export"
#::scsh::open-project
#::scsh::build
#::scsh::elab sim
::pct::save_system testbench.xml

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gen_input/.gitignore vendored
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/src-gen/
/CoreDSL-Instruction-Set-Description

50
gen_input/RISCVBase.core_desc Normal file
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InsructionSet RISCVBase {
constants {
XLEN,
fence:=0,
fencei:=1,
fencevmal:=2,
fencevmau:=3
}
address_spaces {
MEM[8], CSR[XLEN], FENCE[XLEN], RES[8]
}
registers {
[31:0] X[XLEN],
PC[XLEN](is_pc),
alias ZERO[XLEN] is X[0],
alias RA[XLEN] is X[1],
alias SP[XLEN] is X[2],
alias GP[XLEN] is X[3],
alias TP[XLEN] is X[4],
alias T0[XLEN] is X[5],
alias T1[XLEN] is X[6],
alias T2[XLEN] is X[7],
alias S0[XLEN] is X[8],
alias S1[XLEN] is X[9],
alias A0[XLEN] is X[10],
alias A1[XLEN] is X[11],
alias A2[XLEN] is X[12],
alias A3[XLEN] is X[13],
alias A4[XLEN] is X[14],
alias A5[XLEN] is X[15],
alias A6[XLEN] is X[16],
alias A7[XLEN] is X[17],
alias S2[XLEN] is X[18],
alias S3[XLEN] is X[19],
alias S4[XLEN] is X[20],
alias S5[XLEN] is X[21],
alias S6[XLEN] is X[22],
alias S7[XLEN] is X[23],
alias S8[XLEN] is X[24],
alias S9[XLEN] is X[25],
alias S10[XLEN] is X[26],
alias S11[XLEN] is X[27],
alias T3[XLEN] is X[28],
alias T4[XLEN] is X[29],
alias T5[XLEN] is X[30],
alias T6[XLEN] is X[31]
}
}

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import "RISCVBase.core_desc"
InsructionSet RV32I extends RISCVBase{
instructions {
LUI{
encoding: imm[31:12]s | rd[4:0] | b0110111;
args_disass: "{name(rd)}, {imm:#05x}";
if(rd!=0) X[rd] <= imm;
}
AUIPC{
encoding: imm[31:12]s | rd[4:0] | b0010111;
args_disass: "{name(rd)}, {imm:#08x}";
if(rd!=0) X[rd] <= PC's+imm;
}
JAL(no_cont){
encoding: imm[20:20]s | imm[10:1]s | imm[11:11]s | imm[19:12]s | rd[4:0] | b1101111;
args_disass: "{name(rd)}, {imm:#0x}";
if(rd!=0) X[rd] <= PC+4;
PC<=PC's+imm;
}
JALR(no_cont){
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
args_disass: "{name(rd)}, {name(rs1)}, {imm:#0x}";
val new_pc[XLEN] <= X[rs1]'s+ imm;
val align[XLEN] <= new_pc & 0x2;
if(align != 0){
raise(0, 0);
} else {
if(rd!=0) X[rd] <= PC+4;
PC<=new_pc & ~0x1;
}
}
BEQ(no_cont,cond){
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:1]s | imm[11:11]s | b1100011;
args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
PC<=choose(X[rs1]==X[rs2], PC's+imm, PC+4);
}
BNE(no_cont,cond){
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:1]s | imm[11:11]s | b1100011;
args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
PC<=choose(X[rs1]!=X[rs2], PC's+imm, PC+4);
}
BLT(no_cont,cond){
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b100 | imm[4:1]s | imm[11:11]s | b1100011;
args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
PC<=choose(X[rs1]s<X[rs2]s, PC's+imm, PC+4);
}
BGE(no_cont,cond) {
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b101 | imm[4:1]s | imm[11:11]s | b1100011;
args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
PC<=choose(X[rs1]s>=X[rs2]s, PC's+imm, PC+4);
}
BLTU(no_cont,cond) {
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b110 | imm[4:1]s | imm[11:11]s | b1100011;
args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
PC<=choose(X[rs1]<X[rs2],PC's+imm, PC+4);
}
BGEU(no_cont,cond) {
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b111 | imm[4:1]s | imm[11:11]s | b1100011;
args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
PC<=choose(X[rs1]>=X[rs2], PC's+imm, PC+4);
}
LB {
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0000011;
args_disass:"{name(rd)}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s+imm;
if(rd!=0) X[rd]<=sext(MEM[offs]);
}
LH {
encoding: imm[11:0]s | rs1[4:0] | b001 | rd[4:0] | b0000011;
args_disass:"{name(rd)}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s+imm;
if(rd!=0) X[rd]<=sext(MEM[offs]{16});
}
LW {
encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000011;
args_disass:"{name(rd)}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s+imm;
if(rd!=0) X[rd]<=sext(MEM[offs]{32});
}
LBU {
encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0000011;
args_disass:"{name(rd)}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s+imm;
if(rd!=0) X[rd]<=zext(MEM[offs]);
}
LHU {
encoding: imm[11:0]s | rs1[4:0] | b101 | rd[4:0] | b0000011;
args_disass:"{name(rd)}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s+imm;
if(rd!=0) X[rd]<=zext(MEM[offs]{16});
}
SB {
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:0]s | b0100011;
args_disass:"{name(rs2)}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs] <= X[rs2];
}
SH {
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:0]s | b0100011;
args_disass:"{name(rs2)}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs]{16} <= X[rs2];
}
SW {
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100011;
args_disass:"{name(rs2)}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs]{32} <= X[rs2];
}
ADDI {
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0010011;
args_disass:"{name(rd)}, {name(rs1)}, {imm}";
if(rd != 0) X[rd] <= X[rs1]'s + imm;
}
SLTI {
encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0010011;
args_disass:"{name(rd)}, {name(rs1)}, {imm}";
if (rd != 0) X[rd] <= choose(X[rs1]s < imm's, 1, 0);
}
SLTIU {
encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0010011;
args_disass:"{name(rd)}, {name(rs1)}, {imm}";
val full_imm[XLEN] <= imm's;
if (rd != 0) X[rd] <= choose(X[rs1]'u < full_imm'u, 1, 0);
}
XORI {
encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0010011;
args_disass:"{name(rd)}, {name(rs1)}, {imm}";
if(rd != 0) X[rd] <= X[rs1]s ^ imm;
}
ORI {
encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0010011;
args_disass:"{name(rd)}, {name(rs1)}, {imm}";
if(rd != 0) X[rd] <= X[rs1]s | imm;
}
ANDI {
encoding: imm[11:0]s | rs1[4:0] | b111 | rd[4:0] | b0010011;
args_disass:"{name(rd)}, {name(rs1)}, {imm}";
if(rd != 0) X[rd] <= X[rs1]s & imm;
}
SLLI {
encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0010011;
args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
if(shamt > 31){
raise(0,0);
} else {
if(rd != 0) X[rd] <= shll(X[rs1], shamt);
}
}
SRLI {
encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
if(shamt > 31){
raise(0,0);
} else {
if(rd != 0) X[rd] <= shrl(X[rs1], shamt);
}
}
SRAI {
encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
if(shamt > 31){
raise(0,0);
} else {
if(rd != 0) X[rd] <= shra(X[rs1], shamt);
}
}
ADD {
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0) X[rd] <= X[rs1] + X[rs2];
}
SUB {
encoding: b0100000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0) X[rd] <= X[rs1] - X[rs2];
}
SLL {
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0) X[rd] <= shll(X[rs1], X[rs2]&(XLEN-1));
}
SLT {
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if (rd != 0) X[rd] <= choose(X[rs1]s < X[rs2]s, 1, 0);
}
SLTU {
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if (rd != 0) X[rd] <= choose(zext(X[rs1]) < zext(X[rs2]), 1, 0);
}
XOR {
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0) X[rd] <= X[rs1] ^ X[rs2];
}
SRL {
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0) X[rd] <= shrl(X[rs1], X[rs2]&(XLEN-1));
}
SRA {
encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0) X[rd] <= shra(X[rs1], X[rs2]&(XLEN-1));
}
OR {
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0) X[rd] <= X[rs1] | X[rs2];
}
AND {
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0) X[rd] <= X[rs1] & X[rs2];
}
FENCE {
encoding: b0000 | pred[3:0] | succ[3:0] | rs1[4:0] | b000 | rd[4:0] | b0001111;
FENCE[fence] <= pred<<4 | succ;
}
FENCE_I(flush) {
encoding: imm[11:0] | rs1[4:0] | b001 | rd[4:0] | b0001111 ;
FENCE[fencei] <= imm;
}
ECALL(no_cont) {
encoding: b000000000000 | b00000 | b000 | b00000 | b1110011;
raise(0, 11);
}
EBREAK(no_cont) {
encoding: b000000000001 | b00000 | b000 | b00000 | b1110011;
raise(0, 3);
}
URET(no_cont) {
encoding: b0000000 | b00010 | b00000 | b000 | b00000 | b1110011;
leave(0);
}
SRET(no_cont) {
encoding: b0001000 | b00010 | b00000 | b000 | b00000 | b1110011;
leave(1);
}
MRET(no_cont) {
encoding: b0011000 | b00010 | b00000 | b000 | b00000 | b1110011;
leave(3);
}
WFI {
encoding: b0001000 | b00101 | b00000 | b000 | b00000 | b1110011;
wait(1);
}
SFENCE.VMA {
encoding: b0001001 | rs2[4:0] | rs1[4:0] | b000 | b00000 | b1110011;
FENCE[fencevmal] <= rs1;
FENCE[fencevmau] <= rs2;
}
CSRRW {
encoding: csr[11:0] | rs1[4:0] | b001 | rd[4:0] | b1110011;
args_disass:"{name(rd)}, {csr}, {name(rs1)}";
val rs_val[XLEN] <= X[rs1];
if(rd!=0){
val csr_val[XLEN] <= CSR[csr];
CSR[csr] <= rs_val;
// make sure Xrd is updated once CSR write succeeds
X[rd] <= csr_val;
} else {
CSR[csr] <= rs_val;
}
}
CSRRS {
encoding: csr[11:0] | rs1[4:0] | b010 | rd[4:0] | b1110011;
args_disass:"{name(rd)}, {csr}, {name(rs1)}";
val xrd[XLEN] <= CSR[csr];
val xrs1[XLEN] <= X[rs1];
if(rd!=0) X[rd] <= xrd;
if(rs1!=0) CSR[csr] <= xrd | xrs1;
}
CSRRC {
encoding: csr[11:0] | rs1[4:0] | b011 | rd[4:0] | b1110011;
args_disass:"{name(rd)}, {csr}, {name(rs1)}";
val xrd[XLEN] <= CSR[csr];
val xrs1[XLEN] <= X[rs1];
if(rd!=0) X[rd] <= xrd;
if(rs1!=0) CSR[csr] <= xrd & ~xrs1;
}
CSRRWI {
encoding: csr[11:0] | zimm[4:0] | b101 | rd[4:0] | b1110011;
args_disass:"{name(rd)}, {csr}, {zimm:#0x}";
if(rd!=0) X[rd] <= CSR[csr];
CSR[csr] <= zext(zimm);
}
CSRRSI {
encoding: csr[11:0] | zimm[4:0] | b110 | rd[4:0] | b1110011;
args_disass:"{name(rd)}, {csr}, {zimm:#0x}";
val res[XLEN] <= CSR[csr];
if(zimm!=0) CSR[csr] <= res | zext(zimm);
// make sure rd is written after csr write succeeds
if(rd!=0) X[rd] <= res;
}
CSRRCI {
encoding: csr[11:0] | zimm[4:0] | b111 | rd[4:0] | b1110011;
args_disass:"{name(rd)}, {csr}, {zimm:#0x}";
val res[XLEN] <= CSR[csr];
if(rd!=0) X[rd] <= res;
if(zimm!=0) CSR[csr] <= res & ~zext(zimm, XLEN);
}
}
}

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import "RV32I.core_desc"
InsructionSet RV64I extends RV32I {
instructions{
LWU { // 80000104: 0000ef03 lwu t5,0(ra)
encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0000011;
args_disass:"{name(rd)}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s+imm;
if(rd!=0) X[rd]<=zext(MEM[offs]{32});
}
LD{
encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000011;
args_disass:"{name(rd)}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s + imm;
if(rd!=0) X[rd]<=sext(MEM[offs]{64});
}
SD{
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100011;
args_disass:"{name(rs2)}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs]{64} <= X[rs2];
}
SLLI {
encoding: b000000 | shamt[5:0] | rs1[4:0] | b001 | rd[4:0] | b0010011;
args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
if(rd != 0) X[rd] <= shll(X[rs1], shamt);
}
SRLI {
encoding: b000000 | shamt[5:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
if(rd != 0) X[rd] <= shrl(X[rs1], shamt);
}
SRAI {
encoding: b010000 | shamt[5:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
if(rd != 0) X[rd] <= shra(X[rs1], shamt);
}
ADDIW {
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0011011;
args_disass:"{name(rd)}, {name(rs1)}, {imm}";
if(rd != 0){
val res[32] <= X[rs1]{32}'s + imm;
X[rd] <= sext(res);
}
}
SLLIW {
encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0011011;
args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
if(rd != 0){
val sh_val[32] <= shll(X[rs1]{32}, shamt);
X[rd] <= sext(sh_val);
}
}
SRLIW {
encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0011011;
args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
if(rd != 0){
val sh_val[32] <= shrl(X[rs1]{32}, shamt);
X[rd] <= sext(sh_val);
}
}
SRAIW {
encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0011011;
args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
if(rd != 0){
val sh_val[32] <= shra(X[rs1]{32}, shamt);
X[rd] <= sext(sh_val);
}
}
ADDW {
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011;
if(rd != 0){
val res[32] <= X[rs1]{32} + X[rs2]{32};
X[rd] <= sext(res);
}
}
SUBW {
encoding: b0100000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011;
if(rd != 0){
val res[32] <= X[rs1]{32} - X[rs2]{32};
X[rd] <= sext(res);
}
}
SLLW {
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0111011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val mask[32] <= 0x1f;
val count[32] <= X[rs2]{32} & mask;
val sh_val[32] <= shll(X[rs1]{32}, count);
X[rd] <= sext(sh_val);
}
}
SRLW {
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val mask[32] <= 0x1f;
val count[32] <= X[rs2]{32} & mask;
val sh_val[32] <= shrl(X[rs1]{32}, count);
X[rd] <= sext(sh_val);
}
}
SRAW {
encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val mask[32] <= 0x1f;
val count[32] <= X[rs2]{32} & mask;
val sh_val[32] <= shra(X[rs1]{32}, count);
X[rd] <= sext(sh_val);
}
}
}
}

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import "RISCVBase.core_desc"
InsructionSet RV32A extends RISCVBase{
instructions{
LR.W {
encoding: b00010 | aq[0:0] | rl[0:0] | b00000 | rs1[4:0] | b010 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}";
if(rd!=0){
val offs[XLEN] <= X[rs1];
X[rd]<= sext(MEM[offs]{32}, XLEN);
RES[offs]{32}<=sext(-1, 32);
}
}
SC.W {
encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)}";
val offs[XLEN] <= X[rs1];
val res1[32] <= RES[offs]{32};
if(res1!=0)
MEM[offs]{32} <= X[rs2];
if(rd!=0) X[rd]<= choose(res1!=zext(0, 32), 0, 1);
}
AMOSWAP.W{
encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN]<=X[rs1];
if(rd!=0) X[rd]<=sext(MEM[offs]{32});
MEM[offs]{32}<=X[rs2];
}
AMOADD.W{
encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN]<=X[rs1];
val res1[XLEN] <= sext(MEM[offs]{32});
if(rd!=0) X[rd]<=res1;
val res2[XLEN]<=res1 + X[rs2];
MEM[offs]{32}<=res2;
}
AMOXOR.W{
encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN]<=X[rs1];
val res1[XLEN] <= sext(MEM[offs]{32});
if(rd!=0) X[rd]<=res1;
val res2[XLEN]<=res1 ^ X[rs2];
MEM[offs]{32}<=res2;
}
AMOAND.W{
encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN]<=X[rs1];
val res1[XLEN] <= sext(MEM[offs]{32});
if(rd!=0) X[rd]<=res1;
val res2[XLEN] <=res1 & X[rs2];
MEM[offs]{32}<=res2;
}
AMOOR.W {
encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN]<=X[rs1];
val res1[XLEN] <= sext(MEM[offs]{32});
if(rd!=0) X[rd]<=res1;
val res2[XLEN]<=res1 | X[rs2];
MEM[offs]{32}<=res2;
}
AMOMIN.W{
encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN]<=X[rs1];
val res1[XLEN] <= sext(MEM[offs]{32});
if(rd!=0) X[rd] <= res1;
val res2[XLEN] <= choose(res1's > X[rs2]s, X[rs2], res1);
MEM[offs]{32} <= res2;
}
AMOMAX.W{
encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN]<=X[rs1];
val res1[XLEN] <= sext(MEM[offs]{32});
if(rd!=0) X[rd]<=res1;
val res2[XLEN]<= choose(res1's<X[rs2]s, X[rs2], res1);
MEM[offs]{32}<=res2;
}
AMOMINU.W{
encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN]<=X[rs1];
val res1[XLEN] <= sext(MEM[offs]{32});
if(rd!=0) X[rd]<=res1;
val res2[XLEN]<= choose(res1>X[rs2], X[rs2], res1);
MEM[offs]{32}<=res2;
}
AMOMAXU.W{
encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN]<=X[rs1];
val res1[XLEN] <= sext(MEM[offs]{32});
if(rd!=0) X[rd] <= res1;
val res2[XLEN] <= choose(res1 < X[rs2], X[rs2], res1);
MEM[offs]{32} <= res2;
}
}
}
InsructionSet RV64A extends RV32A {
instructions{
LR.D {
encoding: b00010 | aq[0:0] | rl[0:0] | b00000 | rs1[4:0] | b011 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}";
if(rd!=0){
val offs[XLEN] <= X[rs1];
X[rd]<= sext(MEM[offs]{64}, XLEN);
RES[offs]{64}<=sext(-1, 64);
}
}
SC.D {
encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)}";
val offs[XLEN] <= X[rs1];
val res[64] <= RES[offs];
if(res!=0){
MEM[offs]{64} <= X[rs2];
if(rd!=0) X[rd]<=0;
} else{
if(rd!=0) X[rd]<= 1;
}
}
AMOSWAP.D{
encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN] <= X[rs1];
if(rd!=0) X[rd] <= sext(MEM[offs]{64});
MEM[offs]{64} <= X[rs2];
}
AMOADD.D{
encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN] <= X[rs1];
val res[XLEN] <= sext(MEM[offs]{64});
if(rd!=0) X[rd]<=res;
val res2[XLEN] <= res + X[rs2];
MEM[offs]{64}<=res2;
}
AMOXOR.D{
encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN] <= X[rs1];
val res[XLEN] <= sext(MEM[offs]{64});
if(rd!=0) X[rd] <= res;
val res2[XLEN] <= res ^ X[rs2];
MEM[offs]{64} <= res2;
}
AMOAND.D{
encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN] <= X[rs1];
val res[XLEN] <= sext(MEM[offs]{64});
if(rd!=0) X[rd] <= res;
val res2[XLEN] <= res & X[rs2];
MEM[offs]{64} <= res2;
}
AMOOR.D {
encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN] <= X[rs1];
val res[XLEN] <= sext(MEM[offs]{64});
if(rd!=0) X[rd] <= res;
val res2[XLEN] <= res | X[rs2];
MEM[offs]{64} <= res2;
}
AMOMIN.D{
encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN] <= X[rs1];
val res1[XLEN] <= sext(MEM[offs]{64});
if(rd!=0) X[rd] <= res1;
val res2[XLEN] <= choose(res1's > X[rs2]s, X[rs2], res1);
MEM[offs]{64} <= res2;
}
AMOMAX.D{
encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN] <= X[rs1];
val res[XLEN] <= sext(MEM[offs]{64});
if(rd!=0) X[rd] <= res;
val res2[XLEN] <= choose(res s < X[rs2]s, X[rs2], res);
MEM[offs]{64} <= res2;
}
AMOMINU.D{
encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN] <= X[rs1];
val res[XLEN] <= sext(MEM[offs]{64});
if(rd!=0) X[rd] <= res;
val res2[XLEN] <= choose(res > X[rs2], X[rs2], res);
MEM[offs]{64} <= res2;
}
AMOMAXU.D{
encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
val offs[XLEN] <= X[rs1];
val res1[XLEN] <= sext(MEM[offs]{64});
if(rd!=0) X[rd] <= res1;
val res2[XLEN] <= choose(res1 < X[rs2], X[rs2], res1);
MEM[offs]{64} <= res2;
}
}
}

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import "RISCVBase.core_desc"
InsructionSet RV32IC extends RISCVBase{
instructions{
JALR(no_cont){ // overwriting the implementation if rv32i, alignment does not need to be word
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
args_disass: "{name(rd)}, {name(rs1)}, {imm:#0x}";
val new_pc[XLEN] <= X[rs1]s + imm;
if(rd!=0) X[rd] <= PC+4;
PC<=new_pc & ~0x1;
}
C.ADDI4SPN { //(RES, imm=0)
encoding: b000 | imm[5:4] | imm[9:6] | imm[2:2] | imm[3:3] | rd[2:0] | b00;
args_disass: "{name(rd)}, {imm:#05x}";
if(imm == 0) raise(0, 2);
X[rd+8] <= X[2] + imm;
}
C.LW { // (RV32)
encoding: b010 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
args_disass: "{name(8+rd)}, {uimm:#05x}({name(8+rs1)})";
val offs[XLEN] <= X[rs1+8]+uimm;
X[rd+8] <= sext(MEM[offs]{32});
}
C.SW {//(RV32)
encoding: b110 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
args_disass: "{name(8+rs2)}, {uimm:#05x}({name(8+rs1)})";
val offs[XLEN] <= X[rs1+8]+uimm;
MEM[offs]{32} <= X[rs2+8];
}
C.ADDI {//(RV32)
encoding:b000 | imm[5:5]s | rs1[4:0] | imm[4:0]s | b01;
args_disass: "{name(rs1)}, {imm:#05x}";
X[rs1] <= X[rs1]'s + imm;
}
C.NOP {
encoding:b000 | b0 | b00000 | b00000 | b01;
}
// C.JAL will be overwritten by C.ADDIW for RV64/128
C.JAL(no_cont) {//(RV32)
encoding: b001 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
args_disass: "{imm:#05x}";
X[1] <= PC+2;
PC<=PC's+imm;
}
C.LI {//(RV32)
encoding:b010 | imm[5:5]s | rd[4:0] | imm[4:0]s | b01;
args_disass: "{name(rd)}, {imm:#05x}";
if(rd == 0) raise(0, 2); //TODO: should it be handled as trap?
X[rd] <= imm;
}
// order matters here as C.ADDI16SP overwrites C.LUI vor rd==2
C.LUI {//(RV32)
encoding:b011 | imm[17:17] | rd[4:0] | imm[16:12]s | b01;
args_disass: "{name(rd)}, {imm:#05x}";
if(rd == 0) raise(0, 2); //TODO: should it be handled as trap?
if(imm == 0) raise(0, 2); //TODO: should it be handled as trap?
X[rd] <= imm;
}
C.ADDI16SP {//(RV32)
encoding:b011 | imm[9:9]s | b00010 | imm[4:4]s | imm[6:6]s | imm[8:7]s | imm[5:5]s | b01;
args_disass: "{imm:#05x}";
X[2] <= X[2]s + imm;
}
C.SRLI {//(RV32 nse)
encoding:b100 | b0 | b00 | rs1[2:0] | shamt[4:0] | b01;
args_disass: "{name(8+rs1)}, {shamt}";
val rs1_idx[5] <= rs1+8;
X[rs1_idx] <= shrl(X[rs1_idx], shamt);
}
C.SRAI {//(RV32)
encoding:b100 | b0 | b01 | rs1[2:0] | shamt[4:0] | b01;
args_disass: "{name(8+rs1)}, {shamt}";
val rs1_idx[5] <= rs1+8;
X[rs1_idx] <= shra(X[rs1_idx], shamt);
}
C.ANDI {//(RV32)
encoding:b100 | imm[5:5]s | b10 | rs1[2:0] | imm[4:0]s | b01;
args_disass: "{name(8+rs1)}, {imm:#05x}";
val rs1_idx[5] <= rs1 + 8;
X[rs1_idx] <= X[rs1_idx]s & imm;
}
C.SUB {//(RV32)
encoding:b100 | b0 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
args_disass: "{name(8+rd)}, {name(8+rs2)}";
val rd_idx[5] <= rd + 8;
X[rd_idx] <= X[rd_idx] - X[rs2 + 8];
}
C.XOR {//(RV32)
encoding:b100 | b0 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
args_disass: "{name(8+rd)}, {name(8+rs2)}";
val rd_idx[5] <= rd + 8;
X[rd_idx] <= X[rd_idx] ^ X[rs2 + 8];
}
C.OR {//(RV32)
encoding:b100 | b0 | b11 | rd[2:0] | b10 | rs2[2:0] | b01;
args_disass: "{name(8+rd)}, {name(8+rs2)}";
val rd_idx[5] <= rd + 8;
X[rd_idx] <= X[rd_idx] | X[rs2 + 8];
}
C.AND {//(RV32)
encoding:b100 | b0 | b11 | rd[2:0] | b11 | rs2[2:0] | b01;
args_disass: "{name(8+rd)}, {name(8+rs2)}";
val rd_idx[5] <= rd + 8;
X[rd_idx] <= X[rd_idx] & X[rs2 + 8];
}
C.J(no_cont) {//(RV32)
encoding:b101 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
args_disass: "{imm:#05x}";
PC<=PC's+imm;
}
C.BEQZ(no_cont,cond) {//(RV32)
encoding:b110 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s |imm[2:1]s | imm[5:5]s | b01;
args_disass: "{name(8+rs1)}, {imm:#05x}";
PC<=choose(X[rs1+8]==0, PC's+imm, PC+2);
}
C.BNEZ(no_cont,cond) {//(RV32)
encoding:b111 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s | imm[2:1]s | imm[5:5]s | b01;
args_disass: "{name(8+rs1)}, {imm:#05x}";
PC<=choose(X[rs1+8]!=0, PC's+imm, PC+2);
}
C.SLLI {//(RV32)
encoding:b000 | b0 | rs1[4:0] | shamt[4:0] | b10;
args_disass: "{name(rs1)}, {shamt}";
if(rs1 == 0) raise(0, 2);
X[rs1] <= shll(X[rs1], shamt);
}
C.LWSP {//
encoding:b010 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
args_disass: "{name(rd)}, sp, {uimm:#05x}";
val offs[XLEN] <= X[2] + uimm;
X[rd] <= sext(MEM[offs]{32});
}
// order matters as C.JR is a special case of C.MV
C.MV {//(RV32)
encoding:b100 | b0 | rd[4:0] | rs2[4:0] | b10;
args_disass: "{name(rd)}, {name(rs2)}";
X[rd] <= X[rs2];
}
C.JR(no_cont) {//(RV32)
encoding:b100 | b0 | rs1[4:0] | b00000 | b10;
args_disass: "{name(rs1)}";
PC <= X[rs1];
}
// order matters as C.EBREAK is a special case of C.JALR which is a special case of C.ADD
C.ADD {//(RV32)
encoding:b100 | b1 | rd[4:0] | rs2[4:0] | b10;
args_disass: "{name(rd)}, {name(rs2)}";
X[rd] <= X[rd] + X[rs2];
}
C.JALR(no_cont) {//(RV32)
encoding:b100 | b1 | rs1[4:0] | b00000 | b10;
args_disass: "{name(rs1)}";
X[1] <= PC+2;
PC<=X[rs1];
}
C.EBREAK(no_cont) {//(RV32)
encoding:b100 | b1 | b00000 | b00000 | b10;
raise(0, 3);
}
C.SWSP {//
encoding:b110 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
args_disass: "{name(rs2)}, {uimm:#05x}(sp)";
val offs[XLEN] <= X[2] + uimm;
MEM[offs]{32} <= X[rs2];
}
DII(no_cont) { // Defined Illegal Instruction
encoding:b000 | b0 | b00000 | b00000 | b00;
raise(0, 2);
}
}
}
InsructionSet RV32FC extends RV32IC{
constants {
FLEN
}
registers {
[31:0] F[FLEN]
}
instructions{
C.FLW {
encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
args_disass:"f(8+{rd}), {uimm}({name(8+rs1)})";
val offs[XLEN] <= X[rs1+8]+uimm;
val res[32] <= MEM[offs]{32};
if(FLEN==32)
F[rd+8] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd+8] <= (upper<<32) | zext(res, FLEN);
}
}
C.FSW {
encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
args_disass:"f(8+{rs2}), {uimm}({name(8+rs1)})";
val offs[XLEN] <= X[rs1+8]+uimm;
MEM[offs]{32}<=F[rs2+8]{32};
}
C.FLWSP {
encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
args_disass:"f{rd}, {uimm}(x2)";
val offs[XLEN] <= X[2]+uimm;
val res[32] <= MEM[offs]{32};
if(FLEN==32)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
}
C.FSWSP {
encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
args_disass:"f{rs2}, {uimm}(x2), ";
val offs[XLEN] <= X[2]+uimm;
MEM[offs]{32}<=F[rs2]{32};
}
}
}
InsructionSet RV32DC extends RV32IC{
constants {
FLEN
}
registers {
[31:0] F[FLEN]
}
instructions{
C.FLD { //(RV32/64)
encoding: b001 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
args_disass:"f(8+{rd}), {uimm}({name(8+rs1)})";
val offs[XLEN] <= X[rs1+8]+uimm;
val res[64] <= MEM[offs]{64};
if(FLEN==64)
F[rd+8] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd+8] <= (upper<<64) | res;
}
}
C.FSD { //(RV32/64)
encoding: b101 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
args_disass:"f(8+{rs2}), {uimm}({name(8+rs1)})";
val offs[XLEN] <= X[rs1+8]+uimm;
MEM[offs]{64}<=F[rs2+8]{64};
}
C.FLDSP {//(RV32/64)
encoding:b001 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
args_disass:"f{rd}, {uimm}(x2)";
val offs[XLEN] <= X[2]+uimm;
val res[64] <= MEM[offs]{64};
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | zext(res, FLEN);
}
}
C.FSDSP {//(RV32/64)
encoding:b101 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
args_disass:"f{rs2}, {uimm}(x2), ";
val offs[XLEN] <= X[2]+uimm;
MEM[offs]{64}<=F[rs2]{64};
}
}
}
InsructionSet RV64IC extends RV32IC {
instructions{
C.LD {//(RV64/128)
encoding:b011 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
args_disass: "{name(8+rd)}, {uimm},({name(8+rs1)})";
val offs[XLEN] <= X[rs1+8] + uimm;
X[rd+8]<=sext(MEM[offs]{64});
}
C.SD { //(RV64/128)
encoding:b111 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
args_disass: "{name(8+rs2)}, {uimm},({name(8+rs1)})";
val offs[XLEN] <= X[rs1+8] + uimm;
MEM[offs]{64} <= X[rs2+8];
}
C.SUBW {//(RV64/128, RV32 res)
encoding:b100 | b1 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
args_disass: "{name(8+rd)}, {name(8+rd)}, {name(8+rs2)}";
val res[32] <= X[rd+8]{32} - X[rs2+8]{32};
X[rd+8] <= sext(res);
}
C.ADDW {//(RV64/128 RV32 res)
encoding:b100 | b1 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
args_disass: "{name(8+rd)}, {name(8+rd)}, {name(8+rs2)}";
val res[32] <= X[rd+8]{32} + X[rs2+8]{32};
X[rd+8] <= sext(res);
}
C.ADDIW {//(RV64/128)
encoding:b001 | imm[5:5]s | rs1[4:0] | imm[4:0]s | b01;
args_disass: "{name(rs1)}, {imm:#05x}";
if(rs1 != 0){
val res[32] <= X[rs1]{32}'s + imm;
X[rs1] <= sext(res);
}
}
C.SRLI {//(RV64)
encoding:b100 | shamt[5:5] | b00 | rs1[2:0] | shamt[4:0] | b01;
args_disass: "{name(8+rs1)}, {shamt}";
val rs1_idx[5] <= rs1+8;
X[rs1_idx] <= shrl(X[rs1_idx], shamt);
}
C.SRAI {//(RV64)
encoding:b100 | shamt[5:5] | b01 | rs1[2:0] | shamt[4:0] | b01;
args_disass: "{name(8+rs1)}, {shamt}";
val rs1_idx[5] <= rs1+8;
X[rs1_idx] <= shra(X[rs1_idx], shamt);
}
C.SLLI {//(RV64)
encoding:b000 | shamt[5:5] | rs1[4:0] | shamt[4:0] | b10;
args_disass: "{name(rs1)}, {shamt}";
if(rs1 == 0) raise(0, 2);
X[rs1] <= shll(X[rs1], shamt);
}
C.LDSP {//(RV64/128
encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
args_disass:"{name(rd)}, {uimm}(sp)";
val offs[XLEN] <= X[2] + uimm;
if(rd!=0) X[rd]<=sext(MEM[offs]{64});
}
C.SDSP {//(RV64/128)
encoding:b111 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
args_disass:"{name(rs2)}, {uimm}(sp)";
val offs[XLEN] <= X[2] + uimm;
MEM[offs]{64} <= X[rs2];
}
}
}
InsructionSet RV128IC extends RV64IC {
instructions{
C.SRLI {//(RV128)
encoding:b100 | shamt[5:5] | b00 | rs1[2:0] | shamt[4:0] | b01;
args_disass: "{name(8+rs1)}, {shamt}";
val rs1_idx[5] <= rs1+8;
X[rs1_idx] <= shrl(X[rs1_idx], shamt);
}
C.SRAI {//(RV128)
encoding:b100 | shamt[5:5] | b01 | rs1[2:0] | shamt[4:0] | b01;
args_disass: "{name(8+rs1)}, {shamt}";
val rs1_idx[5] <= rs1+8;
X[rs1_idx] <= shra(X[rs1_idx], shamt);
}
C.SLLI {//(RV128)
encoding:b000 | shamt[5:5] | rs1[4:0] | shamt[4:0] | b10;
args_disass: "{name(rs1)}, {shamt}";
if(rs1 == 0) raise(0, 2);
X[rs1] <= shll(X[rs1], shamt);
}
C.LQ { //(RV128)
encoding:b001 | uimm[5:4] | uimm[8:8] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
}
C.SQ { //(RV128)
encoding:b101 | uimm[5:4] | uimm[8:8] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
}
C.SQSP {//(RV128)
encoding:b101 | uimm[5:4] | uimm[9:6] | rs2[4:0] | b10;
}
}
}

360
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import "RISCVBase.core_desc"
InsructionSet RV32D extends RISCVBase{
constants {
FLEN, FFLAG_MASK := 0x1f
}
registers {
[31:0] F[FLEN], FCSR[32]
}
instructions{
FLD {
encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000111;
args_disass:"f{rd}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s + imm;
val res[64] <= MEM[offs]{64};
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
}
FSD {
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100111;
args_disass:"f{rs2}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs]{64}<=F[rs2]{64};
}
FMADD.D {
encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(0, 64), choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FMSUB.D {
encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FNMADD.D {
encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FNMSUB.D {
encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FADD.D {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}, f{rs2}";
// F[rd]f <= F[rs1]f + F[rs2]f;
val res[64] <= fdispatch_fadd_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FSUB.D {
encoding: b0000101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}, f{rs2}";
// F[rd]f <= F[rs1]f - F[rs2]f;
val res[64] <= fdispatch_fsub_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FMUL.D {
encoding: b0001001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}, f{rs2}";
// F[rd]f <= F[rs1]f * F[rs2]f;
val res[64] <= fdispatch_fmul_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FDIV.D {
encoding: b0001101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}, f{rs2}";
// F[rd]f <= F[rs1]f / F[rs2]f;
val res[64] <= fdispatch_fdiv_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FSQRT.D {
encoding: b0101101 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}";
//F[rd]f<=sqrt(F[rs1]f);
val res[64] <= fdispatch_fsqrt_d(F[rs1]{64}, choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FSGNJ.D {
encoding: b0010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}, f{rs2}";
val ONE[64] <= 1;
val MSK1[64] <= ONE<<63;
val MSK2[64] <= MSK1-1;
val res[64] <= (F[rs1]{64} & MSK2) | (F[rs2]{64} & MSK1);
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
}
FSGNJN.D {
encoding: b0010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}, f{rs2}";
val ONE[64] <= 1;
val MSK1[64] <= ONE<<63;
val MSK2[64] <= MSK1-1;
val res[64] <= (F[rs1]{64} & MSK2) | (~F[rs2]{64} & MSK1);
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
}
FSGNJX.D {
encoding: b0010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}, f{rs2}";
val ONE[64] <= 1;
val MSK1[64] <= ONE<<63;
val res[64] <= F[rs1]{64} ^ (F[rs2]{64} & MSK1);
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
}
FMIN.D {
encoding: b0010101 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}, f{rs2}";
//F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32));
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FMAX.D {
encoding: b0010101 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}, f{rs2}";
//F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32));
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FCVT.S.D {
encoding: b0100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}";
val res[32] <= fdispatch_fconv_d2f(F[rs1], rm{8});
// NaN boxing
val upper[FLEN] <= -1;
F[rd] <= upper<<32 | zext(res, FLEN);
}
FCVT.D.S {
encoding: b0100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}";
val res[64] <= fdispatch_fconv_f2d(F[rs1]{32}, rm{8});
if(FLEN==64){
F[rd] <= res;
} else {
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
}
FEQ.D {
encoding: b1010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}, f{rs2}";
X[rd]<=zext(fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32)));
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FLT.D {
encoding: b1010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}, f{rs2}";
X[rd]<=zext(fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(2, 32)));
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FLE.D {
encoding: b1010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}, f{rs2}";
X[rd]<=zext(fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32)));
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FCLASS.D {
encoding: b1110001 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}";
X[rd]<=fdispatch_fclass_d(F[rs1]{64});
}
FCVT.W.D {
encoding: b1100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}";
X[rd]<= sext(fdispatch_fcvt_64_32(F[rs1]{64}, zext(0, 32), rm{8}), XLEN);
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FCVT.WU.D {
encoding: b1100001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}";
//FIXME: should be zext accodring to spec but needs to be sext according to tests
X[rd]<= sext(fdispatch_fcvt_64_32(F[rs1]{64}, zext(1, 32), rm{8}), XLEN);
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FCVT.D.W {
encoding: b1101001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, {name(rs1)}";
val res[64] <= fdispatch_fcvt_32_64(sext(X[rs1]{32},64), zext(2, 32), rm{8});
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
}
FCVT.D.WU {
encoding: b1101001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, {name(rs1)}";
val res[64] <=fdispatch_fcvt_32_64(zext(X[rs1]{32},64), zext(3,32), rm{8});
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
}
}
}
InsructionSet RV64D extends RV32D{
instructions{
FCVT.L.D {
encoding: b1100001 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}";
X[rd]<= sext(fdispatch_fcvt_d(F[rs1]{64}, zext(0, 32), rm{8}), XLEN);
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FCVT.LU.D {
encoding: b1100001 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}";
X[rd]<= sext(fdispatch_fcvt_d(F[rs1]{64}, zext(1, 32), rm{8}), XLEN);
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FCVT.D.L {
encoding: b1101001 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, {name(rs1)}";
val res[64] <= fdispatch_fcvt_d(sext(X[rs1],64), zext(2, 32), rm{8});
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
}
FCVT.D.LU {
encoding: b1101001 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, {name(rs1)}";
val res[64] <=fdispatch_fcvt_d(zext(X[rs1],64), zext(3,32), rm{8});
if(FLEN==64)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<64) | res;
}
}
FMV.X.D {
encoding: b1110001 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}";
X[rd]<=sext(F[rs1]);
}
FMV.D.X {
encoding: b1111001 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"f{rd}, {name(rs1)}";
F[rd] <= zext(X[rs1]);
}
}
}

400
gen_input/RVF.core_desc Normal file
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import "RV32I.core_desc"
InsructionSet RV32F extends RV32I{
constants {
FLEN, FFLAG_MASK := 0x1f
}
registers {
[31:0] F[FLEN], FCSR[32]
}
instructions{
FLW {
encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111;
args_disass:"f{rd}, {imm}(x{rs1})";
val offs[XLEN] <= X[rs1]'s + imm;
val res[32] <= MEM[offs]{32};
if(FLEN==32)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
}
FSW {
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111;
args_disass:"f{rs2}, {imm}(x{rs1})";
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs]{32}<=F[rs2]{32};
}
FMADD.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
if(FLEN==32)
F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
val frs3[32] <= fdispatch_unbox_s(F[rs3]);
val res[32] <= fdispatch_fmadd_s(frs1, frs2, frs3, zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FMSUB.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
if(FLEN==32)
F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
val frs3[32] <= fdispatch_unbox_s(F[rs3]);
val res[32] <= fdispatch_fmadd_s(frs1, frs2, frs3, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FNMADD.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
if(FLEN==32)
F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
val frs3[32] <= fdispatch_unbox_s(F[rs3]);
val res[32] <= fdispatch_fmadd_s(frs1, frs2, frs3, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FNMSUB.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
if(FLEN==32)
F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
val frs3[32] <= fdispatch_unbox_s(F[rs3]);
val res[32] <= fdispatch_fmadd_s(frs1, frs2, frs3, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FADD.S {
encoding: b0000000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}, f{rs2}";
// F[rd]f <= F[rs1]f + F[rs2]f;
if(FLEN==32)
F[rd] <= fdispatch_fadd_s(F[rs1], F[rs2], choose(rm<7, rm{8}, FCSR{8}));
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
val res[32] <= fdispatch_fadd_s(frs1, frs2, choose(rm<7, rm{8}, FCSR{8}));
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FSUB.S {
encoding: b0000100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}, f{rs2}";
// F[rd]f <= F[rs1]f - F[rs2]f;
if(FLEN==32)
F[rd] <= fdispatch_fsub_s(F[rs1], F[rs2], choose(rm<7, rm{8}, FCSR{8}));
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
val res[32] <= fdispatch_fsub_s(frs1, frs2, choose(rm<7, rm{8}, FCSR{8}));
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FMUL.S {
encoding: b0001000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}, f{rs2}";
// F[rd]f <= F[rs1]f * F[rs2]f;
if(FLEN==32)
F[rd] <= fdispatch_fmul_s(F[rs1], F[rs2], choose(rm<7, rm{8}, FCSR{8}));
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
val res[32] <= fdispatch_fmul_s(frs1, frs2, choose(rm<7, rm{8}, FCSR{8}));
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FDIV.S {
encoding: b0001100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}, f{rs2}";
// F[rd]f <= F[rs1]f / F[rs2]f;
if(FLEN==32)
F[rd] <= fdispatch_fdiv_s(F[rs1], F[rs2], choose(rm<7, rm{8}, FCSR{8}));
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
val res[32] <= fdispatch_fdiv_s(frs1, frs2, choose(rm<7, rm{8}, FCSR{8}));
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FSQRT.S {
encoding: b0101100 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}";
//F[rd]f<=sqrt(F[rs1]f);
if(FLEN==32)
F[rd] <= fdispatch_fsqrt_s(F[rs1], choose(rm<7, rm{8}, FCSR{8}));
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val res[32] <= fdispatch_fsqrt_s(frs1, choose(rm<7, rm{8}, FCSR{8}));
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FSGNJ.S {
encoding: b0010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}, f{rs2}";
if(FLEN==32)
F[rd] <= (F[rs1] & 0x7fffffff) | (F[rs2] & 0x80000000);
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
val res[32] <= (frs1 & 0x7fffffff) | (frs2 & 0x80000000);
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
}
FSGNJN.S {
encoding: b0010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}, f{rs2}";
if(FLEN==32)
F[rd] <= (F[rs1] & 0x7fffffff) | (~F[rs2] & 0x80000000);
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
val res[32] <= (frs1 & 0x7fffffff) | (~frs2 & 0x80000000);
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
}
FSGNJX.S {
encoding: b0010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}, f{rs2}";
if(FLEN==32)
F[rd] <= F[rs1] ^ (F[rs2] & 0x80000000);
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
val res[32] <= frs1 ^ (frs2 & 0x80000000);
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
}
FMIN.S {
encoding: b0010100 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}, f{rs2}";
//F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
if(FLEN==32)
F[rd] <= fdispatch_fsel_s(F[rs1], F[rs2], zext(0, 32));
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
val res[32] <= fdispatch_fsel_s(frs1, frs2, zext(0, 32));
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FMAX.S {
encoding: b0010100 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
args_disass:"f{rd}, f{rs1}, f{rs2}";
//F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
if(FLEN==32)
F[rd] <= fdispatch_fsel_s(F[rs1], F[rs2], zext(1, 32));
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
val res[32] <= fdispatch_fsel_s(frs1, frs2, zext(1, 32));
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FCVT.W.S {
encoding: b1100000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}";
if(FLEN==32)
X[rd] <= sext(fdispatch_fcvt_s(F[rs1], zext(0, 32), rm{8}), XLEN);
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
X[rd]<= sext(fdispatch_fcvt_s(frs1, zext(0, 32), rm{8}), XLEN);
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FCVT.WU.S {
encoding: b1100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}";
//FIXME: according to the spec it should be zero-extended not sign extended
if(FLEN==32)
X[rd]<= sext(fdispatch_fcvt_s(F[rs1], zext(1, 32), rm{8}), XLEN);
else { // NaN boxing
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
X[rd]<= sext(fdispatch_fcvt_s(frs1, zext(1, 32), rm{8}), XLEN);
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FEQ.S {
encoding: b1010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}, f{rs2}";
if(FLEN==32)
X[rd]<=zext(fdispatch_fcmp_s(F[rs1], F[rs2], zext(0, 32)));
else {
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
X[rd]<=zext(fdispatch_fcmp_s(frs1, frs2, zext(0, 32)));
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FLT.S {
encoding: b1010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}, f{rs2}";
if(FLEN==32)
X[rd]<=zext(fdispatch_fcmp_s(F[rs1], F[rs2], zext(2, 32)));
else {
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
X[rd]<=zext(fdispatch_fcmp_s(frs1, frs2, zext(2, 32)));
}
X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(2, 32));
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FLE.S {
encoding: b1010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}, f{rs2}";
if(FLEN==32)
X[rd]<=zext(fdispatch_fcmp_s(F[rs1], F[rs2], zext(1, 32)));
else {
val frs1[32] <= fdispatch_unbox_s(F[rs1]);
val frs2[32] <= fdispatch_unbox_s(F[rs2]);
X[rd]<=zext(fdispatch_fcmp_s(frs1, frs2, zext(1, 32)));
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FCLASS.S {
encoding: b1110000 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}";
X[rd]<=fdispatch_fclass_s(fdispatch_unbox_s(F[rs1]));
}
FCVT.S.W {
encoding: b1101000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, {name(rs1)}";
if(FLEN==32)
F[rd] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8});
else { // NaN boxing
val res[32] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8});
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
}
FCVT.S.WU {
encoding: b1101000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, {name(rs1)}";
if(FLEN==32)
F[rd] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8});
else { // NaN boxing
val res[32] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8});
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
}
FMV.X.W {
encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"{name(rd)}, f{rs1}";
X[rd]<=sext(F[rs1]{32});
}
FMV.W.X {
encoding: b1111000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"f{rd}, {name(rs1)}";
if(FLEN==32)
F[rd] <= X[rs1]{32};
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(X[rs1]{32}, FLEN);
}
}
}
}
InsructionSet RV64F extends RV32F{
instructions{
FCVT.L.S { // fp to 64bit signed integer
encoding: b1100000 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"x{rd}, f{rs1}";
val res[64] <= fdispatch_fcvt_32_64(fdispatch_unbox_s(F[rs1]), zext(0, 32), rm{8});
X[rd]<= sext(res);
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FCVT.LU.S { // fp to 64bit unsigned integer
encoding: b1100000 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"x{rd}, f{rs1}";
val res[64] <= fdispatch_fcvt_32_64(fdispatch_unbox_s(F[rs1]), zext(1, 32), rm{8});
X[rd]<= zext(res);
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FCVT.S.L { // 64bit signed int to to fp
encoding: b1101000 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, x{rs1}";
val res[32] <= fdispatch_fcvt_64_32(X[rs1], zext(2, 32));
if(FLEN==32)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
}
FCVT.S.LU { // 64bit unsigned int to to fp
encoding: b1101000 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, x{rs1}";
val res[32] <=fdispatch_fcvt_64_32(X[rs1], zext(3,32));
if(FLEN==32)
F[rd] <= res;
else { // NaN boxing
val upper[FLEN] <= -1;
F[rd] <= (upper<<32) | zext(res, FLEN);
}
}
}
}

160
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import "RISCVBase.core_desc"
InsructionSet RV32M extends RISCVBase {
constants {
MAXLEN:=128
}
instructions{
MUL{
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
X[rd]<= zext(res , XLEN);
}
}
MULH {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val res[MAXLEN] <= sext(X[rs1], MAXLEN) * sext(X[rs2], MAXLEN);
X[rd]<= zext(res >> XLEN, XLEN);
}
}
MULHSU {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val res[MAXLEN] <= sext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
X[rd]<= zext(res >> XLEN, XLEN);
}
}
MULHU {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
X[rd]<= zext(res >> XLEN, XLEN);
}
}
DIV {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
if(X[rs2]!=0){
val M1[XLEN] <= -1;
val XLM1[8] <= XLEN-1;
val ONE[XLEN] <= 1;
val MMIN[XLEN] <= ONE<<XLM1;
if(X[rs1]==MMIN && X[rs2]==M1)
X[rd] <= MMIN;
else
X[rd] <= X[rs1]s / X[rs2]s;
}else
X[rd] <= -1;
}
}
DIVU {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
if(X[rs2]!=0)
X[rd] <= X[rs1] / X[rs2];
else
X[rd] <= -1;
}
}
REM {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
if(X[rs2]!=0) {
val M1[XLEN] <= -1; // constant -1
val XLM1[32] <= XLEN-1;
val ONE[XLEN] <= 1;
val MMIN[XLEN] <= ONE<<XLM1; // -2^(XLEN-1)
if(X[rs1]==MMIN && X[rs2]==M1)
X[rd] <= 0;
else
X[rd] <= X[rs1]'s % X[rs2]'s;
} else
X[rd] <= X[rs1];
}
}
REMU {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
if(X[rs2]!=0)
X[rd] <= X[rs1] % X[rs2];
else
X[rd] <= X[rs1];
}
}
}
}
InsructionSet RV64M extends RV32M {
instructions{
MULW{
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
X[rd]<= sext(X[rs1]{32} * X[rs2]{32});
}
}
DIVW {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0111011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
if(X[rs2]!=0){
val M1[32] <= -1;
val ONE[32] <= 1;
val MMIN[32] <= ONE<<31;
if(X[rs1]{32}==MMIN && X[rs2]{32}==M1)
X[rd] <= -1<<31;
else
X[rd] <= sext(X[rs1]{32}s / X[rs2]{32}s);
}else
X[rd] <= -1;
}
}
DIVUW {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
if(X[rs2]{32}!=0)
X[rd] <= sext(X[rs1]{32} / X[rs2]{32});
else
X[rd] <= -1;
}
}
REMW {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0111011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
if(X[rs2]!=0) {
val M1[32] <= -1; // constant -1
val ONE[32] <= 1;
val MMIN[32] <= ONE<<31; // -2^(XLEN-1)
if(X[rs1]{32}==MMIN && X[rs2]==M1)
X[rd] <= 0;
else
X[rd] <= sext(X[rs1]{32}s % X[rs2]{32}s);
} else
X[rd] <= sext(X[rs1]{32});
}
}
REMUW {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0111011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
if(X[rs2]{32}!=0)
X[rd] <= sext(X[rs1]{32} % X[rs2]{32});
else
X[rd] <= sext(X[rs1]{32});
}
}
}
}

13
gen_input/TGC5C.core_desc
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@ -1,13 +0,0 @@
import "ISA/RVI.core_desc"
import "ISA/RVM.core_desc"
import "ISA/RVC.core_desc"
Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned int MISA_VAL = 0b01000000000000000001000100000100;
unsigned int MARCHID_VAL = 0x80000003;
}
}

70
gen_input/minres_rv.core_desc Normal file
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import "RV32I.core_desc"
import "RV64I.core_desc"
import "RVM.core_desc"
import "RVA.core_desc"
import "RVC.core_desc"
import "RVF.core_desc"
import "RVD.core_desc"
Core MNRV32 provides RV32I, RV32IC {
constants {
XLEN:=32;
PCLEN:=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100000101;
PGSIZE := 0x1000; //1 << 12;
PGMASK := 0xfff; //PGSIZE-1
}
}
/*
Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
constants {
XLEN:=32;
PCLEN:=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100000101;
PGSIZE := 0x1000; //1 << 12;
PGMASK := 0xfff; //PGSIZE-1
}
}
Core RV32GC provides RV32I, RV32M, RV32A, RV32F, RV32D, RV32IC, RV32FC, RV32DC {
constants {
XLEN:=32;
FLEN:=64;
PCLEN:=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100101101;
PGSIZE := 0x1000; //1 << 12;
PGMASK := 0xfff; //PGSIZE-1
}
}
Core RV64I provides RV64I {
constants {
XLEN:=64;
PCLEN:=64;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b10000000000001000000000100000000;
PGSIZE := 0x1000; //1 << 12;
PGMASK := 0xfff; //PGSIZE-1
}
}
Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV64IC, RV32FC, RV32DC {
constants {
XLEN:=64;
FLEN:=64;
PCLEN:=64;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100101101;
PGSIZE := 0x1000; //1 << 12;
PGMASK := 0xfff; //PGSIZE-1
}
}
*/

177
gen_input/templates/CORENAME.h.gtl
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@ -1,177 +0,0 @@
/*******************************************************************************
* Copyright (C) 2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
<%
def nativeTypeSize(int size){
if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
}
def getRegisterSizes(){
def regs = registers.collect{nativeTypeSize(it.size)}
regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
return regs
}
def getRegisterOffsets(){
def offset = 0
def offsets = []
getRegisterSizes().each { size ->
offsets<<offset
offset+=size/8
}
return offsets
}
def byteSize(int size){
if(size<=8) return 8;
if(size<=16) return 16;
if(size<=32) return 32;
if(size<=64) return 64;
return 128;
}
def getCString(def val){
return val.toString()+'ULL'
}
%>
#ifndef _${coreDef.name.toUpperCase()}_H_
#define _${coreDef.name.toUpperCase()}_H_
// clang-format off
#include <array>
#include <iss/arch/traits.h>
#include <iss/arch_if.h>
#include <iss/vm_if.h>
namespace iss {
namespace arch {
struct ${coreDef.name.toLowerCase()};
template <> struct traits<${coreDef.name.toLowerCase()}> {
constexpr static char const* const core_type = "${coreDef.name}";
static constexpr std::array<const char*, ${registers.size()}> reg_names{
{"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
static constexpr std::array<const char*, ${registers.size()}> reg_aliases{
{"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};
enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
enum reg_e {
${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
};
using reg_t = uint${addrDataWidth}_t;
using addr_t = uint${addrDataWidth}_t;
using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> reg_bit_widths{
{${getRegisterSizes().join(',')}}};
static constexpr std::array<const uint32_t, ${getRegisterOffsets().size()}> reg_byte_offsets{
{${getRegisterOffsets().join(',')}}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
enum sreg_flag_e { FLAGS };
enum mem_type_e { ${spaces.collect{it.name}.join(', ')}, IMEM = MEM };
enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
${instr.instruction.name} = ${index},<%}%>
MAX_OPCODE
};
};
struct ${coreDef.name.toLowerCase()}: public arch_if {
using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
using reg_t = typename traits<${coreDef.name.toLowerCase()}>::reg_t;
using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
${coreDef.name.toLowerCase()}();
~${coreDef.name.toLowerCase()}();
void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override;
inline uint64_t get_icount() { return reg.icount; }
inline bool should_stop() { return interrupt_sim; }
inline uint64_t stop_code() { return interrupt_sim; }
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
inline uint32_t get_last_branch() { return reg.last_branch; }
#pragma pack(push, 1)
struct ${coreDef.name}_regs {<%
registers.each { reg -> if(reg.size>0) {%>
uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
}}%>
uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0;
uint64_t cycle = 0;
uint64_t instret = 0;
uint32_t instruction = 0;
uint32_t last_branch = 0;
} reg;
#pragma pack(pop)
std::array<address_type, 4> addr_mode;
uint64_t interrupt_sim=0;
<%
def fcsr = registers.find {it.name=='FCSR'}
if(fcsr != null) {%>
uint${fcsr.size}_t get_fcsr(){return reg.FCSR;}
void set_fcsr(uint${fcsr.size}_t val){reg.FCSR = val;}
<%} else { %>
uint32_t get_fcsr(){return 0;}
void set_fcsr(uint32_t val){}
<%}%>
};
}
}
#endif /* _${coreDef.name.toUpperCase()}_H_ */
// clang-format on

12
gen_input/templates/CORENAME_cyles.txt.gtl
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@ -1,12 +0,0 @@
{
"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
{
"name" : "${instr.name}",
"size" : ${instr.length},
"encoding": "${instr.encoding}",
"mask": "${instr.mask}",
"branch": ${instr.modifiesPC},
"delay" : ${instr.isConditional?"[1,1]":"1"}
}<%}%>
]
}

21
gen_input/templates/CORENAME_instr.yaml.gtl
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@ -1,21 +0,0 @@
<% def getInstructionGroups() {
def instrGroups = [:]
instructions.each {
def groupName = it['instruction'].eContainer().name
if(!instrGroups.containsKey(groupName)) {
instrGroups[groupName]=[]
}
instrGroups[groupName]+=it;
}
instrGroups
}%><%int index = 0; getInstructionGroups().each{name, instrList -> %>
${name}: <% instrList.each { %>
${it.instruction.name}:
index: ${index++}
encoding: ${it.encoding}
mask: ${it.mask}<%if(it.attributes.size) {%>
attributes: ${it.attributes}<%}%>
size: ${it.length}
branch: ${it.modifiesPC}
delay: ${it.isConditional?"[1,1]":"1"}<%}}%>

131
gen_input/templates/CORENAME_sysc.cpp.gtl
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@ -1,131 +0,0 @@
/*******************************************************************************
* Copyright (C) 2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
// clang-format off
#include <sysc/iss_factory.h>
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_mu_p.h>
#include <sysc/sc_core_adapter.h>
#include <sysc/core_complex.h>
#include <array>
<%
def array_count = coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e"? 3 : 2;
%>
namespace iss {
namespace interp {
using namespace sysc;
volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
}),
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%}%>
};
}
#if defined(WITH_LLVM)
namespace llvm {
using namespace sysc;
volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
}),
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%}%>
};
}
#endif
#if defined(WITH_TCC)
namespace tcc {
using namespace sysc;
volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
}),
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%}%>
};
}
#endif
#if defined(WITH_ASMJIT)
namespace asmjit {
using namespace sysc;
volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
}),
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%}%>
};
}
#endif
}
// clang-format on

371
gen_input/templates/asmjit/CORENAME.cpp.gtl
View File

@ -1,371 +0,0 @@
/*******************************************************************************
* Copyright (C) 2017-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
// clang-format off
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
#include <iss/asmjit/vm_base.h>
#include <asmjit/asmjit.h>
#include <util/logging.h>
#include <iss/instruction_decoder.h>
<%def fcsr = registers.find {it.name=='FCSR'}
if(fcsr != null) {%>
#include <vm/fp_functions.h><%}%>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
#include <fmt/format.h>
#include <array>
#include <iss/debugger/riscv_target_adapter.h>
namespace iss {
namespace asmjit {
namespace ${coreDef.name.toLowerCase()} {
using namespace ::asmjit;
using namespace iss::arch;
using namespace iss::debugger;
template <typename ARCH> class vm_impl : public iss::asmjit::vm_base<ARCH> {
public:
using traits = arch::traits<ARCH>;
using super = typename iss::asmjit::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
using mem_type_e = typename super::mem_type_e;
using addr_t = typename super::addr_t;
vm_impl();
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
target_adapter_if *accquire_target_adapter(server_if *srv) override {
debugger_if::dbg_enabled = true;
if (vm_base<ARCH>::tgt_adapter == nullptr)
vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
return vm_base<ARCH>::tgt_adapter;
}
protected:
using super::get_ptr_for;
using super::get_reg_for;
using super::get_reg_for_Gp;
using super::load_reg_from_mem;
using super::load_reg_from_mem_Gp;
using super::write_reg_to_mem;
using super::gen_read_mem;
using super::gen_write_mem;
using super::gen_leave;
using super::gen_sync;
using this_class = vm_impl<ARCH>;
using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
enum globals_e {TVAL = 0, GLOBALS_SIZE};
void gen_block_prologue(jit_holder& jh) override;
void gen_block_epilogue(jit_holder& jh) override;
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
<%if(fcsr != null) {%>
inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
<%}%>
void gen_instr_prologue(jit_holder& jh);
void gen_instr_epilogue(jit_holder& jh);
inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause);
template <typename T, typename = typename std::enable_if<std::is_integral<T>::value>::type> void gen_set_tval(jit_holder& jh, T new_tval) ;
void gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) ;
template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
inline S sext(U from) {
auto mask = (1ULL<<W) - 1;
auto sign_mask = 1ULL<<(W-1);
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
}
<%functions.each{ it.eachLine { %>
${it}<%}%>
<%}%>
private:
/****************************************************************************
* start opcode definitions
****************************************************************************/
struct instruction_descriptor {
uint32_t length;
uint32_t value;
uint32_t mask;
compile_func op;
};
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
}};
//needs to be declared after instr_descr
decoder instr_decoder;
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
/* instruction ${idx}: ${instr.name} */
continuation_e __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, jit_holder& jh){
uint64_t PC = pc.val;
<%instr.fields.eachLine{%>${it}
<%}%>if(this->disass_enabled){
/* generate disass */
<%instr.disass.eachLine{%>
${it}<%}%>
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
jh.disass_collection.push_back(mnemonic_ptr);
jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build<void, void *, uint64_t, char *>());
call_print_disass->setArg(0, jh.arch_if_ptr);
call_print_disass->setArg(1, pc.val);
call_print_disass->setArg(2, mnemonic_ptr);
}
x86::Compiler& cc = jh.cc;
cc.comment(fmt::format("${instr.name}_{:#x}:",pc.val).c_str());
gen_sync(jh, PRE_SYNC, ${idx});
mov(cc, jh.pc, pc.val);
gen_set_tval(jh, instr);
pc = pc+${instr.length/8};
mov(cc, jh.next_pc, pc.val);
gen_instr_prologue(jh);
cc.comment("//behavior:");
/*generate behavior*/
<%instr.behavior.eachLine{%>${it}
<%}%>
gen_sync(jh, POST_SYNC, ${idx});
gen_instr_epilogue(jh);
return returnValue;
}
<%}%>
/****************************************************************************
* end opcode definitions
****************************************************************************/
continuation_e illegal_instruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
x86::Compiler& cc = jh.cc;
if(this->disass_enabled){
auto mnemonic = std::string("illegal_instruction");
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
jh.disass_collection.push_back(mnemonic_ptr);
jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build<void, void *, uint64_t, char *>());
call_print_disass->setArg(0, jh.arch_if_ptr);
call_print_disass->setArg(1, pc.val);
call_print_disass->setArg(2, mnemonic_ptr);
}
cc.comment(fmt::format("illegal_instruction{:#x}:",pc.val).c_str());
gen_sync(jh, PRE_SYNC, instr_descr.size());
mov(cc, jh.pc, pc.val);
gen_set_tval(jh, instr);
pc = pc + ((instr & 3) == 3 ? 4 : 2);
mov(cc, jh.next_pc, pc.val);
gen_instr_prologue(jh);
cc.comment("//behavior:");
gen_raise(jh, 0, 2);
gen_sync(jh, POST_SYNC, instr_descr.size());
gen_instr_epilogue(jh);
return ILLEGAL_INSTR;
}
};
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
template <typename ARCH>
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
: vm_base<ARCH>(core, core_id, cluster_id)
, instr_decoder([this]() {
std::vector<generic_instruction_descriptor> g_instr_descr;
g_instr_descr.reserve(instr_descr.size());
for (uint32_t i = 0; i < instr_descr.size(); ++i) {
generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
g_instr_descr.push_back(new_instr_descr);
}
return std::move(g_instr_descr);
}()) {}
template <typename ARCH>
continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
enum {TRAP_ID=1<<16};
code_word_t instr = 0;
phys_addr_t paddr(pc);
auto *const data = (uint8_t *)&instr;
if(this->core.has_mmu())
paddr = this->core.virt2phys(pc);
auto res = this->core.read(paddr, 4, data);
if (res != iss::Ok)
return ILLEGAL_FETCH;
if (instr == 0x0000006f || (instr&0xffff)==0xa001)
return JUMP_TO_SELF;
++inst_cnt;
uint32_t inst_index = instr_decoder.decode_instr(instr);
compile_func f = nullptr;
if(inst_index < instr_descr.size())
f = instr_descr[inst_index].op;
if (f == nullptr)
f = &this_class::illegal_instruction;
return (this->*f)(pc, instr, jh);
}
template <typename ARCH>
void vm_impl<ARCH>::gen_instr_prologue(jit_holder& jh) {
auto& cc = jh.cc;
cc.comment("//gen_instr_prologue");
x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state);
}
template <typename ARCH>
void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
auto& cc = jh.cc;
cc.comment("//gen_instr_epilogue");
x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
cmp(cc, current_trap_state, 0);
cc.jne(jh.trap_entry);
cc.inc(get_ptr_for(jh, traits::ICOUNT));
cc.inc(get_ptr_for(jh, traits::CYCLE));
}
template <typename ARCH>
void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
jh.pc = load_reg_from_mem_Gp(jh, traits::PC);
jh.next_pc = load_reg_from_mem_Gp(jh, traits::NEXT_PC);
jh.globals.resize(GLOBALS_SIZE);
jh.globals[TVAL] = get_reg_Gp(jh.cc, 64, false);
}
template <typename ARCH>
void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
x86::Compiler& cc = jh.cc;
cc.comment("//gen_block_epilogue");
cc.ret(jh.next_pc);
cc.bind(jh.trap_entry);
this->write_back(jh);
x86::Gp current_trap_state = get_reg_for_Gp(cc, traits::TRAP_STATE);
mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
x86::Gp current_pc = get_reg_for_Gp(cc, traits::PC);
mov(cc, current_pc, get_ptr_for(jh, traits::PC));
cc.comment("//enter trap call;");
InvokeNode* call_enter_trap;
cc.invoke(&call_enter_trap, &enter_trap, FuncSignature::build<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
call_enter_trap->setArg(0, jh.arch_if_ptr);
call_enter_trap->setArg(1, current_trap_state);
call_enter_trap->setArg(2, current_pc);
call_enter_trap->setArg(3, jh.globals[TVAL]);
x86_reg_t current_next_pc = get_reg_for(cc, traits::NEXT_PC);
mov(cc, current_next_pc, get_ptr_for(jh, traits::NEXT_PC));
mov(cc, jh.next_pc, current_next_pc);
mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(UNKNOWN_JUMP));
cc.ret(jh.next_pc);
}
template <typename ARCH>
inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
auto& cc = jh.cc;
cc.comment("//gen_raise");
auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);
cc.jmp(jh.trap_entry);
}
template <typename ARCH>
template <typename T, typename>
void vm_impl<ARCH>::gen_set_tval(jit_holder& jh, T new_tval) {
mov(jh.cc, jh.globals[TVAL], new_tval);
}
template <typename ARCH>
void vm_impl<ARCH>::gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) {
if(nonstd::holds_alternative<x86::Gp>(_new_tval)) {
x86::Gp new_tval = nonstd::get<x86::Gp>(_new_tval);
if(new_tval.size() < 8)
new_tval = gen_ext_Gp(jh.cc, new_tval, 64, false);
mov(jh.cc, jh.globals[TVAL], new_tval);
} else {
throw std::runtime_error("Variant not supported in gen_set_tval");
}
}
} // namespace tgc5c
template <>
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
} // namespace asmjit
} // namespace iss
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_mu_p.h>
#include <iss/factory.h>
namespace iss {
namespace {
volatile std::array<bool, 2> dummy = {
core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};
}),
core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};
})
};
}
}
// clang-format on

367
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@ -1,367 +0,0 @@
/*******************************************************************************
* Copyright (C) 2017-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
<%
def nativeTypeSize(int size){
if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
}
%>
// clang-format off
#include <cstdint>
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
#include <iss/interp/vm_base.h>
#include <vm/fp_functions.h>
#include <util/logging.h>
#include <boost/coroutine2/all.hpp>
#include <functional>
#include <exception>
#include <vector>
#include <sstream>
#include <iss/instruction_decoder.h>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
#include <fmt/format.h>
#include <array>
#include <iss/debugger/riscv_target_adapter.h>
namespace iss {
namespace interp {
namespace ${coreDef.name.toLowerCase()} {
using namespace iss::arch;
using namespace iss::debugger;
using namespace std::placeholders;
struct memory_access_exception : public std::exception{
memory_access_exception(){}
};
template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
public:
using traits = arch::traits<ARCH>;
using super = typename iss::interp::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
using addr_t = typename super::addr_t;
using reg_t = typename traits::reg_t;
using mem_type_e = typename traits::mem_type_e;
using opcode_e = typename traits::opcode_e;
vm_impl();
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
target_adapter_if *accquire_target_adapter(server_if *srv) override {
debugger_if::dbg_enabled = true;
if (super::tgt_adapter == nullptr)
super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
return super::tgt_adapter;
}
protected:
using this_class = vm_impl<ARCH>;
using compile_ret_t = virt_addr_t;
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
<%
def fcsr = registers.find {it.name=='FCSR'}
if(fcsr != null) {%>
inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
<%}%>
virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
// some compile time constants
inline void raise(uint16_t trap_id, uint16_t cause){
auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
this->core.reg.trap_state = trap_val;
}
inline void leave(unsigned lvl){
this->core.leave_trap(lvl);
}
inline void wait(unsigned type){
this->core.wait_until(type);
}
inline void set_tval(uint64_t new_tval){
tval = new_tval;
}
uint64_t fetch_count{0};
uint64_t tval{0};
using yield_t = boost::coroutines2::coroutine<void>::push_type;
using coro_t = boost::coroutines2::coroutine<void>::pull_type;
std::vector<coro_t> spawn_blocks;
template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
inline S sext(U from) {
auto mask = (1ULL<<W) - 1;
auto sign_mask = 1ULL<<(W-1);
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
}
inline void process_spawn_blocks() {
if(spawn_blocks.size()==0) return;
for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
if(*it){
(*it)();
++it;
} else
spawn_blocks.erase(it);
}
<%functions.each{ it.eachLine { %>
${it}<%}%>
<%}%>
private:
/****************************************************************************
* start opcode definitions
****************************************************************************/
struct instruction_descriptor {
uint32_t length;
uint32_t value;
uint32_t mask;
typename arch::traits<ARCH>::opcode_e op;
};
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
{${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
}};
//needs to be declared after instr_descr
decoder instr_decoder;
iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
if(this->core.has_mmu()) {
auto phys_pc = this->core.virt2phys(pc);
// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
// if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
// if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
// if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok)
// return iss::Err;
// } else {
if (this->core.read(phys_pc, 4, data) != iss::Ok)
return iss::Err;
// }
} else {
if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok)
return iss::Err;
}
return iss::Ok;
}
};
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
volatile CODE_WORD x = insn;
insn = 2 * x;
}
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
// according to
// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
#ifdef __GCC__
constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
#elif __cplusplus < 201402L
constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
#else
constexpr size_t bit_count(uint32_t u) {
size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
return ((uCount + (uCount >> 3)) & 030707070707) % 63;
}
#endif
template <typename ARCH>
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
: vm_base<ARCH>(core, core_id, cluster_id)
, instr_decoder([this]() {
std::vector<generic_instruction_descriptor> g_instr_descr;
g_instr_descr.reserve(instr_descr.size());
for (uint32_t i = 0; i < instr_descr.size(); ++i) {
generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
g_instr_descr.push_back(new_instr_descr);
}
return std::move(g_instr_descr);
}()) {}
inline bool is_icount_limit_enabled(finish_cond_e cond){
return (cond & finish_cond_e::ICOUNT_LIMIT) == finish_cond_e::ICOUNT_LIMIT;
}
inline bool is_fcount_limit_enabled(finish_cond_e cond){
return (cond & finish_cond_e::FCOUNT_LIMIT) == finish_cond_e::FCOUNT_LIMIT;
}
inline bool is_jump_to_self_enabled(finish_cond_e cond){
return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
}
template <typename ARCH>
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t count_limit){
auto pc=start;
auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
auto* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
auto& trap_state = this->core.reg.trap_state;
auto& icount = this->core.reg.icount;
auto& cycle = this->core.reg.cycle;
auto& instret = this->core.reg.instret;
auto& instr = this->core.reg.instruction;
// we fetch at max 4 byte, alignment is 2
auto *const data = reinterpret_cast<uint8_t*>(&instr);
while(!this->core.should_stop() &&
!(is_icount_limit_enabled(cond) && icount >= count_limit) &&
!(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
if(this->debugging_enabled())
this->tgt_adapter->check_continue(*PC);
pc.val=*PC;
if(fetch_ins(pc, data)!=iss::Ok){
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
process_spawn_blocks();
if(this->sync_exec && POST_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
pc.val = super::core.enter_trap(arch::traits<ARCH>::RV_CAUSE_FETCH_ACCESS<<16, pc.val, 0);
} else {
if (is_jump_to_self_enabled(cond) &&
(instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
uint32_t inst_index = instr_decoder.decode_instr(instr);
opcode_e inst_id = arch::traits<ARCH>::opcode_e::MAX_OPCODE;;
if(inst_index <instr_descr.size())
inst_id = instr_descr[inst_index].op;
// pre execution stuff
this->core.reg.last_branch = 0;
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
try{
switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
case arch::traits<ARCH>::opcode_e::${instr.name}: {
<%instr.fields.eachLine{%>${it}
<%}%>if(this->disass_enabled){
/* generate console output when executing the command */<%instr.disass.eachLine{%>
${it}<%}%>
this->core.disass_output(pc.val, mnemonic);
}
// used registers<%instr.usedVariables.each{ k,v->
if(v.isArray) {%>
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %>
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
<%}}%>// calculate next pc value
*NEXT_PC = *PC + ${instr.length/8};
// execute instruction<%instr.behavior.eachLine{%>
${it}<%}%>
break;
}// @suppress("No break at end of case")<%}%>
default: {
*NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
raise(0, 2);
}
}
}catch(memory_access_exception& e){}
// post execution stuff
process_spawn_blocks();
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
// if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt
// this->core.reg.trap_state = this->core.reg.pending_trap;
// trap check
if(trap_state!=0){
//In case of Instruction address misaligned (cause = 0 and trapid = 0) need the targeted addr (in tval)
auto mcause = (trap_state>>16) & 0xff;
super::core.enter_trap(trap_state, pc.val, mcause ? instr:tval);
} else {
icount++;
instret++;
}
*PC = *NEXT_PC;
this->core.reg.trap_state = this->core.reg.pending_trap;
}
fetch_count++;
cycle++;
}
return pc;
}
} // namespace ${coreDef.name.toLowerCase()}
template <>
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
} // namespace interp
} // namespace iss
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_mu_p.h>
#include <iss/factory.h>
namespace iss {
namespace {
volatile std::array<bool, 2> dummy = {
core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};
}),
core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};
})
};
}
}
// clang-format on

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{
"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
{
"name" : "${instr.name}",
"size" : ${instr.length},
"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
}<%}%>
]
}

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/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
<%
import com.minres.coredsl.coreDsl.Register
import com.minres.coredsl.coreDsl.RegisterFile
import com.minres.coredsl.coreDsl.RegisterAlias
def getTypeSize(size){
if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
}
def getOriginalName(reg){
if( reg.original instanceof RegisterFile) {
if( reg.index != null ) {
return reg.original.name+generator.generateHostCode(reg.index)
} else {
return reg.original.name
}
} else if(reg.original instanceof Register){
return reg.original.name
}
}
def getRegisterNames(){
def regNames = []
allRegs.each { reg ->
if( reg instanceof RegisterFile) {
(reg.range.right..reg.range.left).each{
regNames+=reg.name.toLowerCase()+it
}
} else if(reg instanceof Register){
regNames+=reg.name.toLowerCase()
}
}
return regNames
}
def getRegisterAliasNames(){
def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
if( reg instanceof RegisterFile) {
return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
} else if(reg instanceof Register){
regMap[reg.name]?:reg.name.toLowerCase()
}
}.flatten()
}
%>
#ifndef _${coreDef.name.toUpperCase()}_H_
#define _${coreDef.name.toUpperCase()}_H_
#include <array>
#include <iss/arch/traits.h>
#include <iss/arch_if.h>
#include <iss/vm_if.h>
namespace iss {
namespace arch {
struct ${coreDef.name.toLowerCase()};
template <> struct traits<${coreDef.name.toLowerCase()}> {
constexpr static char const* const core_type = "${coreDef.name}";
static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
{"${getRegisterNames().join("\", \"")}"}};
static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
{"${getRegisterAliasNames().join("\", \"")}"}};
enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
enum reg_e {<%
allRegs.each { reg ->
if( reg instanceof RegisterFile) {
(reg.range.right..reg.range.left).each{%>
${reg.name}${it},<%
}
} else if(reg instanceof Register){ %>
${reg.name},<%
}
}%>
NUM_REGS,
NEXT_${pc.name}=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
LAST_BRANCH,
ICOUNT<%
allRegs.each { reg ->
if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
${reg.name} = ${aliasname}<%
}
}%>
};
using reg_t = uint${regDataWidth}_t;
using addr_t = uint${addrDataWidth}_t;
using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
{${regSizes.join(",")}}};
static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
{${regOffsets.join(",")}}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
enum sreg_flag_e { FLAGS };
enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
};
struct ${coreDef.name.toLowerCase()}: public arch_if {
using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
using reg_t = typename traits<${coreDef.name.toLowerCase()}>::reg_t;
using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
${coreDef.name.toLowerCase()}();
~${coreDef.name.toLowerCase()}();
void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override;
/// deprecated
void get_reg(short idx, std::vector<uint8_t>& value) override {}
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
bool get_flag(int flag) override {return false;}
void set_flag(int, bool value) override {};
/// deprecated
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
inline uint64_t get_icount() { return reg.icount; }
inline bool should_stop() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
} else
return virt2phys(addr);
}
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
inline uint32_t get_last_branch() { return reg.last_branch; }
protected:
struct ${coreDef.name}_regs {<%
allRegs.each { reg ->
if( reg instanceof RegisterFile) {
(reg.range.right..reg.range.left).each{%>
uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
}
} else if(reg instanceof Register){ %>
uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
}
}%>
uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0;
} reg;
std::array<address_type, 4> addr_mode;
bool interrupt_sim=false;
<%
def fcsr = allRegs.find {it.name=='FCSR'}
if(fcsr != null) {%>
uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}
<%} else { %>
uint32_t get_fcsr(){return 0;}
void set_fcsr(uint32_t val){}
<%}%>
};
}
}
#endif /* _${coreDef.name.toUpperCase()}_H_ */

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/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
<%
import com.minres.coredsl.coreDsl.Register
import com.minres.coredsl.coreDsl.RegisterFile
import com.minres.coredsl.coreDsl.RegisterAlias
def getOriginalName(reg){
if( reg.original instanceof RegisterFile) {
if( reg.index != null ) {
return reg.original.name+generator.generateHostCode(reg.index)
} else {
return reg.original.name
}
} else if(reg.original instanceof Register){
return reg.original.name
}
}
def getRegisterNames(){
def regNames = []
allRegs.each { reg ->
if( reg instanceof RegisterFile) {
(reg.range.right..reg.range.left).each{
regNames+=reg.name.toLowerCase()+it
}
} else if(reg instanceof Register){
regNames+=reg.name.toLowerCase()
}
}
return regNames
}
def getRegisterAliasNames(){
def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
if( reg instanceof RegisterFile) {
return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
} else if(reg instanceof Register){
regMap[reg.name]?:reg.name.toLowerCase()
}
}.flatten()
}
%>
#include "util/ities.h"
#include <util/logging.h>
#include <elfio/elfio.hpp>
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
#ifdef __cplusplus
extern "C" {
#endif
#include <ihex.h>
#ifdef __cplusplus
}
#endif
#include <cstdio>
#include <cstring>
#include <fstream>
using namespace iss::arch;
constexpr std::array<const char*, ${getRegisterNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
constexpr std::array<const char*, ${getRegisterAliasNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
reg.icount = 0;
}
${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x3;
reg.icount=0;
}
uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
return reinterpret_cast<uint8_t*>(&reg);
}
${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
return phys_addr_t(pc); // change logical address to physical address
}

246
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/*******************************************************************************
* Copyright (C) 2020 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
#include <iss/interp/vm_base.h>
#include <util/logging.h>
#include <sstream>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
#include <fmt/format.h>
#include <array>
#include <iss/debugger/riscv_target_adapter.h>
namespace iss {
namespace interp {
namespace ${coreDef.name.toLowerCase()} {
using namespace iss::arch;
using namespace iss::debugger;
template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
public:
using super = typename iss::interp::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
using addr_t = typename super::addr_t;
using reg_t = typename traits<ARCH>::reg_t;
using iss::interp::vm_base<ARCH>::get_reg;
vm_impl();
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
target_adapter_if *accquire_target_adapter(server_if *srv) override {
debugger_if::dbg_enabled = true;
if (super::tgt_adapter == nullptr)
super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
return super::tgt_adapter;
}
protected:
using this_class = vm_impl<ARCH>;
using compile_ret_t = virt_addr_t;
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
virt_addr_t execute_inst(virt_addr_t start, std::function<bool(void)> pred) override;
// some compile time constants
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
std::array<compile_func, LUT_SIZE> lut;
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
std::array<compile_func, LUT_SIZE> lut_11;
std::array<compile_func *, 4> qlut;
std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
compile_func f) {
if (pos < 0) {
lut[idx] = f;
} else {
auto bitmask = 1UL << pos;
if ((mask & bitmask) == 0) {
expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
} else {
if ((valid & bitmask) == 0) {
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
} else {
auto new_val = idx << 1;
if ((value & bitmask) != 0) new_val++;
expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
}
}
}
}
inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
if (pos >= 0) {
auto bitmask = 1UL << pos;
if ((mask & bitmask) == 0) {
lut_val = extract_fields(pos - 1, val, mask, lut_val);
} else {
auto new_val = lut_val << 1;
if ((val & bitmask) != 0) new_val++;
lut_val = extract_fields(pos - 1, val, mask, new_val);
}
}
return lut_val;
}
void raise_trap(uint16_t trap_id, uint16_t cause){
auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
this->template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE) = trap_val;
this->template get_reg<uint32_t>(arch::traits<ARCH>::NEXT_PC) = std::numeric_limits<uint32_t>::max();
}
void leave_trap(unsigned lvl){
this->core.leave_trap(lvl);
auto pc_val = super::template read_mem<reg_t>(traits<ARCH>::CSR, (lvl << 8) + 0x41);
this->template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc_val;
this->template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
}
void wait(unsigned type){
this->core.wait_until(type);
}
private:
/****************************************************************************
* start opcode definitions
****************************************************************************/
struct InstructionDesriptor {
size_t length;
uint32_t value;
uint32_t mask;
compile_func op;
};
const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name} */
{${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
}};
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
/* instruction ${idx}: ${instr.name} */
compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){<%instr.code.eachLine{%>
${it}<%}%>
}
<%}%>
/****************************************************************************
* end opcode definitions
****************************************************************************/
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
pc = pc + ((instr & 3) == 3 ? 4 : 2);
return pc;
}
};
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
volatile CODE_WORD x = insn;
insn = 2 * x;
}
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
template <typename ARCH>
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
: vm_base<ARCH>(core, core_id, cluster_id) {
qlut[0] = lut_00.data();
qlut[1] = lut_01.data();
qlut[2] = lut_10.data();
qlut[3] = lut_11.data();
for (auto instr : instr_descr) {
auto quantrant = instr.value & 0x3;
expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
}
}
template <typename ARCH>
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t start, std::function<bool(void)> pred) {
// we fetch at max 4 byte, alignment is 2
enum {TRAP_ID=1<<16};
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
code_word_t insn = 0;
auto *const data = (uint8_t *)&insn;
auto pc=start;
while(pred){
auto paddr = this->core.v2p(pc);
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
if (this->core.read(paddr, 2, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
if ((insn & 0x3) == 0x3) // this is a 32bit instruction
if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
} else {
if (this->core.read(paddr, 4, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
}
if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
auto lut_val = extract_fields(insn);
auto f = qlut[insn & 0x3][lut_val];
if (!f)
f = &this_class::illegal_intruction;
pc = (this->*f)(pc, insn);
}
return pc;
}
} // namespace mnrv32
template <>
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
} // namespace interp
} // namespace iss

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/*******************************************************************************
* Copyright (C) 2017-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
// clang-format off
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
#include <iss/llvm/vm_base.h>
#include <util/logging.h>
#include <iss/instruction_decoder.h>
<%def fcsr = registers.find {it.name=='FCSR'}
if(fcsr != null) {%>
#include <vm/fp_functions.h><%}%>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
#include <fmt/format.h>
#include <array>
#include <iss/debugger/riscv_target_adapter.h>
namespace iss {
namespace llvm {
namespace fp_impl {
void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
}
namespace ${coreDef.name.toLowerCase()} {
using namespace ::llvm;
using namespace iss::arch;
using namespace iss::debugger;
template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
public:
using traits = arch::traits<ARCH>;
using super = typename iss::llvm::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
using addr_t = typename super::addr_t;
vm_impl();
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
target_adapter_if *accquire_target_adapter(server_if *srv) override {
debugger_if::dbg_enabled = true;
if (vm_base<ARCH>::tgt_adapter == nullptr)
vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
return vm_base<ARCH>::tgt_adapter;
}
protected:
using vm_base<ARCH>::get_reg_ptr;
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
<%if(fcsr != null) {%>
inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
<%}%>
template <typename T> inline ConstantInt *size(T type) {
return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
}
void setup_module(Module* m) override {
super::setup_module(m);
iss::llvm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE, traits::XLEN);
}
inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
}
std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
void gen_leave_behavior(BasicBlock *leave_blk) override;
void gen_raise_trap(uint16_t trap_id, uint16_t cause);
void gen_leave_trap(unsigned lvl);
void gen_wait(unsigned type);
void set_tval(uint64_t new_tval);
void set_tval(Value* new_tval);
void gen_trap_behavior(BasicBlock *) override;
void gen_instr_prologue();
void gen_instr_epilogue(BasicBlock *bb);
inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
return this->builder.CreateLoad(this->get_typeptr(i), get_reg_ptr(i), false);
}
inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val),
this->get_type(traits::XLEN));
this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
}
// some compile time constants
using this_class = vm_impl<ARCH>;
using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
code_word_t instr,
BasicBlock *bb);
template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
inline S sext(U from) {
auto mask = (1ULL<<W) - 1;
auto sign_mask = 1ULL<<(W-1);
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
}
<%functions.each{ it.eachLine { %>
${it}<%}%>
<%}%>
private:
/****************************************************************************
* start opcode definitions
****************************************************************************/
struct instruction_descriptor {
uint32_t length;
uint32_t value;
uint32_t mask;
compile_func op;
};
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
}};
//needs to be declared after instr_descr
decoder instr_decoder;
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
/* instruction ${idx}: ${instr.name} */
std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
uint64_t PC = pc.val;
<%instr.fields.eachLine{%>${it}
<%}%>if(this->disass_enabled){
/* generate console output when executing the command */<%instr.disass.eachLine{%>
${it}<%}%>
std::vector<Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(mnemonic),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
bb->setName(fmt::format("${instr.name}_0x{:X}",pc.val));
this->gen_sync(PRE_SYNC,${idx});
this->gen_set_pc(pc, traits::PC);
this->set_tval(instr);
pc=pc+ ${instr.length/8};
this->gen_set_pc(pc, traits::NEXT_PC);
this->gen_instr_prologue();
/*generate behavior*/
<%instr.behavior.eachLine{%>${it}
<%}%>
this->gen_sync(POST_SYNC, ${idx});
this->gen_instr_epilogue(bb);
this->builder.CreateBr(bb);
return returnValue;
}
<%}%>
/****************************************************************************
* end opcode definitions
****************************************************************************/
std::tuple<continuation_e, BasicBlock *> illegal_instruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
if(this->disass_enabled){
auto mnemonic = std::string("illegal_instruction");
std::vector<Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(mnemonic),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
this->gen_sync(iss::PRE_SYNC, instr_descr.size());
this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
get_reg_ptr(traits::PC), true);
this->builder.CreateStore(
this->builder.CreateAdd(this->builder.CreateLoad(this->get_typeptr(traits::ICOUNT), get_reg_ptr(traits::ICOUNT), true),
this->gen_const(64U, 1)),
get_reg_ptr(traits::ICOUNT), true);
pc = pc + ((instr & 3) == 3 ? 4 : 2);
this->set_tval(instr);
this->gen_raise_trap(0, 2); // illegal instruction trap
this->gen_sync(iss::POST_SYNC, instr_descr.size());
bb = this->leave_blk;
this->gen_instr_epilogue(bb);
this->builder.CreateBr(bb);
return std::make_tuple(ILLEGAL_INSTR, nullptr);
}
};
template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
volatile CODE_WORD x = instr;
instr = 2 * x;
}
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
template <typename ARCH>
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
: vm_base<ARCH>(core, core_id, cluster_id)
, instr_decoder([this]() {
std::vector<generic_instruction_descriptor> g_instr_descr;
g_instr_descr.reserve(instr_descr.size());
for (uint32_t i = 0; i < instr_descr.size(); ++i) {
generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
g_instr_descr.push_back(new_instr_descr);
}
return std::move(g_instr_descr);
}()) {}
template <typename ARCH>
std::tuple<continuation_e, BasicBlock *>
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
// we fetch at max 4 byte, alignment is 2
enum {TRAP_ID=1<<16};
code_word_t instr = 0;
// const typename traits::addr_t upper_bits = ~traits::PGMASK;
phys_addr_t paddr(pc);
auto *const data = (uint8_t *)&instr;
if(this->core.has_mmu())
paddr = this->core.virt2phys(pc);
auto res = this->core.read(paddr, 4, data);
if (res != iss::Ok)
return std::make_tuple(ILLEGAL_FETCH, nullptr);
if (instr == 0x0000006f || (instr&0xffff)==0xa001)
return std::make_tuple(JUMP_TO_SELF, nullptr);
++inst_cnt;
uint32_t inst_index = instr_decoder.decode_instr(instr);
compile_func f = nullptr;
if(inst_index < instr_descr.size())
f = instr_descr[inst_index].op;
if (f == nullptr) {
f = &this_class::illegal_instruction;
}
return (this->*f)(pc, instr, this_block);
}
template <typename ARCH>
void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
this->builder.SetInsertPoint(leave_blk);
this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC),get_reg_ptr(traits::NEXT_PC), false));
}
template <typename ARCH>
void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true);
this->builder.CreateBr(this->trap_blk);
}
template <typename ARCH>
void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
this->builder.CreateStore(this->gen_const(32U, static_cast<int>(UNKNOWN_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
}
template <typename ARCH>
void vm_impl<ARCH>::gen_wait(unsigned type) {
std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
this->builder.CreateCall(this->mod->getFunction("wait"), args);
}
template <typename ARCH>
inline void vm_impl<ARCH>::set_tval(uint64_t tval) {
auto tmp_tval = this->gen_const(64, tval);
this->set_tval(tmp_tval);
}
template <typename ARCH>
inline void vm_impl<ARCH>::set_tval(Value* new_tval) {
this->builder.CreateStore(this->gen_ext(new_tval, 64, false), this->tval);
}
template <typename ARCH>
void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
this->builder.SetInsertPoint(trap_blk);
auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
auto *cur_pc_val = this->builder.CreateLoad(this->get_typeptr(traits::PC), get_reg_ptr(traits::PC), true);
std::vector<Value *> args{this->core_ptr,
this->adj_to64(trap_state_val),
this->adj_to64(cur_pc_val),
this->adj_to64(this->builder.CreateLoad(this->get_type(64),this->tval))};
this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
this->builder.CreateStore(this->gen_const(32U, static_cast<int>(UNKNOWN_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
auto *trap_addr_val = this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false);
this->builder.CreateRet(trap_addr_val);
}
template <typename ARCH>
void vm_impl<ARCH>::gen_instr_prologue() {
auto* trap_val =
this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::PENDING_TRAP), get_reg_ptr(arch::traits<ARCH>::PENDING_TRAP));
this->builder.CreateStore(trap_val, get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), false);
}
template <typename ARCH>
void vm_impl<ARCH>::gen_instr_epilogue(BasicBlock *bb) {
auto* target_bb = BasicBlock::Create(this->mod->getContext(), "", this->func, bb);
auto *v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
this->gen_cond_branch(this->builder.CreateICmp(
ICmpInst::ICMP_EQ, v,
ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
target_bb, this->trap_blk, 1);
this->builder.SetInsertPoint(target_bb);
// update icount
auto* icount_val = this->builder.CreateAdd(
this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::ICOUNT), get_reg_ptr(arch::traits<ARCH>::ICOUNT)), this->gen_const(64U, 1));
this->builder.CreateStore(icount_val, get_reg_ptr(arch::traits<ARCH>::ICOUNT), false);
}
} // namespace ${coreDef.name.toLowerCase()}
template <>
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
} // namespace llvm
} // namespace iss
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_mu_p.h>
#include <iss/factory.h>
namespace iss {
namespace {
volatile std::array<bool, 2> dummy = {
core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};
}),
core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};
})
};
}
}
// clang-format on

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{
"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
{
"name" : "${instr.name}",
"size" : ${instr.length},
"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
}<%}%>
]
}

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/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
<%
import com.minres.coredsl.coreDsl.Register
import com.minres.coredsl.coreDsl.RegisterFile
import com.minres.coredsl.coreDsl.RegisterAlias
def getTypeSize(size){
if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
}
def getOriginalName(reg){
if( reg.original instanceof RegisterFile) {
if( reg.index != null ) {
return reg.original.name+generator.generateHostCode(reg.index)
} else {
return reg.original.name
}
} else if(reg.original instanceof Register){
return reg.original.name
}
}
def getRegisterNames(){
def regNames = []
allRegs.each { reg ->
if( reg instanceof RegisterFile) {
(reg.range.right..reg.range.left).each{
regNames+=reg.name.toLowerCase()+it
}
} else if(reg instanceof Register){
regNames+=reg.name.toLowerCase()
}
}
return regNames
}
def getRegisterAliasNames(){
def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
if( reg instanceof RegisterFile) {
return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
} else if(reg instanceof Register){
regMap[reg.name]?:reg.name.toLowerCase()
}
}.flatten()
}
%>
#ifndef _${coreDef.name.toUpperCase()}_H_
#define _${coreDef.name.toUpperCase()}_H_
#include <array>
#include <iss/arch/traits.h>
#include <iss/arch_if.h>
#include <iss/vm_if.h>
namespace iss {
namespace arch {
struct ${coreDef.name.toLowerCase()};
template <> struct traits<${coreDef.name.toLowerCase()}> {
constexpr static char const* const core_type = "${coreDef.name}";
static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
{"${getRegisterNames().join("\", \"")}"}};
static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
{"${getRegisterAliasNames().join("\", \"")}"}};
enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
enum reg_e {<%
allRegs.each { reg ->
if( reg instanceof RegisterFile) {
(reg.range.right..reg.range.left).each{%>
${reg.name}${it},<%
}
} else if(reg instanceof Register){ %>
${reg.name},<%
}
}%>
NUM_REGS,
NEXT_${pc.name}=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
LAST_BRANCH,
ICOUNT<%
allRegs.each { reg ->
if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
${reg.name} = ${aliasname}<%
}
}%>
};
using reg_t = uint${regDataWidth}_t;
using addr_t = uint${addrDataWidth}_t;
using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
{${regSizes.join(",")}}};
static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
{${regOffsets.join(",")}}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
enum sreg_flag_e { FLAGS };
enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
};
struct ${coreDef.name.toLowerCase()}: public arch_if {
using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
using reg_t = typename traits<${coreDef.name.toLowerCase()}>::reg_t;
using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
${coreDef.name.toLowerCase()}();
~${coreDef.name.toLowerCase()}();
void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override;
/// deprecated
void get_reg(short idx, std::vector<uint8_t>& value) override {}
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
bool get_flag(int flag) override {return false;}
void set_flag(int, bool value) override {};
/// deprecated
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
inline uint64_t get_icount() { return reg.icount; }
inline bool should_stop() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
} else
return virt2phys(addr);
}
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
inline uint32_t get_last_branch() { return reg.last_branch; }
protected:
struct ${coreDef.name}_regs {<%
allRegs.each { reg ->
if( reg instanceof RegisterFile) {
(reg.range.right..reg.range.left).each{%>
uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
}
} else if(reg instanceof Register){ %>
uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
}
}%>
uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0;
} reg;
std::array<address_type, 4> addr_mode;
bool interrupt_sim=false;
<%
def fcsr = allRegs.find {it.name=='FCSR'}
if(fcsr != null) {%>
uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}
<%} else { %>
uint32_t get_fcsr(){return 0;}
void set_fcsr(uint32_t val){}
<%}%>
};
}
}
#endif /* _${coreDef.name.toUpperCase()}_H_ */

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/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
<%
import com.minres.coredsl.coreDsl.Register
import com.minres.coredsl.coreDsl.RegisterFile
import com.minres.coredsl.coreDsl.RegisterAlias
def getOriginalName(reg){
if( reg.original instanceof RegisterFile) {
if( reg.index != null ) {
return reg.original.name+generator.generateHostCode(reg.index)
} else {
return reg.original.name
}
} else if(reg.original instanceof Register){
return reg.original.name
}
}
def getRegisterNames(){
def regNames = []
allRegs.each { reg ->
if( reg instanceof RegisterFile) {
(reg.range.right..reg.range.left).each{
regNames+=reg.name.toLowerCase()+it
}
} else if(reg instanceof Register){
regNames+=reg.name.toLowerCase()
}
}
return regNames
}
def getRegisterAliasNames(){
def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
if( reg instanceof RegisterFile) {
return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
} else if(reg instanceof Register){
regMap[reg.name]?:reg.name.toLowerCase()
}
}.flatten()
}
%>
#include "util/ities.h"
#include <util/logging.h>
#include <elfio/elfio.hpp>
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
#ifdef __cplusplus
extern "C" {
#endif
#include <ihex.h>
#ifdef __cplusplus
}
#endif
#include <cstdio>
#include <cstring>
#include <fstream>
using namespace iss::arch;
constexpr std::array<const char*, ${getRegisterNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
constexpr std::array<const char*, ${getRegisterAliasNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
reg.icount = 0;
}
${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x3;
reg.icount=0;
}
uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
return reinterpret_cast<uint8_t*>(&reg);
}
${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
return phys_addr_t(pc); // change logical address to physical address
}

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/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
#include <iss/llvm/vm_base.h>
#include <util/logging.h>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
#include <fmt/format.h>
#include <array>
#include <iss/debugger/riscv_target_adapter.h>
namespace iss {
namespace llvm {
namespace fp_impl {
void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
}
namespace ${coreDef.name.toLowerCase()} {
using namespace ::llvm;
using namespace iss::arch;
using namespace iss::debugger;
template <typename ARCH> class vm_impl : public vm::llvm::vm_base<ARCH> {
public:
using super = typename iss::llvm::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
using addr_t = typename super::addr_t;
vm_impl();
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
target_adapter_if *accquire_target_adapter(server_if *srv) override {
debugger_if::dbg_enabled = true;
if (vm_base<ARCH>::tgt_adapter == nullptr)
vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
return vm_base<ARCH>::tgt_adapter;
}
protected:
using vm_base<ARCH>::get_reg_ptr;
inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
template <typename T> inline ConstantInt *size(T type) {
return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
}
void setup_module(Module* m) override {
super::setup_module(m);
iss::llvm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
}
inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
}
std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
void gen_leave_behavior(BasicBlock *leave_blk) override;
void gen_raise_trap(uint16_t trap_id, uint16_t cause);
void gen_leave_trap(unsigned lvl);
void gen_wait(unsigned type);
void gen_trap_behavior(BasicBlock *) override;
void gen_trap_check(BasicBlock *bb);
inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
return this->builder.CreateLoad(get_reg_ptr(i), false);
}
inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
this->get_type(traits<ARCH>::XLEN));
this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
}
// some compile time constants
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
using this_class = vm_impl<ARCH>;
using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
code_word_t instr,
BasicBlock *bb);
std::array<compile_func, LUT_SIZE> lut;
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
std::array<compile_func, LUT_SIZE> lut_11;
std::array<compile_func *, 4> qlut;
std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
compile_func f) {
if (pos < 0) {
lut[idx] = f;
} else {
auto bitmask = 1UL << pos;
if ((mask & bitmask) == 0) {
expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
} else {
if ((valid & bitmask) == 0) {
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
} else {
auto new_val = idx << 1;
if ((value & bitmask) != 0) new_val++;
expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
}
}
}
}
inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
if (pos >= 0) {
auto bitmask = 1UL << pos;
if ((mask & bitmask) == 0) {
lut_val = extract_fields(pos - 1, val, mask, lut_val);
} else {
auto new_val = lut_val << 1;
if ((val & bitmask) != 0) new_val++;
lut_val = extract_fields(pos - 1, val, mask, new_val);
}
}
return lut_val;
}
private:
/****************************************************************************
* start opcode definitions
****************************************************************************/
struct InstructionDesriptor {
size_t length;
uint32_t value;
uint32_t mask;
compile_func op;
};
const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name} */
{${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
}};
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
/* instruction ${idx}: ${instr.name} */
std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){<%instr.code.eachLine{%>
${it}<%}%>
}
<%}%>
/****************************************************************************
* end opcode definitions
****************************************************************************/
std::tuple<continuation_e, BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
this->gen_sync(iss::PRE_SYNC, instr_descr.size());
this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
get_reg_ptr(traits<ARCH>::PC), true);
this->builder.CreateStore(
this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
this->gen_const(64U, 1)),
get_reg_ptr(traits<ARCH>::ICOUNT), true);
pc = pc + ((instr & 3) == 3 ? 4 : 2);
this->gen_raise_trap(0, 2); // illegal instruction trap
this->gen_sync(iss::POST_SYNC, instr_descr.size());
this->gen_trap_check(this->leave_blk);
return std::make_tuple(BRANCH, nullptr);
}
};
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
volatile CODE_WORD x = insn;
insn = 2 * x;
}
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
template <typename ARCH>
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
: vm_base<ARCH>(core, core_id, cluster_id) {
qlut[0] = lut_00.data();
qlut[1] = lut_01.data();
qlut[2] = lut_10.data();
qlut[3] = lut_11.data();
for (auto instr : instr_descr) {
auto quantrant = instr.value & 0x3;
expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
}
}
template <typename ARCH>
std::tuple<continuation_e, BasicBlock *>
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
// we fetch at max 4 byte, alignment is 2
enum {TRAP_ID=1<<16};
code_word_t insn = 0;
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
phys_addr_t paddr(pc);
auto *const data = (uint8_t *)&insn;
paddr = this->core.v2p(pc);
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
auto res = this->core.read(paddr, 2, data);
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
}
} else {
auto res = this->core.read(paddr, 4, data);
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
}
if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
// curr pc on stack
++inst_cnt;
auto lut_val = extract_fields(insn);
auto f = qlut[insn & 0x3][lut_val];
if (f == nullptr) {
f = &this_class::illegal_intruction;
}
return (this->*f)(pc, insn, this_block);
}
template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
this->builder.SetInsertPoint(leave_blk);
this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
}
template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
}
template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
}
template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
this->builder.CreateCall(this->mod->getFunction("wait"), args);
}
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
this->builder.SetInsertPoint(trap_blk);
auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
this->builder.CreateRet(trap_addr_val);
}
template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
this->gen_cond_branch(this->builder.CreateICmp(
ICmpInst::ICMP_EQ, v,
ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
bb, this->trap_blk, 1);
}
} // namespace ${coreDef.name.toLowerCase()}
template <>
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
} // namespace llvm
} // namespace iss

350
gen_input/templates/tcc/CORENAME.cpp.gtl
View File

@ -1,350 +0,0 @@
/*******************************************************************************
* Copyright (C) 2020-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
// clang-format off
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
#include <iss/tcc/vm_base.h>
#include <util/logging.h>
#include <sstream>
#include <iss/instruction_decoder.h>
<%def fcsr = registers.find {it.name=='FCSR'}
if(fcsr != null) {%>
#include <vm/fp_functions.h><%}%>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
#include <fmt/format.h>
#include <array>
#include <iss/debugger/riscv_target_adapter.h>
namespace iss {
namespace tcc {
namespace ${coreDef.name.toLowerCase()} {
using namespace iss::arch;
using namespace iss::debugger;
template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
public:
using traits = arch::traits<ARCH>;
using super = typename iss::tcc::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
using mem_type_e = typename traits::mem_type_e;
using addr_t = typename super::addr_t;
using tu_builder = typename super::tu_builder;
vm_impl();
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
target_adapter_if *accquire_target_adapter(server_if *srv) override {
debugger_if::dbg_enabled = true;
if (vm_base<ARCH>::tgt_adapter == nullptr)
vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
return vm_base<ARCH>::tgt_adapter;
}
protected:
using vm_base<ARCH>::get_reg_ptr;
using this_class = vm_impl<ARCH>;
using compile_ret_t = std::tuple<continuation_e>;
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
<%
if(fcsr != null) {%>
inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
void add_prologue(tu_builder& tu) override;
<%}%>
void setup_module(std::string m) override {
super::setup_module(m);
}
compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, tu_builder&) override;
void gen_trap_behavior(tu_builder& tu) override;
void gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause);
void gen_leave_trap(tu_builder& tu, unsigned lvl);
inline void gen_set_tval(tu_builder& tu, uint64_t new_tval);
inline void gen_set_tval(tu_builder& tu, value new_tval);
inline void gen_trap_check(tu_builder& tu) {
tu("if(*trap_state!=0) goto trap_entry;");
}
inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
switch(reg_num){
case traits::NEXT_PC:
tu("*next_pc = {:#x};", pc.val);
break;
case traits::PC:
tu("*pc = {:#x};", pc.val);
break;
default:
if(!tu.defined_regs[reg_num]){
tu("reg_t* reg{:02d} = (reg_t*){:#x};", reg_num, reinterpret_cast<uintptr_t>(get_reg_ptr(reg_num)));
tu.defined_regs[reg_num]=true;
}
tu("*reg{:02d} = {:#x};", reg_num, pc.val);
}
}
template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
inline S sext(U from) {
auto mask = (1ULL<<W) - 1;
auto sign_mask = 1ULL<<(W-1);
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
}
<%functions.each{ it.eachLine { %>
${it}<%}%>
<%}%>
private:
/****************************************************************************
* start opcode definitions
****************************************************************************/
struct instruction_descriptor {
uint32_t length;
uint32_t value;
uint32_t mask;
compile_func op;
};
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
}};
//needs to be declared after instr_descr
decoder instr_decoder;
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
/* instruction ${idx}: ${instr.name} */
compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
tu("${instr.name}_{:#010x}:", pc.val);
vm_base<ARCH>::gen_sync(tu, PRE_SYNC,${idx});
uint64_t PC = pc.val;
<%instr.fields.eachLine{%>${it}
<%}%>if(this->disass_enabled){
/* generate console output when executing the command */<%instr.disass.eachLine{%>
${it}<%}%>
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
}
auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
pc=pc+ ${instr.length/8};
gen_set_pc(tu, pc, traits::NEXT_PC);
tu.open_scope();
this->gen_set_tval(tu, instr);
<%instr.behavior.eachLine{%>${it}
<%}%>
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
gen_trap_check(tu);
return returnValue;
}
<%}%>
/****************************************************************************
* end opcode definitions
****************************************************************************/
compile_ret_t illegal_instruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
vm_impl::gen_sync(tu, iss::PRE_SYNC, instr_descr.size());
if(this->disass_enabled){
/* generate console output when executing the command */
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, std::string("illegal_instruction"));
}
pc = pc + ((instr & 3) == 3 ? 4 : 2);
gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
this->gen_set_tval(tu, instr);
vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
vm_impl::gen_trap_check(tu);
return ILLEGAL_INSTR;
}
};
template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
volatile CODE_WORD x = instr;
instr = 2 * x;
}
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
template <typename ARCH>
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
: vm_base<ARCH>(core, core_id, cluster_id)
, instr_decoder([this]() {
std::vector<generic_instruction_descriptor> g_instr_descr;
g_instr_descr.reserve(instr_descr.size());
for (uint32_t i = 0; i < instr_descr.size(); ++i) {
generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
g_instr_descr.push_back(new_instr_descr);
}
return std::move(g_instr_descr);
}()) {}
template <typename ARCH>
std::tuple<continuation_e>
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
// we fetch at max 4 byte, alignment is 2
enum {TRAP_ID=1<<16};
code_word_t instr = 0;
phys_addr_t paddr(pc);
if(this->core.has_mmu())
paddr = this->core.virt2phys(pc);
auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
if (res != iss::Ok)
return ILLEGAL_FETCH;
if (instr == 0x0000006f || (instr&0xffff)==0xa001)
return JUMP_TO_SELF;
++inst_cnt;
uint32_t inst_index = instr_decoder.decode_instr(instr);
compile_func f = nullptr;
if(inst_index < instr_descr.size())
f = instr_descr[inst_index].op;
if (f == nullptr) {
f = &this_class::illegal_instruction;
}
return (this->*f)(pc, instr, tu);
}
template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
tu(" *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
}
template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
tu("leave_trap(core_ptr, {});", lvl);
tu.store(traits::NEXT_PC, tu.read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN));
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP), 32));
}
template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, uint64_t new_tval) {
tu(fmt::format("tval = {};", new_tval));
}
template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, value new_tval) {
tu(fmt::format("tval = {};", new_tval.str));
}
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
tu("trap_entry:");
this->gen_sync(tu, POST_SYNC, -1);
tu("enter_trap(core_ptr, *trap_state, *pc, tval);");
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP),32));
tu("return *next_pc;");
}
<%
if(fcsr != null) {%>
template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
std::ostringstream os;
os << "uint32_t (*fget_flags)()=" << (uintptr_t)&fget_flags << ";\\n";
os << "uint32_t (*fadd_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fadd_s << ";\\n";
os << "uint32_t (*fsub_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fsub_s << ";\\n";
os << "uint32_t (*fmul_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fmul_s << ";\\n";
os << "uint32_t (*fdiv_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_s << ";\\n";
os << "uint32_t (*fsqrt_s)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_s << ";\\n";
os << "uint32_t (*fcmp_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fcmp_s << ";\\n";
os << "uint32_t (*fcvt_s)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_s << ";\\n";
os << "uint32_t (*fmadd_s)(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_s << ";\\n";
os << "uint32_t (*fsel_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fsel_s << ";\\n";
os << "uint32_t (*fclass_s)( uint32_t v1 )=" << (uintptr_t)&fclass_s << ";\\n";
os << "uint32_t (*fconv_d2f)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fconv_d2f << ";\\n";
os << "uint64_t (*fconv_f2d)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fconv_f2d << ";\\n";
os << "uint64_t (*fadd_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fadd_d << ";\\n";
os << "uint64_t (*fsub_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fsub_d << ";\\n";
os << "uint64_t (*fmul_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fmul_d << ";\\n";
os << "uint64_t (*fdiv_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_d << ";\\n";
os << "uint64_t (*fsqrt_d)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_d << ";\\n";
os << "uint64_t (*fcmp_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fcmp_d << ";\\n";
os << "uint64_t (*fcvt_d)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_d << ";\\n";
os << "uint64_t (*fmadd_d)(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_d << ";\\n";
os << "uint64_t (*fsel_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fsel_d << ";\\n";
os << "uint64_t (*fclass_d)(uint64_t v1 )=" << (uintptr_t)&fclass_d << ";\\n";
os << "uint64_t (*fcvt_32_64)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_32_64 << ";\\n";
os << "uint32_t (*fcvt_64_32)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_64_32 << ";\\n";
os << "uint32_t (*unbox_s)(uint64_t v)=" << (uintptr_t)&unbox_s << ";\\n";
tu.add_prologue(os.str());
}
<%}%>
} // namespace ${coreDef.name.toLowerCase()}
template <>
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
} // namesapce tcc
} // namespace iss
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_mu_p.h>
#include <iss/factory.h>
namespace iss {
namespace {
volatile std::array<bool, 2> dummy = {
core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};
}),
core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};
})
};
}
}
// clang-format on

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{
"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
{
"name" : "${instr.name}",
"size" : ${instr.length},
"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
}<%}%>
]
}

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/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
<%
import com.minres.coredsl.coreDsl.Register
import com.minres.coredsl.coreDsl.RegisterFile
import com.minres.coredsl.coreDsl.RegisterAlias
def getTypeSize(size){
if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
}
def getOriginalName(reg){
if( reg.original instanceof RegisterFile) {
if( reg.index != null ) {
return reg.original.name+generator.generateHostCode(reg.index)
} else {
return reg.original.name
}
} else if(reg.original instanceof Register){
return reg.original.name
}
}
def getRegisterNames(){
def regNames = []
allRegs.each { reg ->
if( reg instanceof RegisterFile) {
(reg.range.right..reg.range.left).each{
regNames+=reg.name.toLowerCase()+it
}
} else if(reg instanceof Register){
regNames+=reg.name.toLowerCase()
}
}
return regNames
}
def getRegisterAliasNames(){
def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
if( reg instanceof RegisterFile) {
return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
} else if(reg instanceof Register){
regMap[reg.name]?:reg.name.toLowerCase()
}
}.flatten()
}
%>
#ifndef _${coreDef.name.toUpperCase()}_H_
#define _${coreDef.name.toUpperCase()}_H_
#include <array>
#include <iss/arch/traits.h>
#include <iss/arch_if.h>
#include <iss/vm_if.h>
namespace iss {
namespace arch {
struct ${coreDef.name.toLowerCase()};
template <> struct traits<${coreDef.name.toLowerCase()}> {
constexpr static char const* const core_type = "${coreDef.name}";
static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
{"${getRegisterNames().join("\", \"")}"}};
static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
{"${getRegisterAliasNames().join("\", \"")}"}};
enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
enum reg_e {<%
allRegs.each { reg ->
if( reg instanceof RegisterFile) {
(reg.range.right..reg.range.left).each{%>
${reg.name}${it},<%
}
} else if(reg instanceof Register){ %>
${reg.name},<%
}
}%>
NUM_REGS,
NEXT_${pc.name}=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
LAST_BRANCH,
ICOUNT<%
allRegs.each { reg ->
if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
${reg.name} = ${aliasname}<%
}
}%>
};
using reg_t = uint${regDataWidth}_t;
using addr_t = uint${addrDataWidth}_t;
using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
{${regSizes.join(",")}}};
static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
{${regOffsets.join(",")}}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
enum sreg_flag_e { FLAGS };
enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
};
struct ${coreDef.name.toLowerCase()}: public arch_if {
using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
using reg_t = typename traits<${coreDef.name.toLowerCase()}>::reg_t;
using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
${coreDef.name.toLowerCase()}();
~${coreDef.name.toLowerCase()}();
void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override;
/// deprecated
void get_reg(short idx, std::vector<uint8_t>& value) override {}
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
bool get_flag(int flag) override {return false;}
void set_flag(int, bool value) override {};
/// deprecated
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
inline uint64_t get_icount() { return reg.icount; }
inline bool should_stop() { return interrupt_sim; }
inline uint64_t stop_code() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
} else
return virt2phys(addr);
}
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
inline uint32_t get_last_branch() { return reg.last_branch; }
protected:
struct ${coreDef.name}_regs {<%
allRegs.each { reg ->
if( reg instanceof RegisterFile) {
(reg.range.right..reg.range.left).each{%>
uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
}
} else if(reg instanceof Register){ %>
uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
}
}%>
uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0;
} reg;
std::array<address_type, 4> addr_mode;
uint64_t interrupt_sim=0;
<%
def fcsr = allRegs.find {it.name=='FCSR'}
if(fcsr != null) {%>
uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}
<%} else { %>
uint32_t get_fcsr(){return 0;}
void set_fcsr(uint32_t val){}
<%}%>
};
}
}
#endif /* _${coreDef.name.toUpperCase()}_H_ */

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/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
<%
import com.minres.coredsl.coreDsl.Register
import com.minres.coredsl.coreDsl.RegisterFile
import com.minres.coredsl.coreDsl.RegisterAlias
def getOriginalName(reg){
if( reg.original instanceof RegisterFile) {
if( reg.index != null ) {
return reg.original.name+generator.generateHostCode(reg.index)
} else {
return reg.original.name
}
} else if(reg.original instanceof Register){
return reg.original.name
}
}
def getRegisterNames(){
def regNames = []
allRegs.each { reg ->
if( reg instanceof RegisterFile) {
(reg.range.right..reg.range.left).each{
regNames+=reg.name.toLowerCase()+it
}
} else if(reg instanceof Register){
regNames+=reg.name.toLowerCase()
}
}
return regNames
}
def getRegisterAliasNames(){
def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
if( reg instanceof RegisterFile) {
return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
} else if(reg instanceof Register){
regMap[reg.name]?:reg.name.toLowerCase()
}
}.flatten()
}
%>
#include "util/ities.h"
#include <util/logging.h>
#include <elfio/elfio.hpp>
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
#ifdef __cplusplus
extern "C" {
#endif
#include <ihex.h>
#ifdef __cplusplus
}
#endif
#include <cstdio>
#include <cstring>
#include <fstream>
using namespace iss::arch;
constexpr std::array<const char*, ${getRegisterNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
constexpr std::array<const char*, ${getRegisterAliasNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
reg.icount = 0;
}
${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x3;
reg.icount=0;
}
uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
return reinterpret_cast<uint8_t*>(&reg);
}
${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
return phys_addr_t(pc); // change logical address to physical address
}

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/*******************************************************************************
* Copyright (C) 2020 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
#include <iss/tcc/vm_base.h>
#include <util/logging.h>
#include <sstream>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
#include <fmt/format.h>
#include <array>
#include <iss/debugger/riscv_target_adapter.h>
namespace iss {
namespace tcc {
namespace ${coreDef.name.toLowerCase()} {
using namespace iss::arch;
using namespace iss::debugger;
template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
public:
using super = typename iss::tcc::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
using addr_t = typename super::addr_t;
using tu_builder = typename super::tu_builder;
vm_impl();
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
target_adapter_if *accquire_target_adapter(server_if *srv) override {
debugger_if::dbg_enabled = true;
if (vm_base<ARCH>::tgt_adapter == nullptr)
vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
return vm_base<ARCH>::tgt_adapter;
}
protected:
using vm_base<ARCH>::get_reg_ptr;
using this_class = vm_impl<ARCH>;
using compile_ret_t = std::tuple<continuation_e>;
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
void setup_module(std::string m) override {
super::setup_module(m);
}
compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, tu_builder&) override;
void gen_trap_behavior(tu_builder& tu) override;
void gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause);
void gen_leave_trap(tu_builder& tu, unsigned lvl);
void gen_wait(tu_builder& tu, unsigned type);
inline void gen_trap_check(tu_builder& tu) {
tu("if(*trap_state!=0) goto trap_entry;");
}
inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
switch(reg_num){
case traits<ARCH>::NEXT_PC:
tu("*next_pc = {:#x};", pc.val);
break;
case traits<ARCH>::PC:
tu("*pc = {:#x};", pc.val);
break;
default:
if(!tu.defined_regs[reg_num]){
tu("reg_t* reg{:02d} = (reg_t*){:#x};", reg_num, reinterpret_cast<uintptr_t>(get_reg_ptr(reg_num)));
tu.defined_regs[reg_num]=true;
}
tu("*reg{:02d} = {:#x};", reg_num, pc.val);
}
}
// some compile time constants
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
std::array<compile_func, LUT_SIZE> lut;
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
std::array<compile_func, LUT_SIZE> lut_11;
std::array<compile_func *, 4> qlut;
std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
compile_func f) {
if (pos < 0) {
lut[idx] = f;
} else {
auto bitmask = 1UL << pos;
if ((mask & bitmask) == 0) {
expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
} else {
if ((valid & bitmask) == 0) {
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
} else {
auto new_val = idx << 1;
if ((value & bitmask) != 0) new_val++;
expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
}
}
}
}
inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
if (pos >= 0) {
auto bitmask = 1UL << pos;
if ((mask & bitmask) == 0) {
lut_val = extract_fields(pos - 1, val, mask, lut_val);
} else {
auto new_val = lut_val << 1;
if ((val & bitmask) != 0) new_val++;
lut_val = extract_fields(pos - 1, val, mask, new_val);
}
}
return lut_val;
}
private:
/****************************************************************************
* start opcode definitions
****************************************************************************/
struct InstructionDesriptor {
size_t length;
uint32_t value;
uint32_t mask;
compile_func op;
};
const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name} */
{${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
}};
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
/* instruction ${idx}: ${instr.name} */
compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){<%instr.code.eachLine{%>
${it}<%}%>
}
<%}%>
/****************************************************************************
* end opcode definitions
****************************************************************************/
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
vm_impl::gen_sync(tu, iss::PRE_SYNC, instr_descr.size());
pc = pc + ((instr & 3) == 3 ? 4 : 2);
gen_raise_trap(tu, 0, 2); // illegal instruction trap
vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
vm_impl::gen_trap_check(tu);
return BRANCH;
}
};
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
volatile CODE_WORD x = insn;
insn = 2 * x;
}
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
template <typename ARCH>
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
: vm_base<ARCH>(core, core_id, cluster_id) {
qlut[0] = lut_00.data();
qlut[1] = lut_01.data();
qlut[2] = lut_10.data();
qlut[3] = lut_11.data();
for (auto instr : instr_descr) {
auto quantrant = instr.value & 0x3;
expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
}
}
template <typename ARCH>
std::tuple<continuation_e>
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
// we fetch at max 4 byte, alignment is 2
enum {TRAP_ID=1<<16};
code_word_t insn = 0;
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
phys_addr_t paddr(pc);
auto *const data = (uint8_t *)&insn;
paddr = this->core.v2p(pc);
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
auto res = this->core.read(paddr, 2, data);
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
}
} else {
auto res = this->core.read(paddr, 4, data);
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
}
if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
// curr pc on stack
++inst_cnt;
auto lut_val = extract_fields(insn);
auto f = qlut[insn & 0x3][lut_val];
if (f == nullptr) {
f = &this_class::illegal_intruction;
}
return (this->*f)(pc, insn, tu);
}
template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
tu(" *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
}
template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
tu("leave_trap(core_ptr, {});", lvl);
tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
}
template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
}
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
tu("trap_entry:");
tu("enter_trap(core_ptr, *trap_state, *pc);");
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
tu("return *next_pc;");
}
} // namespace mnrv32
template <>
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
}
} // namespace iss

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/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#ifndef _MNRV32_H_
#define _MNRV32_H_
#include <array>
#include <iss/arch/traits.h>
#include <iss/arch_if.h>
#include <iss/vm_if.h>
namespace iss {
namespace arch {
struct mnrv32;
template <> struct traits<mnrv32> {
constexpr static char const* const core_type = "MNRV32";
static constexpr std::array<const char*, 33> reg_names{
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
static constexpr std::array<const char*, 33> reg_aliases{
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000101000001000100000101, PGSIZE=0x1000, PGMASK=0xfff};
constexpr static unsigned FP_REGS_SIZE = 0;
enum reg_e {
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31,
PC,
NUM_REGS,
NEXT_PC=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
LAST_BRANCH,
ICOUNT,
ZERO = X0,
RA = X1,
SP = X2,
GP = X3,
TP = X4,
T0 = X5,
T1 = X6,
T2 = X7,
S0 = X8,
S1 = X9,
A0 = X10,
A1 = X11,
A2 = X12,
A3 = X13,
A4 = X14,
A5 = X15,
A6 = X16,
A7 = X17,
S2 = X18,
S3 = X19,
S4 = X20,
S5 = X21,
S6 = X22,
S7 = X23,
S8 = X24,
S9 = X25,
S10 = X26,
S11 = X27,
T3 = X28,
T4 = X29,
T5 = X30,
T6 = X31
};
using reg_t = uint32_t;
using addr_t = uint32_t;
using code_word_t = uint32_t; //TODO: check removal
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, 39> reg_bit_widths{
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
enum sreg_flag_e { FLAGS };
enum mem_type_e { MEM, CSR, FENCE, RES };
};
struct mnrv32: public arch_if {
using virt_addr_t = typename traits<mnrv32>::virt_addr_t;
using phys_addr_t = typename traits<mnrv32>::phys_addr_t;
using reg_t = typename traits<mnrv32>::reg_t;
using addr_t = typename traits<mnrv32>::addr_t;
mnrv32();
~mnrv32();
void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override;
/// deprecated
void get_reg(short idx, std::vector<uint8_t>& value) override {}
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
bool get_flag(int flag) override {return false;}
void set_flag(int, bool value) override {};
/// deprecated
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
inline uint64_t get_icount() { return reg.icount; }
inline bool should_stop() { return interrupt_sim; }
inline uint64_t stop_code() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<mnrv32>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<mnrv32>::addr_mask);
} else
return virt2phys(addr);
}
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
inline uint32_t get_last_branch() { return reg.last_branch; }
protected:
struct MNRV32_regs {
uint32_t X0 = 0;
uint32_t X1 = 0;
uint32_t X2 = 0;
uint32_t X3 = 0;
uint32_t X4 = 0;
uint32_t X5 = 0;
uint32_t X6 = 0;
uint32_t X7 = 0;
uint32_t X8 = 0;
uint32_t X9 = 0;
uint32_t X10 = 0;
uint32_t X11 = 0;
uint32_t X12 = 0;
uint32_t X13 = 0;
uint32_t X14 = 0;
uint32_t X15 = 0;
uint32_t X16 = 0;
uint32_t X17 = 0;
uint32_t X18 = 0;
uint32_t X19 = 0;
uint32_t X20 = 0;
uint32_t X21 = 0;
uint32_t X22 = 0;
uint32_t X23 = 0;
uint32_t X24 = 0;
uint32_t X25 = 0;
uint32_t X26 = 0;
uint32_t X27 = 0;
uint32_t X28 = 0;
uint32_t X29 = 0;
uint32_t X30 = 0;
uint32_t X31 = 0;
uint32_t PC = 0;
uint32_t NEXT_PC = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0;
} reg;
std::array<address_type, 4> addr_mode;
uint64_t interrupt_sim=0;
uint32_t get_fcsr(){return 0;}
void set_fcsr(uint32_t val){}
};
}
}
#endif /* _MNRV32_H_ */

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/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#ifndef _RV32GC_H_
#define _RV32GC_H_
#include <array>
#include <iss/arch/traits.h>
#include <iss/arch_if.h>
#include <iss/vm_if.h>
namespace iss {
namespace arch {
struct rv32gc;
template <> struct traits<rv32gc> {
constexpr static char const* const core_type = "RV32GC";
static constexpr std::array<const char*, 66> reg_names{
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr"}};
static constexpr std::array<const char*, 66> reg_aliases{
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr"}};
enum constants {XLEN=32, FLEN=64, PCLEN=32, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff};
constexpr static unsigned FP_REGS_SIZE = 64;
enum reg_e {
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31,
PC,
F0,
F1,
F2,
F3,
F4,
F5,
F6,
F7,
F8,
F9,
F10,
F11,
F12,
F13,
F14,
F15,
F16,
F17,
F18,
F19,
F20,
F21,
F22,
F23,
F24,
F25,
F26,
F27,
F28,
F29,
F30,
F31,
FCSR,
NUM_REGS,
NEXT_PC=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
LAST_BRANCH,
ICOUNT,
ZERO = X0,
RA = X1,
SP = X2,
GP = X3,
TP = X4,
T0 = X5,
T1 = X6,
T2 = X7,
S0 = X8,
S1 = X9,
A0 = X10,
A1 = X11,
A2 = X12,
A3 = X13,
A4 = X14,
A5 = X15,
A6 = X16,
A7 = X17,
S2 = X18,
S3 = X19,
S4 = X20,
S5 = X21,
S6 = X22,
S7 = X23,
S8 = X24,
S9 = X25,
S10 = X26,
S11 = X27,
T3 = X28,
T4 = X29,
T5 = X30,
T6 = X31
};
using reg_t = uint32_t;
using addr_t = uint32_t;
using code_word_t = uint32_t; //TODO: check removal
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, 72> reg_bit_widths{
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,32,32,32,64}};
static constexpr std::array<const uint32_t, 73> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,280,288,296,304,312,320,328,336,344,352,360,368,376,384,392,396,400,404,408,412,416,424}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
enum sreg_flag_e { FLAGS };
enum mem_type_e { MEM, CSR, FENCE, RES };
};
struct rv32gc: public arch_if {
using virt_addr_t = typename traits<rv32gc>::virt_addr_t;
using phys_addr_t = typename traits<rv32gc>::phys_addr_t;
using reg_t = typename traits<rv32gc>::reg_t;
using addr_t = typename traits<rv32gc>::addr_t;
rv32gc();
~rv32gc();
void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override;
/// deprecated
void get_reg(short idx, std::vector<uint8_t>& value) override {}
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
bool get_flag(int flag) override {return false;}
void set_flag(int, bool value) override {};
/// deprecated
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
inline uint64_t get_icount() { return reg.icount; }
inline bool should_stop() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<rv32gc>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<rv32gc>::addr_mask);
} else
return virt2phys(addr);
}
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
inline uint32_t get_last_branch() { return reg.last_branch; }
protected:
struct RV32GC_regs {
uint32_t X0 = 0;
uint32_t X1 = 0;
uint32_t X2 = 0;
uint32_t X3 = 0;
uint32_t X4 = 0;
uint32_t X5 = 0;
uint32_t X6 = 0;
uint32_t X7 = 0;
uint32_t X8 = 0;
uint32_t X9 = 0;
uint32_t X10 = 0;
uint32_t X11 = 0;
uint32_t X12 = 0;
uint32_t X13 = 0;
uint32_t X14 = 0;
uint32_t X15 = 0;
uint32_t X16 = 0;
uint32_t X17 = 0;
uint32_t X18 = 0;
uint32_t X19 = 0;
uint32_t X20 = 0;
uint32_t X21 = 0;
uint32_t X22 = 0;
uint32_t X23 = 0;
uint32_t X24 = 0;
uint32_t X25 = 0;
uint32_t X26 = 0;
uint32_t X27 = 0;
uint32_t X28 = 0;
uint32_t X29 = 0;
uint32_t X30 = 0;
uint32_t X31 = 0;
uint32_t PC = 0;
uint64_t F0 = 0;
uint64_t F1 = 0;
uint64_t F2 = 0;
uint64_t F3 = 0;
uint64_t F4 = 0;
uint64_t F5 = 0;
uint64_t F6 = 0;
uint64_t F7 = 0;
uint64_t F8 = 0;
uint64_t F9 = 0;
uint64_t F10 = 0;
uint64_t F11 = 0;
uint64_t F12 = 0;
uint64_t F13 = 0;
uint64_t F14 = 0;
uint64_t F15 = 0;
uint64_t F16 = 0;
uint64_t F17 = 0;
uint64_t F18 = 0;
uint64_t F19 = 0;
uint64_t F20 = 0;
uint64_t F21 = 0;
uint64_t F22 = 0;
uint64_t F23 = 0;
uint64_t F24 = 0;
uint64_t F25 = 0;
uint64_t F26 = 0;
uint64_t F27 = 0;
uint64_t F28 = 0;
uint64_t F29 = 0;
uint64_t F30 = 0;
uint64_t F31 = 0;
uint32_t FCSR = 0;
uint32_t NEXT_PC = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0;
} reg;
std::array<address_type, 4> addr_mode;
bool interrupt_sim=false;
uint32_t get_fcsr(){return reg.FCSR;}
void set_fcsr(uint32_t val){reg.FCSR = val;}
};
}
}
#endif /* _RV32GC_H_ */

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/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#ifndef _RV32IMAC_H_
#define _RV32IMAC_H_
#include <array>
#include <iss/arch/traits.h>
#include <iss/arch_if.h>
#include <iss/vm_if.h>
namespace iss {
namespace arch {
struct rv32imac;
template <> struct traits<rv32imac> {
constexpr static char const* const core_type = "RV32IMAC";
static constexpr std::array<const char*, 33> reg_names{
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
static constexpr std::array<const char*, 33> reg_aliases{
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000101000001000100000101, PGSIZE=0x1000, PGMASK=0xfff};
constexpr static unsigned FP_REGS_SIZE = 0;
enum reg_e {
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31,
PC,
NUM_REGS,
NEXT_PC=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
LAST_BRANCH,
ICOUNT,
ZERO = X0,
RA = X1,
SP = X2,
GP = X3,
TP = X4,
T0 = X5,
T1 = X6,
T2 = X7,
S0 = X8,
S1 = X9,
A0 = X10,
A1 = X11,
A2 = X12,
A3 = X13,
A4 = X14,
A5 = X15,
A6 = X16,
A7 = X17,
S2 = X18,
S3 = X19,
S4 = X20,
S5 = X21,
S6 = X22,
S7 = X23,
S8 = X24,
S9 = X25,
S10 = X26,
S11 = X27,
T3 = X28,
T4 = X29,
T5 = X30,
T6 = X31
};
using reg_t = uint32_t;
using addr_t = uint32_t;
using code_word_t = uint32_t; //TODO: check removal
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, 39> reg_bit_widths{
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
enum sreg_flag_e { FLAGS };
enum mem_type_e { MEM, CSR, FENCE, RES };
};
struct rv32imac: public arch_if {
using virt_addr_t = typename traits<rv32imac>::virt_addr_t;
using phys_addr_t = typename traits<rv32imac>::phys_addr_t;
using reg_t = typename traits<rv32imac>::reg_t;
using addr_t = typename traits<rv32imac>::addr_t;
rv32imac();
~rv32imac();
void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override;
/// deprecated
void get_reg(short idx, std::vector<uint8_t>& value) override {}
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
bool get_flag(int flag) override {return false;}
void set_flag(int, bool value) override {};
/// deprecated
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
inline uint64_t get_icount() { return reg.icount; }
inline bool should_stop() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<rv32imac>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<rv32imac>::addr_mask);
} else
return virt2phys(addr);
}
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
inline uint32_t get_last_branch() { return reg.last_branch; }
protected:
struct RV32IMAC_regs {
uint32_t X0 = 0;
uint32_t X1 = 0;
uint32_t X2 = 0;
uint32_t X3 = 0;
uint32_t X4 = 0;
uint32_t X5 = 0;
uint32_t X6 = 0;
uint32_t X7 = 0;
uint32_t X8 = 0;
uint32_t X9 = 0;
uint32_t X10 = 0;
uint32_t X11 = 0;
uint32_t X12 = 0;
uint32_t X13 = 0;
uint32_t X14 = 0;
uint32_t X15 = 0;
uint32_t X16 = 0;
uint32_t X17 = 0;
uint32_t X18 = 0;
uint32_t X19 = 0;
uint32_t X20 = 0;
uint32_t X21 = 0;
uint32_t X22 = 0;
uint32_t X23 = 0;
uint32_t X24 = 0;
uint32_t X25 = 0;
uint32_t X26 = 0;
uint32_t X27 = 0;
uint32_t X28 = 0;
uint32_t X29 = 0;
uint32_t X30 = 0;
uint32_t X31 = 0;
uint32_t PC = 0;
uint32_t NEXT_PC = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0;
} reg;
std::array<address_type, 4> addr_mode;
bool interrupt_sim=false;
uint32_t get_fcsr(){return 0;}
void set_fcsr(uint32_t val){}
};
}
}
#endif /* _RV32IMAC_H_ */

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/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#ifndef _RV64GC_H_
#define _RV64GC_H_
#include <array>
#include <iss/arch/traits.h>
#include <iss/arch_if.h>
#include <iss/vm_if.h>
namespace iss {
namespace arch {
struct rv64gc;
template <> struct traits<rv64gc> {
constexpr static char const* const core_type = "RV64GC";
static constexpr std::array<const char*, 66> reg_names{
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr"}};
static constexpr std::array<const char*, 66> reg_aliases{
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr"}};
enum constants {XLEN=64, FLEN=64, PCLEN=64, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff};
constexpr static unsigned FP_REGS_SIZE = 64;
enum reg_e {
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31,
PC,
F0,
F1,
F2,
F3,
F4,
F5,
F6,
F7,
F8,
F9,
F10,
F11,
F12,
F13,
F14,
F15,
F16,
F17,
F18,
F19,
F20,
F21,
F22,
F23,
F24,
F25,
F26,
F27,
F28,
F29,
F30,
F31,
FCSR,
NUM_REGS,
NEXT_PC=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
LAST_BRANCH,
ICOUNT,
ZERO = X0,
RA = X1,
SP = X2,
GP = X3,
TP = X4,
T0 = X5,
T1 = X6,
T2 = X7,
S0 = X8,
S1 = X9,
A0 = X10,
A1 = X11,
A2 = X12,
A3 = X13,
A4 = X14,
A5 = X15,
A6 = X16,
A7 = X17,
S2 = X18,
S3 = X19,
S4 = X20,
S5 = X21,
S6 = X22,
S7 = X23,
S8 = X24,
S9 = X25,
S10 = X26,
S11 = X27,
T3 = X28,
T4 = X29,
T5 = X30,
T6 = X31
};
using reg_t = uint64_t;
using addr_t = uint64_t;
using code_word_t = uint64_t; //TODO: check removal
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, 72> reg_bit_widths{
{64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,64,32,32,32,32,64}};
static constexpr std::array<const uint32_t, 73> reg_byte_offsets{
{0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,280,288,296,304,312,320,328,336,344,352,360,368,376,384,392,400,408,416,424,432,440,448,456,464,472,480,488,496,504,512,520,528,536,540,544,548,552,560}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
enum sreg_flag_e { FLAGS };
enum mem_type_e { MEM, CSR, FENCE, RES };
};
struct rv64gc: public arch_if {
using virt_addr_t = typename traits<rv64gc>::virt_addr_t;
using phys_addr_t = typename traits<rv64gc>::phys_addr_t;
using reg_t = typename traits<rv64gc>::reg_t;
using addr_t = typename traits<rv64gc>::addr_t;
rv64gc();
~rv64gc();
void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override;
/// deprecated
void get_reg(short idx, std::vector<uint8_t>& value) override {}
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
bool get_flag(int flag) override {return false;}
void set_flag(int, bool value) override {};
/// deprecated
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
inline uint64_t get_icount() { return reg.icount; }
inline bool should_stop() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<rv64gc>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<rv64gc>::addr_mask);
} else
return virt2phys(addr);
}
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
inline uint32_t get_last_branch() { return reg.last_branch; }
protected:
struct RV64GC_regs {
uint64_t X0 = 0;
uint64_t X1 = 0;
uint64_t X2 = 0;
uint64_t X3 = 0;
uint64_t X4 = 0;
uint64_t X5 = 0;
uint64_t X6 = 0;
uint64_t X7 = 0;
uint64_t X8 = 0;
uint64_t X9 = 0;
uint64_t X10 = 0;
uint64_t X11 = 0;
uint64_t X12 = 0;
uint64_t X13 = 0;
uint64_t X14 = 0;
uint64_t X15 = 0;
uint64_t X16 = 0;
uint64_t X17 = 0;
uint64_t X18 = 0;
uint64_t X19 = 0;
uint64_t X20 = 0;
uint64_t X21 = 0;
uint64_t X22 = 0;
uint64_t X23 = 0;
uint64_t X24 = 0;
uint64_t X25 = 0;
uint64_t X26 = 0;
uint64_t X27 = 0;
uint64_t X28 = 0;
uint64_t X29 = 0;
uint64_t X30 = 0;
uint64_t X31 = 0;
uint64_t PC = 0;
uint64_t F0 = 0;
uint64_t F1 = 0;
uint64_t F2 = 0;
uint64_t F3 = 0;
uint64_t F4 = 0;
uint64_t F5 = 0;
uint64_t F6 = 0;
uint64_t F7 = 0;
uint64_t F8 = 0;
uint64_t F9 = 0;
uint64_t F10 = 0;
uint64_t F11 = 0;
uint64_t F12 = 0;
uint64_t F13 = 0;
uint64_t F14 = 0;
uint64_t F15 = 0;
uint64_t F16 = 0;
uint64_t F17 = 0;
uint64_t F18 = 0;
uint64_t F19 = 0;
uint64_t F20 = 0;
uint64_t F21 = 0;
uint64_t F22 = 0;
uint64_t F23 = 0;
uint64_t F24 = 0;
uint64_t F25 = 0;
uint64_t F26 = 0;
uint64_t F27 = 0;
uint64_t F28 = 0;
uint64_t F29 = 0;
uint64_t F30 = 0;
uint64_t F31 = 0;
uint32_t FCSR = 0;
uint64_t NEXT_PC = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0;
} reg;
std::array<address_type, 4> addr_mode;
bool interrupt_sim=false;
uint32_t get_fcsr(){return reg.FCSR;}
void set_fcsr(uint32_t val){reg.FCSR = val;}
};
}
}
#endif /* _RV64GC_H_ */

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/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#ifndef _RV64I_H_
#define _RV64I_H_
#include <array>
#include <iss/arch/traits.h>
#include <iss/arch_if.h>
#include <iss/vm_if.h>
namespace iss {
namespace arch {
struct rv64i;
template <> struct traits<rv64i> {
constexpr static char const* const core_type = "RV64I";
static constexpr std::array<const char*, 33> reg_names{
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
static constexpr std::array<const char*, 33> reg_aliases{
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
enum constants {XLEN=64, PCLEN=64, MISA_VAL=0b10000000000001000000000100000000, PGSIZE=0x1000, PGMASK=0xfff};
constexpr static unsigned FP_REGS_SIZE = 0;
enum reg_e {
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31,
PC,
NUM_REGS,
NEXT_PC=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
LAST_BRANCH,
ICOUNT,
ZERO = X0,
RA = X1,
SP = X2,
GP = X3,
TP = X4,
T0 = X5,
T1 = X6,
T2 = X7,
S0 = X8,
S1 = X9,
A0 = X10,
A1 = X11,
A2 = X12,
A3 = X13,
A4 = X14,
A5 = X15,
A6 = X16,
A7 = X17,
S2 = X18,
S3 = X19,
S4 = X20,
S5 = X21,
S6 = X22,
S7 = X23,
S8 = X24,
S9 = X25,
S10 = X26,
S11 = X27,
T3 = X28,
T4 = X29,
T5 = X30,
T6 = X31
};
using reg_t = uint64_t;
using addr_t = uint64_t;
using code_word_t = uint64_t; //TODO: check removal
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, 39> reg_bit_widths{
{64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,32,64}};
static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
{0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,284,288,296}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
enum sreg_flag_e { FLAGS };
enum mem_type_e { MEM, CSR, FENCE, RES };
};
struct rv64i: public arch_if {
using virt_addr_t = typename traits<rv64i>::virt_addr_t;
using phys_addr_t = typename traits<rv64i>::phys_addr_t;
using reg_t = typename traits<rv64i>::reg_t;
using addr_t = typename traits<rv64i>::addr_t;
rv64i();
~rv64i();
void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override;
/// deprecated
void get_reg(short idx, std::vector<uint8_t>& value) override {}
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
bool get_flag(int flag) override {return false;}
void set_flag(int, bool value) override {};
/// deprecated
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
inline uint64_t get_icount() { return reg.icount; }
inline bool should_stop() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<rv64i>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<rv64i>::addr_mask);
} else
return virt2phys(addr);
}
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
inline uint32_t get_last_branch() { return reg.last_branch; }
protected:
struct RV64I_regs {
uint64_t X0 = 0;
uint64_t X1 = 0;
uint64_t X2 = 0;
uint64_t X3 = 0;
uint64_t X4 = 0;
uint64_t X5 = 0;
uint64_t X6 = 0;
uint64_t X7 = 0;
uint64_t X8 = 0;
uint64_t X9 = 0;
uint64_t X10 = 0;
uint64_t X11 = 0;
uint64_t X12 = 0;
uint64_t X13 = 0;
uint64_t X14 = 0;
uint64_t X15 = 0;
uint64_t X16 = 0;
uint64_t X17 = 0;
uint64_t X18 = 0;
uint64_t X19 = 0;
uint64_t X20 = 0;
uint64_t X21 = 0;
uint64_t X22 = 0;
uint64_t X23 = 0;
uint64_t X24 = 0;
uint64_t X25 = 0;
uint64_t X26 = 0;
uint64_t X27 = 0;
uint64_t X28 = 0;
uint64_t X29 = 0;
uint64_t X30 = 0;
uint64_t X31 = 0;
uint64_t PC = 0;
uint64_t NEXT_PC = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0;
} reg;
std::array<address_type, 4> addr_mode;
bool interrupt_sim=false;
uint32_t get_fcsr(){return 0;}
void set_fcsr(uint32_t val){}
};
}
}
#endif /* _RV64I_H_ */

450
incl/iss/debugger/riscv_target_adapter.h Normal file
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@ -0,0 +1,450 @@
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#ifndef _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
#define _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
#include "iss/arch_if.h"
#include <iss/arch/traits.h>
#include <iss/debugger/target_adapter_base.h>
#include <iss/iss.h>
#include <array>
#include <memory>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
#include <fmt/format.h>
#include <util/logging.h>
namespace iss {
namespace debugger {
using namespace iss::arch;
using namespace iss::debugger;
template <typename ARCH> class riscv_target_adapter : public target_adapter_base {
public:
riscv_target_adapter(server_if *srv, iss::arch_if *core)
: target_adapter_base(srv)
, core(core) {}
/*============== Thread Control ===============================*/
/* Set generic thread */
status set_gen_thread(rp_thread_ref &thread) override;
/* Set control thread */
status set_ctrl_thread(rp_thread_ref &thread) override;
/* Get thread status */
status is_thread_alive(rp_thread_ref &thread, bool &alive) override;
/*============= Register Access ================================*/
/* Read all registers. buf is 4-byte aligned and it is in
target byte order. If register is not available
corresponding bytes in avail_buf are 0, otherwise
avail buf is 1 */
status read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) override;
/* Write all registers. buf is 4-byte aligned and it is in target
byte order */
status write_registers(const std::vector<uint8_t> &data) override;
/* Read one register. buf is 4-byte aligned and it is in
target byte order. If register is not available
corresponding bytes in avail_buf are 0, otherwise
avail buf is 1 */
status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
std::vector<uint8_t> &avail_buf) override;
/* Write one register. buf is 4-byte aligned and it is in target byte
order */
status write_single_register(unsigned int reg_no, const std::vector<uint8_t> &buf) override;
/*=================== Memory Access =====================*/
/* Read memory, buf is 4-bytes aligned and it is in target
byte order */
status read_mem(uint64_t addr, std::vector<uint8_t> &buf) override;
/* Write memory, buf is 4-bytes aligned and it is in target
byte order */
status write_mem(uint64_t addr, const std::vector<uint8_t> &buf) override;
status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
size_t &num, bool &done) override;
status current_thread_query(rp_thread_ref &thread) override;
status offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) override;
status crc_query(uint64_t addr, size_t len, uint32_t &val) override;
status raw_query(std::string in_buf, std::string &out_buf) override;
status threadinfo_query(int first, std::string &out_buf) override;
status threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) override;
status packetsize_query(std::string &out_buf) override;
status add_break(int type, uint64_t addr, unsigned int length) override;
status remove_break(int type, uint64_t addr, unsigned int length) override;
status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
std::function<void(unsigned)> stop_callback) override;
status target_xml_query(std::string &out_buf) override;
protected:
static inline constexpr addr_t map_addr(const addr_t &i) { return i; }
iss::arch_if *core;
rp_thread_ref thread_idx;
};
template <typename ARCH> status riscv_target_adapter<ARCH>::set_gen_thread(rp_thread_ref &thread) {
thread_idx = thread;
return Ok;
}
template <typename ARCH> status riscv_target_adapter<ARCH>::set_ctrl_thread(rp_thread_ref &thread) {
thread_idx = thread;
return Ok;
}
template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_thread_ref &thread, bool &alive) {
alive = 1;
return Ok;
}
/* List threads. If first is non-zero then start from the first thread,
* otherwise start from arg, result points to array of threads to be
* filled out, result size is number of elements in the result,
* num points to the actual number of threads found, done is
* set if all threads are processed.
*/
template <typename ARCH>
status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
bool &done) {
if (first == 0) {
result.clear();
result.push_back(thread_idx);
num = 1;
done = true;
return Ok;
} else
return NotSupported;
}
template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query(rp_thread_ref &thread) {
thread = thread_idx;
return Ok;
}
template <typename ARCH>
status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) {
LOG(TRACE) << "reading target registers";
// return idx<0?:;
data.clear();
avail.clear();
const uint8_t *reg_base = core->get_regs_base_ptr();
for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) {
auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
for (size_t j = 0; j < reg_width; ++j) {
data.push_back(*(reg_base + offset + j));
avail.push_back(0xff);
}
// if(arch::traits<ARCH>::XLEN < 64)
// for(unsigned j=0; j<4; ++j){
// data.push_back(0);
// avail.push_back(0xff);
// }
}
// work around fill with F type registers
if (arch::traits<ARCH>::NUM_REGS < 65) {
auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
for (size_t j = 0; j < reg_width; ++j) {
data.push_back(0x0);
avail.push_back(0x00);
}
// if(arch::traits<ARCH>::XLEN < 64)
// for(unsigned j=0; j<4; ++j){
// data.push_back(0x0);
// avail.push_back(0x00);
// }
}
}
return Ok;
}
template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(const std::vector<uint8_t> &data) {
auto reg_count = arch::traits<ARCH>::NUM_REGS;
auto *reg_base = core->get_regs_base_ptr();
auto iter = data.data();
for (size_t reg_no = 0; reg_no < reg_count; ++reg_no) {
auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
std::copy(iter, iter + reg_width, reg_base);
iter += 4;
reg_base += offset;
}
return Ok;
}
template <typename ARCH>
status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
std::vector<uint8_t> &avail) {
if (reg_no < 65) {
// auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
// arch::traits<ARCH>::reg_e>(reg_no))/8;
auto *reg_base = core->get_regs_base_ptr();
auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
data.resize(reg_width);
avail.resize(reg_width);
auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
std::copy(reg_base + offset, reg_base + offset + reg_width, data.begin());
std::fill(avail.begin(), avail.end(), 0xff);
} else {
typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, reg_no - 65);
data.resize(sizeof(typename traits<ARCH>::reg_t));
avail.resize(sizeof(typename traits<ARCH>::reg_t));
std::fill(avail.begin(), avail.end(), 0xff);
core->read(a, data.size(), data.data());
}
return data.size() > 0 ? Ok : Err;
}
template <typename ARCH>
status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t> &data) {
if (reg_no < 65) {
auto *reg_base = core->get_regs_base_ptr();
auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
std::copy(data.begin(), data.begin() + reg_width, reg_base + offset);
} else {
typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_WRITE, traits<ARCH>::CSR, reg_no - 65);
core->write(a, data.size(), data.data());
}
return Ok;
}
template <typename ARCH> status riscv_target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t> &data) {
auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
auto f = [&]() -> status { return core->read(a, data.size(), data.data()); };
return srv->execute_syncronized(f);
}
template <typename ARCH> status riscv_target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t> &data) {
auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
auto f = [&]() -> status { return core->write(a, data.size(), data.data()); };
return srv->execute_syncronized(f);
}
template <typename ARCH>
status riscv_target_adapter<ARCH>::process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) {
return NotSupported;
}
template <typename ARCH>
status riscv_target_adapter<ARCH>::offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) {
text = 0;
data = 0;
bss = 0;
return Ok;
}
template <typename ARCH> status riscv_target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t &val) {
return NotSupported;
}
template <typename ARCH> status riscv_target_adapter<ARCH>::raw_query(std::string in_buf, std::string &out_buf) {
return NotSupported;
}
template <typename ARCH> status riscv_target_adapter<ARCH>::threadinfo_query(int first, std::string &out_buf) {
if (first) {
out_buf = fmt::format("m{:x}", thread_idx.val);
} else {
out_buf = "l";
}
return Ok;
}
template <typename ARCH>
status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) {
std::array<char, 20> buf;
memset(buf.data(), 0, 20);
sprintf(buf.data(), "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
out_buf = buf.data();
return Ok;
}
template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std::string &out_buf) {
out_buf = "PacketSize=1000";
return Ok;
}
template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
<< saddr.val << std::dec;
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
return Ok;
}
template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
if (handle) {
LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
<< std::dec;
// TODO: check length of addr range
target_adapter_base::bp_lut.removeEntry(handle);
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
return Ok;
}
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
return Err;
}
template <typename ARCH>
status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
std::function<void(unsigned)> stop_callback) {
auto *reg_base = core->get_regs_base_ptr();
auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
const uint8_t *iter = reinterpret_cast<const uint8_t *>(&addr);
std::copy(iter, iter + reg_width, reg_base);
return resume_from_current(step, sig, thread, stop_callback);
}
template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string &out_buf) {
const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
"<target><architecture>riscv:rv32</architecture>"
//" <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
//" <reg name=\"x0\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x1\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x2\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x3\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x4\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x5\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x6\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x7\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x8\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x9\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
//" </feature>\n"
"</target>"};
out_buf = res;
return Ok;
}
/*
*
<?xml version="1.0"?>
<!DOCTYPE target SYSTEM "gdb-target.dtd">
<target>
<architecture>riscv:rv32</architecture>
<feature name="org.gnu.gdb.riscv.rv32i">
<reg name="x0" bitsize="32" group="general"/>
<reg name="x1" bitsize="32" group="general"/>
<reg name="x2" bitsize="32" group="general"/>
<reg name="x3" bitsize="32" group="general"/>
<reg name="x4" bitsize="32" group="general"/>
<reg name="x5" bitsize="32" group="general"/>
<reg name="x6" bitsize="32" group="general"/>
<reg name="x7" bitsize="32" group="general"/>
<reg name="x8" bitsize="32" group="general"/>
<reg name="x9" bitsize="32" group="general"/>
<reg name="x10" bitsize="32" group="general"/>
<reg name="x11" bitsize="32" group="general"/>
<reg name="x12" bitsize="32" group="general"/>
<reg name="x13" bitsize="32" group="general"/>
<reg name="x14" bitsize="32" group="general"/>
<reg name="x15" bitsize="32" group="general"/>
<reg name="x16" bitsize="32" group="general"/>
<reg name="x17" bitsize="32" group="general"/>
<reg name="x18" bitsize="32" group="general"/>
<reg name="x19" bitsize="32" group="general"/>
<reg name="x20" bitsize="32" group="general"/>
<reg name="x21" bitsize="32" group="general"/>
<reg name="x22" bitsize="32" group="general"/>
<reg name="x23" bitsize="32" group="general"/>
<reg name="x24" bitsize="32" group="general"/>
<reg name="x25" bitsize="32" group="general"/>
<reg name="x26" bitsize="32" group="general"/>
<reg name="x27" bitsize="32" group="general"/>
<reg name="x28" bitsize="32" group="general"/>
<reg name="x29" bitsize="32" group="general"/>
<reg name="x30" bitsize="32" group="general"/>
<reg name="x31" bitsize="32" group="general"/>
</feature>
</target>
*/
}
}
#endif /* _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */

51
src/iss/plugin/cycle_estimate.h → incl/iss/plugin/cycle_estimate.h
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@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017 - 2023, MINRES Technologies GmbH
* Copyright (C) 2017, 2018, MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -37,61 +37,60 @@
#include "iss/instrumentation_if.h"
#include "iss/vm_plugin.h"
#include <functional>
#include <json/json.h>
#include <string>
#include <unordered_map>
#include <vector>
namespace iss {
namespace plugin {
class cycle_estimate : public vm_plugin {
struct instr_desc {
size_t size{0};
bool is_branch{false};
unsigned not_taken{1};
unsigned taken{1};
std::function<unsigned(uint64_t)> f;
};
class cycle_estimate: public iss::vm_plugin {
BEGIN_BF_DECL(instr_desc, uint32_t)
BF_FIELD(taken, 24, 8)
BF_FIELD(not_taken, 16, 8)
BF_FIELD(size, 0, 16)
instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken): instr_desc() {
this->size=size;
this->taken=taken;
this->not_taken=not_taken;
}
END_BF_DECL();
public:
cycle_estimate() = delete;
cycle_estimate(const cycle_estimate&) = delete;
cycle_estimate(const cycle_estimate &) = delete;
cycle_estimate(const cycle_estimate&&) = delete;
cycle_estimate(const cycle_estimate &&) = delete;
cycle_estimate(std::string const& config_file_name);
cycle_estimate(std::string config_file_name);
virtual ~cycle_estimate();
cycle_estimate& operator=(const cycle_estimate&) = delete;
cycle_estimate &operator=(const cycle_estimate &) = delete;
cycle_estimate& operator=(const cycle_estimate&&) = delete;
cycle_estimate &operator=(const cycle_estimate &&) = delete;
bool registration(const char* const version, vm_if& arch) override;
bool registration(const char *const version, vm_if &arch) override;
sync_type get_sync() override { return ALL_SYNC; };
sync_type get_sync() override { return POST_SYNC; };
void callback(instr_info_t instr_info) override;
private:
iss::instrumentation_if* instr_if{nullptr};
uint32_t* reg_base_ptr{nullptr};
instr_desc illegal_desc{};
iss::instrumentation_if *arch_instr;
std::vector<instr_desc> delays;
unsigned current_delay{0};
struct pair_hash {
size_t operator()(const std::pair<uint64_t, uint64_t>& p) const {
size_t operator()(const std::pair<uint64_t, uint64_t> &p) const {
std::hash<uint64_t> hash;
return hash(p.first) + hash(p.second);
}
};
std::unordered_map<std::pair<uint64_t, uint64_t>, uint64_t, pair_hash> blocks;
std::string config_file_name;
Json::Value root;
};
} // namespace plugin
} // namespace iss
}
}
#endif /* _ISS_PLUGIN_CYCLE_ESTIMATE_H_ */

21
src/iss/plugin/instruction_count.h → incl/iss/plugin/instruction_count.h
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@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017 - 2023, MINRES Technologies GmbH
* Copyright (C) 2017, 2018, MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -36,8 +36,8 @@
#define _ISS_PLUGIN_INSTRUCTION_COUNTER_H_
#include <iss/vm_plugin.h>
#include <json/json.h>
#include <string>
#include <vector>
namespace iss {
namespace plugin {
@ -53,29 +53,30 @@ class instruction_count : public iss::vm_plugin {
public:
instruction_count() = delete;
instruction_count(const instruction_count&) = delete;
instruction_count(const instruction_count &) = delete;
instruction_count(const instruction_count&&) = delete;
instruction_count(const instruction_count &&) = delete;
instruction_count(std::string config_file_name);
virtual ~instruction_count();
instruction_count& operator=(const instruction_count&) = delete;
instruction_count &operator=(const instruction_count &) = delete;
instruction_count& operator=(const instruction_count&&) = delete;
instruction_count &operator=(const instruction_count &&) = delete;
bool registration(const char* const version, vm_if& arch) override;
bool registration(const char *const version, vm_if &arch) override;
sync_type get_sync() override { return POST_SYNC; };
void callback(instr_info_t) override;
void callback(instr_info_t instr_info) override;
private:
Json::Value root;
std::vector<instr_delay> delays;
std::vector<uint64_t> rep_counts;
};
} // namespace plugin
} // namespace iss
}
}
#endif /* _ISS_PLUGIN_INSTRUCTION_COUNTER_H_ */

162
incl/sysc/core_complex.h Normal file
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@ -0,0 +1,162 @@
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#ifndef _SYSC_SIFIVE_FE310_H_
#define _SYSC_SIFIVE_FE310_H_
#include "scc/initiator_mixin.h"
#include "scc/traceable.h"
#include "scc/utilities.h"
#include "scv4tlm/tlm_rec_initiator_socket.h"
#include <cci_configuration>
#include <tlm>
#include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
#include <tlm_utils/tlm_quantumkeeper.h>
#include <util/range_lut.h>
class scv_tr_db;
class scv_tr_stream;
struct _scv_tr_generator_default_data;
template <class T_begin, class T_end> class scv_tr_generator;
namespace iss {
class vm_if;
namespace arch {
template <typename BASE> class riscv_hart_msu_vp;
}
namespace debugger {
class target_adapter_if;
}
}
namespace sysc {
class tlm_dmi_ext : public tlm::tlm_dmi {
public:
bool operator==(const tlm_dmi_ext &o) const {
return this->get_granted_access() == o.get_granted_access() &&
this->get_start_address() == o.get_start_address() && this->get_end_address() == o.get_end_address();
}
bool operator!=(const tlm_dmi_ext &o) const { return !operator==(o); }
};
namespace SiFive {
class core_wrapper;
class core_complex : public sc_core::sc_module, public scc::traceable {
public:
scc::initiator_mixin<scv4tlm::tlm_rec_initiator_socket<32>> initiator;
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
sc_core::sc_in<bool> global_irq_i;
sc_core::sc_in<bool> timer_irq_i;
sc_core::sc_in<bool> sw_irq_i;
sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i;
sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
cci::cci_param<std::string> elf_file;
cci::cci_param<bool> enable_disass;
cci::cci_param<uint64_t> reset_address;
cci::cci_param<unsigned short> gdb_server_port;
cci::cci_param<bool> dump_ir;
core_complex(sc_core::sc_module_name name);
~core_complex();
inline void sync(uint64_t cycle) {
auto time = curr_clk * (cycle - last_sync_cycle);
quantum_keeper.inc(time);
if (quantum_keeper.need_sync()) {
wait(quantum_keeper.get_local_time());
quantum_keeper.reset();
}
last_sync_cycle = cycle;
}
bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
bool write_mem(uint64_t addr, unsigned length, const uint8_t *const data);
bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data);
bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data);
void trace(sc_core::sc_trace_file *trf) const override;
void disass_output(uint64_t pc, const std::string instr);
protected:
void before_end_of_elaboration() override;
void start_of_simulation() override;
void run();
void clk_cb();
void rst_cb();
void sw_irq_cb();
void timer_irq_cb();
void global_irq_cb();
uint64_t last_sync_cycle = 0;
util::range_lut<tlm_dmi_ext> read_lut, write_lut;
tlm_utils::tlm_quantumkeeper quantum_keeper;
std::vector<uint8_t> write_buf;
std::unique_ptr<core_wrapper> cpu;
std::unique_ptr<iss::vm_if> vm;
sc_core::sc_time curr_clk;
iss::debugger::target_adapter_if *tgt_adapter;
#ifdef WITH_SCV
//! transaction recording database
scv_tr_db *m_db;
//! blocking transaction recording stream handle
scv_tr_stream *stream_handle;
//! transaction generator handle for blocking transactions
scv_tr_generator<_scv_tr_generator_default_data, _scv_tr_generator_default_data> *instr_tr_handle;
scv_tr_generator<uint64_t, _scv_tr_generator_default_data> *fetch_tr_handle;
scv_tr_handle tr_handle;
#endif
};
} /* namespace SiFive */
} /* namespace sysc */
#endif /* _SYSC_SIFIVE_FE310_H_ */

2
softfloat/.gitignore vendored
View File

@ -1,2 +0,0 @@
build/*/*.o
build/*/*.a

61
softfloat/CMakeLists.txt
View File

@ -2,17 +2,31 @@ cmake_minimum_required(VERSION 3.12)
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/../cmake) # main (top) cmake dir
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake) # project specific cmake dir
# CMake useful variables
set(CMAKE_RUNTIME_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/bin")
set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib")
set(CMAKE_LIBRARY_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib")
# Set the name of your project here
project("sotfloat" VERSION 3.0.0)
project("sotfloat")
# Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0)
set(VERSION "3e")
#include(Common)
include(GNUInstallDirs)
include(Common)
set(SPECIALIZATION RISCV)
add_definitions(
-DSOFTFLOAT_ROUND_ODD
-DINLINE_LEVEL=5
-DSOFTFLOAT_FAST_DIV32TO16
-DSOFTFLOAT_FAST_DIV64TO32
-DSOFTFLOAT_FAST_INT64
# -DTHREAD_LOCAL=__thread
)
set(LIB_HEADERS source/include/softfloat.h source/include/softfloat_types.h)
set(PRIMITIVES
source/s_eq128.c
@ -327,29 +341,32 @@ set(OTHERS
set(LIB_SOURCES ${PRIMITIVES} ${SPECIALIZE} ${OTHERS})
add_library(softfloat STATIC ${LIB_SOURCES})
set_property(TARGET softfloat PROPERTY C_STANDARD 99)
target_compile_definitions(softfloat PRIVATE
SOFTFLOAT_ROUND_ODD
INLINE_LEVEL=5
SOFTFLOAT_FAST_DIV32TO16
SOFTFLOAT_FAST_DIV64TO32
SOFTFLOAT_FAST_INT64
# THREAD_LOCAL=__thread
)
target_include_directories(softfloat PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/build/Linux-x86_64-GCC)
target_include_directories(softfloat PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/source/include ${CMAKE_CURRENT_SOURCE_DIR}/source/${SPECIALIZATION})
set_target_properties(softfloat PROPERTIES
# Define two variables in order not to repeat ourselves.
set(LIBRARY_NAME softfloat)
# Define the library
add_library(${LIBRARY_NAME} ${LIB_SOURCES})
set_property(TARGET ${LIBRARY_NAME} PROPERTY C_STANDARD 99)
target_include_directories(${LIBRARY_NAME} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/build/Linux-x86_64-GCC)
target_include_directories(${LIBRARY_NAME} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/source/include ${CMAKE_CURRENT_SOURCE_DIR}/source/${SPECIALIZATION})
# Set the build version. It will be used in the name of the lib, with corresponding
# symlinks created. SOVERSION could also be specified for api version.
set_target_properties(${LIBRARY_NAME} PROPERTIES
VERSION ${VERSION}
FRAMEWORK FALSE
PUBLIC_HEADER "${LIB_HEADERS}"
)
install(TARGETS softfloat
# Says how and where to install software
# Targets:
# * <prefix>/lib/<libraries>
# * header location after install: <prefix>/include/<project>/*.h
# * headers can be included by C++ code `#<project>/Bar.hpp>`
install(TARGETS ${LIBRARY_NAME}
EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}/static COMPONENT libs # static lib
LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # shared lib
FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac
PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} COMPONENT devel # headers for mac (note the different component -> different package)
INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
ARCHIVE DESTINATION lib COMPONENT libs # static lib
LIBRARY DESTINATION lib COMPONENT libs # shared lib
FRAMEWORK DESTINATION bin COMPONENT libs # for mac
PUBLIC_HEADER DESTINATION include COMPONENT devel # headers for mac (note the different component -> different package)
INCLUDES DESTINATION include # headers
)

74
softfloat/COPYING.txt
View File

@ -1,37 +1,37 @@
License for Berkeley SoftFloat Release 3e
John R. Hauser
2018 January 20
The following applies to the whole of SoftFloat Release 3e as well as to
each source file individually.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions, and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors
may be used to endorse or promote products derived from this software
without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
License for Berkeley SoftFloat Release 3e
John R. Hauser
2018 January 20
The following applies to the whole of SoftFloat Release 3e as well as to
each source file individually.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions, and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors
may be used to endorse or promote products derived from this software
without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

98
softfloat/README.html
View File

@ -1,49 +1,49 @@
<HTML>
<HEAD>
<TITLE>Berkeley SoftFloat Package Overview</TITLE>
</HEAD>
<BODY>
<H1>Package Overview for Berkeley SoftFloat Release 3e</H1>
<P>
John R. Hauser<BR>
2018 January 20<BR>
</P>
<P>
Berkeley SoftFloat is a software implementation of binary floating-point that
conforms to the IEEE Standard for Floating-Point Arithmetic.
SoftFloat is distributed in the form of C source code.
Building the SoftFloat sources generates a library file (typically
<CODE>softfloat.a</CODE> or <CODE>libsoftfloat.a</CODE>) containing the
floating-point subroutines.
</P>
<P>
The SoftFloat package is documented in the following files in the
<CODE>doc</CODE> subdirectory:
<BLOCKQUOTE>
<TABLE>
<TR>
<TD><A HREF="doc/SoftFloat.html"><NOBR><CODE>SoftFloat.html</CODE></NOBR></A></TD>
<TD>Documentation for using the SoftFloat functions.</TD>
</TR>
<TR>
<TD><A HREF="doc/SoftFloat-source.html"><NOBR><CODE>SoftFloat-source.html</CODE></NOBR></A></TD>
<TD>Documentation for building SoftFloat.</TD>
</TR>
<TR>
<TD><A HREF="doc/SoftFloat-history.html"><NOBR><CODE>SoftFloat-history.html</CODE></A><CODE>&nbsp;&nbsp;&nbsp;</CODE></NOBR></TD>
<TD>History of the major changes to SoftFloat.</TD>
</TR>
</TABLE>
</BLOCKQUOTE>
Other files in the package comprise the source code for SoftFloat.
</P>
</BODY>
<HTML>
<HEAD>
<TITLE>Berkeley SoftFloat Package Overview</TITLE>
</HEAD>
<BODY>
<H1>Package Overview for Berkeley SoftFloat Release 3e</H1>
<P>
John R. Hauser<BR>
2018 January 20<BR>
</P>
<P>
Berkeley SoftFloat is a software implementation of binary floating-point that
conforms to the IEEE Standard for Floating-Point Arithmetic.
SoftFloat is distributed in the form of C source code.
Building the SoftFloat sources generates a library file (typically
<CODE>softfloat.a</CODE> or <CODE>libsoftfloat.a</CODE>) containing the
floating-point subroutines.
</P>
<P>
The SoftFloat package is documented in the following files in the
<CODE>doc</CODE> subdirectory:
<BLOCKQUOTE>
<TABLE>
<TR>
<TD><A HREF="doc/SoftFloat.html"><NOBR><CODE>SoftFloat.html</CODE></NOBR></A></TD>
<TD>Documentation for using the SoftFloat functions.</TD>
</TR>
<TR>
<TD><A HREF="doc/SoftFloat-source.html"><NOBR><CODE>SoftFloat-source.html</CODE></NOBR></A></TD>
<TD>Documentation for building SoftFloat.</TD>
</TR>
<TR>
<TD><A HREF="doc/SoftFloat-history.html"><NOBR><CODE>SoftFloat-history.html</CODE></A><CODE>&nbsp;&nbsp;&nbsp;</CODE></NOBR></TD>
<TD>History of the major changes to SoftFloat.</TD>
</TR>
</TABLE>
</BLOCKQUOTE>
Other files in the package comprise the source code for SoftFloat.
</P>
</BODY>

24
softfloat/README.md
View File

@ -1,24 +0,0 @@
Package Overview for Berkeley SoftFloat Release 3e
==================================================
John R. Hauser<br>
2018 January 20
Berkeley SoftFloat is a software implementation of binary floating-point
that conforms to the IEEE Standard for Floating-Point Arithmetic. SoftFloat
is distributed in the form of C source code. Building the SoftFloat sources
generates a library file (typically `softfloat.a` or `libsoftfloat.a`)
containing the floating-point subroutines.
The SoftFloat package is documented in the following files in the `doc`
subdirectory:
* [SoftFloat.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat.html) Documentation for using the SoftFloat functions.
* [SoftFloat-source.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat-source.html) Documentation for building SoftFloat.
* [SoftFloat-history.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat-history.html) History of the major changes to SoftFloat.
Other files in the package comprise the source code for SoftFloat.

42
softfloat/README.txt
View File

@ -1,21 +1,21 @@
Package Overview for Berkeley SoftFloat Release 3e
John R. Hauser
2018 January 20
Berkeley SoftFloat is a software implementation of binary floating-point
that conforms to the IEEE Standard for Floating-Point Arithmetic. SoftFloat
is distributed in the form of C source code. Building the SoftFloat sources
generates a library file (typically "softfloat.a" or "libsoftfloat.a")
containing the floating-point subroutines.
The SoftFloat package is documented in the following files in the "doc"
subdirectory:
SoftFloat.html Documentation for using the SoftFloat functions.
SoftFloat-source.html Documentation for building SoftFloat.
SoftFloat-history.html History of the major changes to SoftFloat.
Other files in the package comprise the source code for SoftFloat.
Package Overview for Berkeley SoftFloat Release 3e
John R. Hauser
2018 January 20
Berkeley SoftFloat is a software implementation of binary floating-point
that conforms to the IEEE Standard for Floating-Point Arithmetic. SoftFloat
is distributed in the form of C source code. Building the SoftFloat sources
generates a library file (typically "softfloat.a" or "libsoftfloat.a")
containing the floating-point subroutines.
The SoftFloat package is documented in the following files in the "doc"
subdirectory:
SoftFloat.html Documentation for using the SoftFloat functions.
SoftFloat-source.html Documentation for building SoftFloat.
SoftFloat-history.html History of the major changes to SoftFloat.
Other files in the package comprise the source code for SoftFloat.

650
softfloat/build/Linux-386-GCC/Makefile
View File

@ -1,325 +1,325 @@
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= 8086
SOFTFLOAT_OPTS ?= \
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-DSOFTFLOAT_FAST_DIV64TO32
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
$(C_INCLUDES) -O2 -o $@
MAKELIB = ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS =
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_compare96M$(OBJ) \
s_compare128M$(OBJ) \
s_shortShiftLeft64To96M$(OBJ) \
s_shortShiftLeftM$(OBJ) \
s_shiftLeftM$(OBJ) \
s_shortShiftRightM$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJamM$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJamM$(OBJ) \
s_shiftRightM$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_addM$(OBJ) \
s_addCarryM$(OBJ) \
s_addComplCarryM$(OBJ) \
s_negXM$(OBJ) \
s_sub1XM$(OBJ) \
s_subM$(OBJ) \
s_mul64To128M$(OBJ) \
s_mul128MTo256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
s_remStepMBy32$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80MToCommonNaN$(OBJ) \
s_commonNaNToExtF80M$(OBJ) \
s_propagateNaNExtF80M$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128MToCommonNaN$(OBJ) \
s_commonNaNToF128M$(OBJ) \
s_propagateNaNF128M$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundMToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundMToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_tryPropagateNaNExtF80M$(OBJ) \
s_invalidExtF80M$(OBJ) \
s_normExtF80SigM$(OBJ) \
s_roundPackMToExtF80M$(OBJ) \
s_normRoundPackMToExtF80M$(OBJ) \
s_addExtF80M$(OBJ) \
s_compareNonnormExtF80M$(OBJ) \
s_isNaNF128M$(OBJ) \
s_tryPropagateNaNF128M$(OBJ) \
s_invalidF128M$(OBJ) \
s_shiftNormSigF128M$(OBJ) \
s_roundPackMToF128M$(OBJ) \
s_normRoundPackMToF128M$(OBJ) \
s_addF128M$(OBJ) \
s_mulAddF128M$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= 8086
SOFTFLOAT_OPTS ?= \
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-DSOFTFLOAT_FAST_DIV64TO32
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
$(C_INCLUDES) -O2 -o $@
MAKELIB = ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS =
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_compare96M$(OBJ) \
s_compare128M$(OBJ) \
s_shortShiftLeft64To96M$(OBJ) \
s_shortShiftLeftM$(OBJ) \
s_shiftLeftM$(OBJ) \
s_shortShiftRightM$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJamM$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJamM$(OBJ) \
s_shiftRightM$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_addM$(OBJ) \
s_addCarryM$(OBJ) \
s_addComplCarryM$(OBJ) \
s_negXM$(OBJ) \
s_sub1XM$(OBJ) \
s_subM$(OBJ) \
s_mul64To128M$(OBJ) \
s_mul128MTo256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
s_remStepMBy32$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80MToCommonNaN$(OBJ) \
s_commonNaNToExtF80M$(OBJ) \
s_propagateNaNExtF80M$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128MToCommonNaN$(OBJ) \
s_commonNaNToF128M$(OBJ) \
s_propagateNaNF128M$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundMToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundMToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_tryPropagateNaNExtF80M$(OBJ) \
s_invalidExtF80M$(OBJ) \
s_normExtF80SigM$(OBJ) \
s_roundPackMToExtF80M$(OBJ) \
s_normRoundPackMToExtF80M$(OBJ) \
s_addExtF80M$(OBJ) \
s_compareNonnormExtF80M$(OBJ) \
s_isNaNF128M$(OBJ) \
s_tryPropagateNaNF128M$(OBJ) \
s_invalidF128M$(OBJ) \
s_shiftNormSigF128M$(OBJ) \
s_roundPackMToF128M$(OBJ) \
s_normRoundPackMToF128M$(OBJ) \
s_addF128M$(OBJ) \
s_mulAddF128M$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)

106
softfloat/build/Linux-386-GCC/platform.h
View File

@ -1,53 +1,53 @@
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
#define INLINE inline
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define SOFTFLOAT_BUILTIN_CLZ 1
#include "opts-GCC.h"
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
#define INLINE inline
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define SOFTFLOAT_BUILTIN_CLZ 1
#include "opts-GCC.h"

650
softfloat/build/Linux-386-SSE2-GCC/Makefile
View File

@ -1,325 +1,325 @@
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= 8086-SSE
SOFTFLOAT_OPTS ?= \
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-DSOFTFLOAT_FAST_DIV64TO32
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
$(C_INCLUDES) -O2 -o $@
MAKELIB = ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS =
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_compare96M$(OBJ) \
s_compare128M$(OBJ) \
s_shortShiftLeft64To96M$(OBJ) \
s_shortShiftLeftM$(OBJ) \
s_shiftLeftM$(OBJ) \
s_shortShiftRightM$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJamM$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJamM$(OBJ) \
s_shiftRightM$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_addM$(OBJ) \
s_addCarryM$(OBJ) \
s_addComplCarryM$(OBJ) \
s_negXM$(OBJ) \
s_sub1XM$(OBJ) \
s_subM$(OBJ) \
s_mul64To128M$(OBJ) \
s_mul128MTo256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
s_remStepMBy32$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80MToCommonNaN$(OBJ) \
s_commonNaNToExtF80M$(OBJ) \
s_propagateNaNExtF80M$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128MToCommonNaN$(OBJ) \
s_commonNaNToF128M$(OBJ) \
s_propagateNaNF128M$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundMToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundMToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_tryPropagateNaNExtF80M$(OBJ) \
s_invalidExtF80M$(OBJ) \
s_normExtF80SigM$(OBJ) \
s_roundPackMToExtF80M$(OBJ) \
s_normRoundPackMToExtF80M$(OBJ) \
s_addExtF80M$(OBJ) \
s_compareNonnormExtF80M$(OBJ) \
s_isNaNF128M$(OBJ) \
s_tryPropagateNaNF128M$(OBJ) \
s_invalidF128M$(OBJ) \
s_shiftNormSigF128M$(OBJ) \
s_roundPackMToF128M$(OBJ) \
s_normRoundPackMToF128M$(OBJ) \
s_addF128M$(OBJ) \
s_mulAddF128M$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= 8086-SSE
SOFTFLOAT_OPTS ?= \
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-DSOFTFLOAT_FAST_DIV64TO32
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
$(C_INCLUDES) -O2 -o $@
MAKELIB = ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS =
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_compare96M$(OBJ) \
s_compare128M$(OBJ) \
s_shortShiftLeft64To96M$(OBJ) \
s_shortShiftLeftM$(OBJ) \
s_shiftLeftM$(OBJ) \
s_shortShiftRightM$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJamM$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJamM$(OBJ) \
s_shiftRightM$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_addM$(OBJ) \
s_addCarryM$(OBJ) \
s_addComplCarryM$(OBJ) \
s_negXM$(OBJ) \
s_sub1XM$(OBJ) \
s_subM$(OBJ) \
s_mul64To128M$(OBJ) \
s_mul128MTo256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
s_remStepMBy32$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80MToCommonNaN$(OBJ) \
s_commonNaNToExtF80M$(OBJ) \
s_propagateNaNExtF80M$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128MToCommonNaN$(OBJ) \
s_commonNaNToF128M$(OBJ) \
s_propagateNaNF128M$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundMToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundMToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_tryPropagateNaNExtF80M$(OBJ) \
s_invalidExtF80M$(OBJ) \
s_normExtF80SigM$(OBJ) \
s_roundPackMToExtF80M$(OBJ) \
s_normRoundPackMToExtF80M$(OBJ) \
s_addExtF80M$(OBJ) \
s_compareNonnormExtF80M$(OBJ) \
s_isNaNF128M$(OBJ) \
s_tryPropagateNaNF128M$(OBJ) \
s_invalidF128M$(OBJ) \
s_shiftNormSigF128M$(OBJ) \
s_roundPackMToF128M$(OBJ) \
s_normRoundPackMToF128M$(OBJ) \
s_addF128M$(OBJ) \
s_mulAddF128M$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)

106
softfloat/build/Linux-386-SSE2-GCC/platform.h
View File

@ -1,53 +1,53 @@
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
#define INLINE inline
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define SOFTFLOAT_BUILTIN_CLZ 1
#include "opts-GCC.h"
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
#define INLINE inline
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define SOFTFLOAT_BUILTIN_CLZ 1
#include "opts-GCC.h"

646
softfloat/build/Linux-ARM-VFPv2-GCC/Makefile
View File

@ -1,323 +1,323 @@
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= ARM-VFPv2
SOFTFLOAT_OPTS ?= -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
$(C_INCLUDES) -O2 -o $@
MAKELIB = ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS =
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_compare96M$(OBJ) \
s_compare128M$(OBJ) \
s_shortShiftLeft64To96M$(OBJ) \
s_shortShiftLeftM$(OBJ) \
s_shiftLeftM$(OBJ) \
s_shortShiftRightM$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJamM$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJamM$(OBJ) \
s_shiftRightM$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_addM$(OBJ) \
s_addCarryM$(OBJ) \
s_addComplCarryM$(OBJ) \
s_negXM$(OBJ) \
s_sub1XM$(OBJ) \
s_subM$(OBJ) \
s_mul64To128M$(OBJ) \
s_mul128MTo256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
s_remStepMBy32$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80MToCommonNaN$(OBJ) \
s_commonNaNToExtF80M$(OBJ) \
s_propagateNaNExtF80M$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128MToCommonNaN$(OBJ) \
s_commonNaNToF128M$(OBJ) \
s_propagateNaNF128M$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundMToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundMToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_tryPropagateNaNExtF80M$(OBJ) \
s_invalidExtF80M$(OBJ) \
s_normExtF80SigM$(OBJ) \
s_roundPackMToExtF80M$(OBJ) \
s_normRoundPackMToExtF80M$(OBJ) \
s_addExtF80M$(OBJ) \
s_compareNonnormExtF80M$(OBJ) \
s_isNaNF128M$(OBJ) \
s_tryPropagateNaNF128M$(OBJ) \
s_invalidF128M$(OBJ) \
s_shiftNormSigF128M$(OBJ) \
s_roundPackMToF128M$(OBJ) \
s_normRoundPackMToF128M$(OBJ) \
s_addF128M$(OBJ) \
s_mulAddF128M$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= ARM-VFPv2
SOFTFLOAT_OPTS ?= -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
$(C_INCLUDES) -O2 -o $@
MAKELIB = ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS =
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_compare96M$(OBJ) \
s_compare128M$(OBJ) \
s_shortShiftLeft64To96M$(OBJ) \
s_shortShiftLeftM$(OBJ) \
s_shiftLeftM$(OBJ) \
s_shortShiftRightM$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJamM$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJamM$(OBJ) \
s_shiftRightM$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_addM$(OBJ) \
s_addCarryM$(OBJ) \
s_addComplCarryM$(OBJ) \
s_negXM$(OBJ) \
s_sub1XM$(OBJ) \
s_subM$(OBJ) \
s_mul64To128M$(OBJ) \
s_mul128MTo256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
s_remStepMBy32$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80MToCommonNaN$(OBJ) \
s_commonNaNToExtF80M$(OBJ) \
s_propagateNaNExtF80M$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128MToCommonNaN$(OBJ) \
s_commonNaNToF128M$(OBJ) \
s_propagateNaNF128M$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundMToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundMToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_tryPropagateNaNExtF80M$(OBJ) \
s_invalidExtF80M$(OBJ) \
s_normExtF80SigM$(OBJ) \
s_roundPackMToExtF80M$(OBJ) \
s_normRoundPackMToExtF80M$(OBJ) \
s_addExtF80M$(OBJ) \
s_compareNonnormExtF80M$(OBJ) \
s_isNaNF128M$(OBJ) \
s_tryPropagateNaNF128M$(OBJ) \
s_invalidF128M$(OBJ) \
s_shiftNormSigF128M$(OBJ) \
s_roundPackMToF128M$(OBJ) \
s_normRoundPackMToF128M$(OBJ) \
s_addF128M$(OBJ) \
s_mulAddF128M$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)

106
softfloat/build/Linux-ARM-VFPv2-GCC/platform.h
View File

@ -1,53 +1,53 @@
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
#define INLINE inline
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define SOFTFLOAT_BUILTIN_CLZ 1
#include "opts-GCC.h"
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
#define INLINE inline
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define SOFTFLOAT_BUILTIN_CLZ 1
#include "opts-GCC.h"

399
softfloat/build/Linux-RISCV64-GCC/Makefile
View File

@ -1,399 +0,0 @@
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= RISCV
MARCH ?= rv64gcv_zfh_zfhmin
MABI ?= lp64d
SOFTFLOAT_OPTS ?= \
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-DSOFTFLOAT_FAST_DIV64TO32
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
riscv64-unknown-linux-gnu-gcc -c -march=$(MARCH) -mabi=$(MABI) -Werror-implicit-function-declaration -DSOFTFLOAT_FAST_INT64 \
$(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
MAKELIB = ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_eq128$(OBJ) \
s_le128$(OBJ) \
s_lt128$(OBJ) \
s_shortShiftLeft128$(OBJ) \
s_shortShiftRight128$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJam64Extra$(OBJ) \
s_shortShiftRightJam128$(OBJ) \
s_shortShiftRightJam128Extra$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJam64Extra$(OBJ) \
s_shiftRightJam128$(OBJ) \
s_shiftRightJam128Extra$(OBJ) \
s_shiftRightJam256M$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_add128$(OBJ) \
s_add256M$(OBJ) \
s_sub128$(OBJ) \
s_sub256M$(OBJ) \
s_mul64ByShifted32To128$(OBJ) \
s_mul64To128$(OBJ) \
s_mul128By32$(OBJ) \
s_mul128To256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_bf16UIToCommonNaN$(OBJ) \
s_commonNaNToBF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80UIToCommonNaN$(OBJ) \
s_commonNaNToExtF80UI$(OBJ) \
s_propagateNaNExtF80UI$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128UIToCommonNaN$(OBJ) \
s_commonNaNToF128UI$(OBJ) \
s_propagateNaNF128UI$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundToI64$(OBJ) \
s_normSubnormalBF16Sig$(OBJ) \
s_roundPackToBF16$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_normSubnormalExtF80Sig$(OBJ) \
s_roundPackToExtF80$(OBJ) \
s_normRoundPackToExtF80$(OBJ) \
s_addMagsExtF80$(OBJ) \
s_subMagsExtF80$(OBJ) \
s_normSubnormalF128Sig$(OBJ) \
s_roundPackToF128$(OBJ) \
s_normRoundPackToF128$(OBJ) \
s_addMagsF128$(OBJ) \
s_subMagsF128$(OBJ) \
s_mulAddF128$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128$(OBJ) \
i64_to_f128M$(OBJ) \
bf16_isSignalingNaN$(OBJ) \
bf16_to_f32$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_bf16$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80_to_ui32$(OBJ) \
extF80_to_ui64$(OBJ) \
extF80_to_i32$(OBJ) \
extF80_to_i64$(OBJ) \
extF80_to_ui32_r_minMag$(OBJ) \
extF80_to_ui64_r_minMag$(OBJ) \
extF80_to_i32_r_minMag$(OBJ) \
extF80_to_i64_r_minMag$(OBJ) \
extF80_to_f16$(OBJ) \
extF80_to_f32$(OBJ) \
extF80_to_f64$(OBJ) \
extF80_to_f128$(OBJ) \
extF80_roundToInt$(OBJ) \
extF80_add$(OBJ) \
extF80_sub$(OBJ) \
extF80_mul$(OBJ) \
extF80_div$(OBJ) \
extF80_rem$(OBJ) \
extF80_sqrt$(OBJ) \
extF80_eq$(OBJ) \
extF80_le$(OBJ) \
extF80_lt$(OBJ) \
extF80_eq_signaling$(OBJ) \
extF80_le_quiet$(OBJ) \
extF80_lt_quiet$(OBJ) \
extF80_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128_to_ui32$(OBJ) \
f128_to_ui64$(OBJ) \
f128_to_i32$(OBJ) \
f128_to_i64$(OBJ) \
f128_to_ui32_r_minMag$(OBJ) \
f128_to_ui64_r_minMag$(OBJ) \
f128_to_i32_r_minMag$(OBJ) \
f128_to_i64_r_minMag$(OBJ) \
f128_to_f16$(OBJ) \
f128_to_f32$(OBJ) \
f128_to_extF80$(OBJ) \
f128_to_f64$(OBJ) \
f128_roundToInt$(OBJ) \
f128_add$(OBJ) \
f128_sub$(OBJ) \
f128_mul$(OBJ) \
f128_mulAdd$(OBJ) \
f128_div$(OBJ) \
f128_rem$(OBJ) \
f128_sqrt$(OBJ) \
f128_eq$(OBJ) \
f128_le$(OBJ) \
f128_lt$(OBJ) \
f128_eq_signaling$(OBJ) \
f128_le_quiet$(OBJ) \
f128_lt_quiet$(OBJ) \
f128_isSignalingNaN$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)

54
softfloat/build/Linux-RISCV64-GCC/platform.h
View File

@ -1,54 +0,0 @@
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
#define INLINE inline
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define SOFTFLOAT_BUILTIN_CLZ 1
#define SOFTFLOAT_INTRINSIC_INT128 1
#include "opts-GCC.h"

787
softfloat/build/Linux-x86_64-GCC/Makefile
View File

@ -1,397 +1,390 @@
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= 8086-SSE
SOFTFLOAT_OPTS ?= \
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-DSOFTFLOAT_FAST_DIV64TO32
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
gcc -c -Werror-implicit-function-declaration -DSOFTFLOAT_FAST_INT64 \
$(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
MAKELIB = ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_eq128$(OBJ) \
s_le128$(OBJ) \
s_lt128$(OBJ) \
s_shortShiftLeft128$(OBJ) \
s_shortShiftRight128$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJam64Extra$(OBJ) \
s_shortShiftRightJam128$(OBJ) \
s_shortShiftRightJam128Extra$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJam64Extra$(OBJ) \
s_shiftRightJam128$(OBJ) \
s_shiftRightJam128Extra$(OBJ) \
s_shiftRightJam256M$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_add128$(OBJ) \
s_add256M$(OBJ) \
s_sub128$(OBJ) \
s_sub256M$(OBJ) \
s_mul64ByShifted32To128$(OBJ) \
s_mul64To128$(OBJ) \
s_mul128By32$(OBJ) \
s_mul128To256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_bf16UIToCommonNaN$(OBJ) \
s_commonNaNToBF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80UIToCommonNaN$(OBJ) \
s_commonNaNToExtF80UI$(OBJ) \
s_propagateNaNExtF80UI$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128UIToCommonNaN$(OBJ) \
s_commonNaNToF128UI$(OBJ) \
s_propagateNaNF128UI$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundToI64$(OBJ) \
s_normSubnormalBF16Sig$(OBJ) \
s_roundPackToBF16$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_normSubnormalExtF80Sig$(OBJ) \
s_roundPackToExtF80$(OBJ) \
s_normRoundPackToExtF80$(OBJ) \
s_addMagsExtF80$(OBJ) \
s_subMagsExtF80$(OBJ) \
s_normSubnormalF128Sig$(OBJ) \
s_roundPackToF128$(OBJ) \
s_normRoundPackToF128$(OBJ) \
s_addMagsF128$(OBJ) \
s_subMagsF128$(OBJ) \
s_mulAddF128$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128$(OBJ) \
i64_to_f128M$(OBJ) \
bf16_isSignalingNaN$(OBJ) \
bf16_to_f32$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_bf16$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80_to_ui32$(OBJ) \
extF80_to_ui64$(OBJ) \
extF80_to_i32$(OBJ) \
extF80_to_i64$(OBJ) \
extF80_to_ui32_r_minMag$(OBJ) \
extF80_to_ui64_r_minMag$(OBJ) \
extF80_to_i32_r_minMag$(OBJ) \
extF80_to_i64_r_minMag$(OBJ) \
extF80_to_f16$(OBJ) \
extF80_to_f32$(OBJ) \
extF80_to_f64$(OBJ) \
extF80_to_f128$(OBJ) \
extF80_roundToInt$(OBJ) \
extF80_add$(OBJ) \
extF80_sub$(OBJ) \
extF80_mul$(OBJ) \
extF80_div$(OBJ) \
extF80_rem$(OBJ) \
extF80_sqrt$(OBJ) \
extF80_eq$(OBJ) \
extF80_le$(OBJ) \
extF80_lt$(OBJ) \
extF80_eq_signaling$(OBJ) \
extF80_le_quiet$(OBJ) \
extF80_lt_quiet$(OBJ) \
extF80_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128_to_ui32$(OBJ) \
f128_to_ui64$(OBJ) \
f128_to_i32$(OBJ) \
f128_to_i64$(OBJ) \
f128_to_ui32_r_minMag$(OBJ) \
f128_to_ui64_r_minMag$(OBJ) \
f128_to_i32_r_minMag$(OBJ) \
f128_to_i64_r_minMag$(OBJ) \
f128_to_f16$(OBJ) \
f128_to_f32$(OBJ) \
f128_to_extF80$(OBJ) \
f128_to_f64$(OBJ) \
f128_roundToInt$(OBJ) \
f128_add$(OBJ) \
f128_sub$(OBJ) \
f128_mul$(OBJ) \
f128_mulAdd$(OBJ) \
f128_div$(OBJ) \
f128_rem$(OBJ) \
f128_sqrt$(OBJ) \
f128_eq$(OBJ) \
f128_le$(OBJ) \
f128_lt$(OBJ) \
f128_eq_signaling$(OBJ) \
f128_le_quiet$(OBJ) \
f128_lt_quiet$(OBJ) \
f128_isSignalingNaN$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= 8086-SSE
SOFTFLOAT_OPTS ?= \
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-DSOFTFLOAT_FAST_DIV64TO32
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
gcc -c -Werror-implicit-function-declaration -DSOFTFLOAT_FAST_INT64 \
$(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
MAKELIB = ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_eq128$(OBJ) \
s_le128$(OBJ) \
s_lt128$(OBJ) \
s_shortShiftLeft128$(OBJ) \
s_shortShiftRight128$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJam64Extra$(OBJ) \
s_shortShiftRightJam128$(OBJ) \
s_shortShiftRightJam128Extra$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJam64Extra$(OBJ) \
s_shiftRightJam128$(OBJ) \
s_shiftRightJam128Extra$(OBJ) \
s_shiftRightJam256M$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_add128$(OBJ) \
s_add256M$(OBJ) \
s_sub128$(OBJ) \
s_sub256M$(OBJ) \
s_mul64ByShifted32To128$(OBJ) \
s_mul64To128$(OBJ) \
s_mul128By32$(OBJ) \
s_mul128To256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80UIToCommonNaN$(OBJ) \
s_commonNaNToExtF80UI$(OBJ) \
s_propagateNaNExtF80UI$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128UIToCommonNaN$(OBJ) \
s_commonNaNToF128UI$(OBJ) \
s_propagateNaNF128UI$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_normSubnormalExtF80Sig$(OBJ) \
s_roundPackToExtF80$(OBJ) \
s_normRoundPackToExtF80$(OBJ) \
s_addMagsExtF80$(OBJ) \
s_subMagsExtF80$(OBJ) \
s_normSubnormalF128Sig$(OBJ) \
s_roundPackToF128$(OBJ) \
s_normRoundPackToF128$(OBJ) \
s_addMagsF128$(OBJ) \
s_subMagsF128$(OBJ) \
s_mulAddF128$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80_to_ui32$(OBJ) \
extF80_to_ui64$(OBJ) \
extF80_to_i32$(OBJ) \
extF80_to_i64$(OBJ) \
extF80_to_ui32_r_minMag$(OBJ) \
extF80_to_ui64_r_minMag$(OBJ) \
extF80_to_i32_r_minMag$(OBJ) \
extF80_to_i64_r_minMag$(OBJ) \
extF80_to_f16$(OBJ) \
extF80_to_f32$(OBJ) \
extF80_to_f64$(OBJ) \
extF80_to_f128$(OBJ) \
extF80_roundToInt$(OBJ) \
extF80_add$(OBJ) \
extF80_sub$(OBJ) \
extF80_mul$(OBJ) \
extF80_div$(OBJ) \
extF80_rem$(OBJ) \
extF80_sqrt$(OBJ) \
extF80_eq$(OBJ) \
extF80_le$(OBJ) \
extF80_lt$(OBJ) \
extF80_eq_signaling$(OBJ) \
extF80_le_quiet$(OBJ) \
extF80_lt_quiet$(OBJ) \
extF80_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128_to_ui32$(OBJ) \
f128_to_ui64$(OBJ) \
f128_to_i32$(OBJ) \
f128_to_i64$(OBJ) \
f128_to_ui32_r_minMag$(OBJ) \
f128_to_ui64_r_minMag$(OBJ) \
f128_to_i32_r_minMag$(OBJ) \
f128_to_i64_r_minMag$(OBJ) \
f128_to_f16$(OBJ) \
f128_to_f32$(OBJ) \
f128_to_extF80$(OBJ) \
f128_to_f64$(OBJ) \
f128_roundToInt$(OBJ) \
f128_add$(OBJ) \
f128_sub$(OBJ) \
f128_mul$(OBJ) \
f128_mulAdd$(OBJ) \
f128_div$(OBJ) \
f128_rem$(OBJ) \
f128_sqrt$(OBJ) \
f128_eq$(OBJ) \
f128_le$(OBJ) \
f128_lt$(OBJ) \
f128_eq_signaling$(OBJ) \
f128_le_quiet$(OBJ) \
f128_lt_quiet$(OBJ) \
f128_isSignalingNaN$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)

111
softfloat/build/Linux-x86_64-GCC/platform.h
View File

@ -1,56 +1,55 @@
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
//#define INLINE inline
#define INLINE static
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC__
#define SOFTFLOAT_BUILTIN_CLZ 1
#define SOFTFLOAT_INTRINSIC_INT128 1
#endif
#include "opts-GCC.h"
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
//#define INLINE inline
#define INLINE static
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define SOFTFLOAT_BUILTIN_CLZ 1
#define SOFTFLOAT_INTRINSIC_INT128 1
#include "opts-GCC.h"

650
softfloat/build/Win32-MinGW/Makefile
View File

@ -1,325 +1,325 @@
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= 8086
SOFTFLOAT_OPTS ?= \
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-DSOFTFLOAT_FAST_DIV64TO32
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
$(C_INCLUDES) -O2 -o $@
MAKELIB = ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS =
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_compare96M$(OBJ) \
s_compare128M$(OBJ) \
s_shortShiftLeft64To96M$(OBJ) \
s_shortShiftLeftM$(OBJ) \
s_shiftLeftM$(OBJ) \
s_shortShiftRightM$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJamM$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJamM$(OBJ) \
s_shiftRightM$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_addM$(OBJ) \
s_addCarryM$(OBJ) \
s_addComplCarryM$(OBJ) \
s_negXM$(OBJ) \
s_sub1XM$(OBJ) \
s_subM$(OBJ) \
s_mul64To128M$(OBJ) \
s_mul128MTo256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
s_remStepMBy32$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80MToCommonNaN$(OBJ) \
s_commonNaNToExtF80M$(OBJ) \
s_propagateNaNExtF80M$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128MToCommonNaN$(OBJ) \
s_commonNaNToF128M$(OBJ) \
s_propagateNaNF128M$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundMToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundMToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_tryPropagateNaNExtF80M$(OBJ) \
s_invalidExtF80M$(OBJ) \
s_normExtF80SigM$(OBJ) \
s_roundPackMToExtF80M$(OBJ) \
s_normRoundPackMToExtF80M$(OBJ) \
s_addExtF80M$(OBJ) \
s_compareNonnormExtF80M$(OBJ) \
s_isNaNF128M$(OBJ) \
s_tryPropagateNaNF128M$(OBJ) \
s_invalidF128M$(OBJ) \
s_shiftNormSigF128M$(OBJ) \
s_roundPackMToF128M$(OBJ) \
s_normRoundPackMToF128M$(OBJ) \
s_addF128M$(OBJ) \
s_mulAddF128M$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= 8086
SOFTFLOAT_OPTS ?= \
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-DSOFTFLOAT_FAST_DIV64TO32
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
$(C_INCLUDES) -O2 -o $@
MAKELIB = ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS =
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_compare96M$(OBJ) \
s_compare128M$(OBJ) \
s_shortShiftLeft64To96M$(OBJ) \
s_shortShiftLeftM$(OBJ) \
s_shiftLeftM$(OBJ) \
s_shortShiftRightM$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJamM$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJamM$(OBJ) \
s_shiftRightM$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_addM$(OBJ) \
s_addCarryM$(OBJ) \
s_addComplCarryM$(OBJ) \
s_negXM$(OBJ) \
s_sub1XM$(OBJ) \
s_subM$(OBJ) \
s_mul64To128M$(OBJ) \
s_mul128MTo256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
s_remStepMBy32$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80MToCommonNaN$(OBJ) \
s_commonNaNToExtF80M$(OBJ) \
s_propagateNaNExtF80M$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128MToCommonNaN$(OBJ) \
s_commonNaNToF128M$(OBJ) \
s_propagateNaNF128M$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundMToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundMToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_tryPropagateNaNExtF80M$(OBJ) \
s_invalidExtF80M$(OBJ) \
s_normExtF80SigM$(OBJ) \
s_roundPackMToExtF80M$(OBJ) \
s_normRoundPackMToExtF80M$(OBJ) \
s_addExtF80M$(OBJ) \
s_compareNonnormExtF80M$(OBJ) \
s_isNaNF128M$(OBJ) \
s_tryPropagateNaNF128M$(OBJ) \
s_invalidF128M$(OBJ) \
s_shiftNormSigF128M$(OBJ) \
s_roundPackMToF128M$(OBJ) \
s_normRoundPackMToF128M$(OBJ) \
s_addF128M$(OBJ) \
s_mulAddF128M$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)

106
softfloat/build/Win32-MinGW/platform.h
View File

@ -1,53 +1,53 @@
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
#define INLINE inline
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define SOFTFLOAT_BUILTIN_CLZ 1
#include "opts-GCC.h"
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
#define INLINE inline
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define SOFTFLOAT_BUILTIN_CLZ 1
#include "opts-GCC.h"

650
softfloat/build/Win32-SSE2-MinGW/Makefile
View File

@ -1,325 +1,325 @@
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= 8086-SSE
SOFTFLOAT_OPTS ?= \
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-DSOFTFLOAT_FAST_DIV64TO32
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
$(C_INCLUDES) -O2 -o $@
MAKELIB = ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS =
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_compare96M$(OBJ) \
s_compare128M$(OBJ) \
s_shortShiftLeft64To96M$(OBJ) \
s_shortShiftLeftM$(OBJ) \
s_shiftLeftM$(OBJ) \
s_shortShiftRightM$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJamM$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJamM$(OBJ) \
s_shiftRightM$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_addM$(OBJ) \
s_addCarryM$(OBJ) \
s_addComplCarryM$(OBJ) \
s_negXM$(OBJ) \
s_sub1XM$(OBJ) \
s_subM$(OBJ) \
s_mul64To128M$(OBJ) \
s_mul128MTo256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
s_remStepMBy32$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80MToCommonNaN$(OBJ) \
s_commonNaNToExtF80M$(OBJ) \
s_propagateNaNExtF80M$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128MToCommonNaN$(OBJ) \
s_commonNaNToF128M$(OBJ) \
s_propagateNaNF128M$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundMToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundMToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_tryPropagateNaNExtF80M$(OBJ) \
s_invalidExtF80M$(OBJ) \
s_normExtF80SigM$(OBJ) \
s_roundPackMToExtF80M$(OBJ) \
s_normRoundPackMToExtF80M$(OBJ) \
s_addExtF80M$(OBJ) \
s_compareNonnormExtF80M$(OBJ) \
s_isNaNF128M$(OBJ) \
s_tryPropagateNaNF128M$(OBJ) \
s_invalidF128M$(OBJ) \
s_shiftNormSigF128M$(OBJ) \
s_roundPackMToF128M$(OBJ) \
s_normRoundPackMToF128M$(OBJ) \
s_addF128M$(OBJ) \
s_mulAddF128M$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= 8086-SSE
SOFTFLOAT_OPTS ?= \
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-DSOFTFLOAT_FAST_DIV64TO32
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
$(C_INCLUDES) -O2 -o $@
MAKELIB = ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS =
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_compare96M$(OBJ) \
s_compare128M$(OBJ) \
s_shortShiftLeft64To96M$(OBJ) \
s_shortShiftLeftM$(OBJ) \
s_shiftLeftM$(OBJ) \
s_shortShiftRightM$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJamM$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJamM$(OBJ) \
s_shiftRightM$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_addM$(OBJ) \
s_addCarryM$(OBJ) \
s_addComplCarryM$(OBJ) \
s_negXM$(OBJ) \
s_sub1XM$(OBJ) \
s_subM$(OBJ) \
s_mul64To128M$(OBJ) \
s_mul128MTo256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
s_remStepMBy32$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80MToCommonNaN$(OBJ) \
s_commonNaNToExtF80M$(OBJ) \
s_propagateNaNExtF80M$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128MToCommonNaN$(OBJ) \
s_commonNaNToF128M$(OBJ) \
s_propagateNaNF128M$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundMToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundMToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_tryPropagateNaNExtF80M$(OBJ) \
s_invalidExtF80M$(OBJ) \
s_normExtF80SigM$(OBJ) \
s_roundPackMToExtF80M$(OBJ) \
s_normRoundPackMToExtF80M$(OBJ) \
s_addExtF80M$(OBJ) \
s_compareNonnormExtF80M$(OBJ) \
s_isNaNF128M$(OBJ) \
s_tryPropagateNaNF128M$(OBJ) \
s_invalidF128M$(OBJ) \
s_shiftNormSigF128M$(OBJ) \
s_roundPackMToF128M$(OBJ) \
s_normRoundPackMToF128M$(OBJ) \
s_addF128M$(OBJ) \
s_mulAddF128M$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)

106
softfloat/build/Win32-SSE2-MinGW/platform.h
View File

@ -1,53 +1,53 @@
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
#define INLINE inline
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define SOFTFLOAT_BUILTIN_CLZ 1
#include "opts-GCC.h"
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
#define INLINE inline
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define SOFTFLOAT_BUILTIN_CLZ 1
#include "opts-GCC.h"

780
softfloat/build/Win64-MinGW-w64/Makefile
View File

@ -1,390 +1,390 @@
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= 8086-SSE
SOFTFLOAT_OPTS ?= \
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-DSOFTFLOAT_FAST_DIV64TO32
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
x86_64-w64-mingw32-gcc -c -Werror-implicit-function-declaration \
-DSOFTFLOAT_FAST_INT64 $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
MAKELIB = x86_64-w64-mingw32-ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_eq128$(OBJ) \
s_le128$(OBJ) \
s_lt128$(OBJ) \
s_shortShiftLeft128$(OBJ) \
s_shortShiftRight128$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJam64Extra$(OBJ) \
s_shortShiftRightJam128$(OBJ) \
s_shortShiftRightJam128Extra$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJam64Extra$(OBJ) \
s_shiftRightJam128$(OBJ) \
s_shiftRightJam128Extra$(OBJ) \
s_shiftRightJam256M$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_add128$(OBJ) \
s_add256M$(OBJ) \
s_sub128$(OBJ) \
s_sub256M$(OBJ) \
s_mul64ByShifted32To128$(OBJ) \
s_mul64To128$(OBJ) \
s_mul128By32$(OBJ) \
s_mul128To256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80UIToCommonNaN$(OBJ) \
s_commonNaNToExtF80UI$(OBJ) \
s_propagateNaNExtF80UI$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128UIToCommonNaN$(OBJ) \
s_commonNaNToF128UI$(OBJ) \
s_propagateNaNF128UI$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_normSubnormalExtF80Sig$(OBJ) \
s_roundPackToExtF80$(OBJ) \
s_normRoundPackToExtF80$(OBJ) \
s_addMagsExtF80$(OBJ) \
s_subMagsExtF80$(OBJ) \
s_normSubnormalF128Sig$(OBJ) \
s_roundPackToF128$(OBJ) \
s_normRoundPackToF128$(OBJ) \
s_addMagsF128$(OBJ) \
s_subMagsF128$(OBJ) \
s_mulAddF128$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80_to_ui32$(OBJ) \
extF80_to_ui64$(OBJ) \
extF80_to_i32$(OBJ) \
extF80_to_i64$(OBJ) \
extF80_to_ui32_r_minMag$(OBJ) \
extF80_to_ui64_r_minMag$(OBJ) \
extF80_to_i32_r_minMag$(OBJ) \
extF80_to_i64_r_minMag$(OBJ) \
extF80_to_f16$(OBJ) \
extF80_to_f32$(OBJ) \
extF80_to_f64$(OBJ) \
extF80_to_f128$(OBJ) \
extF80_roundToInt$(OBJ) \
extF80_add$(OBJ) \
extF80_sub$(OBJ) \
extF80_mul$(OBJ) \
extF80_div$(OBJ) \
extF80_rem$(OBJ) \
extF80_sqrt$(OBJ) \
extF80_eq$(OBJ) \
extF80_le$(OBJ) \
extF80_lt$(OBJ) \
extF80_eq_signaling$(OBJ) \
extF80_le_quiet$(OBJ) \
extF80_lt_quiet$(OBJ) \
extF80_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128_to_ui32$(OBJ) \
f128_to_ui64$(OBJ) \
f128_to_i32$(OBJ) \
f128_to_i64$(OBJ) \
f128_to_ui32_r_minMag$(OBJ) \
f128_to_ui64_r_minMag$(OBJ) \
f128_to_i32_r_minMag$(OBJ) \
f128_to_i64_r_minMag$(OBJ) \
f128_to_f16$(OBJ) \
f128_to_f32$(OBJ) \
f128_to_extF80$(OBJ) \
f128_to_f64$(OBJ) \
f128_roundToInt$(OBJ) \
f128_add$(OBJ) \
f128_sub$(OBJ) \
f128_mul$(OBJ) \
f128_mulAdd$(OBJ) \
f128_div$(OBJ) \
f128_rem$(OBJ) \
f128_sqrt$(OBJ) \
f128_eq$(OBJ) \
f128_le$(OBJ) \
f128_lt$(OBJ) \
f128_eq_signaling$(OBJ) \
f128_le_quiet$(OBJ) \
f128_lt_quiet$(OBJ) \
f128_isSignalingNaN$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)
#=============================================================================
#
# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
# Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
SOURCE_DIR ?= ../../source
SPECIALIZE_TYPE ?= 8086-SSE
SOFTFLOAT_OPTS ?= \
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-DSOFTFLOAT_FAST_DIV64TO32
DELETE = rm -f
C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
COMPILE_C = \
x86_64-w64-mingw32-gcc -c -Werror-implicit-function-declaration \
-DSOFTFLOAT_FAST_INT64 $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
MAKELIB = x86_64-w64-mingw32-ar crs $@
OBJ = .o
LIB = .a
OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_eq128$(OBJ) \
s_le128$(OBJ) \
s_lt128$(OBJ) \
s_shortShiftLeft128$(OBJ) \
s_shortShiftRight128$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJam64Extra$(OBJ) \
s_shortShiftRightJam128$(OBJ) \
s_shortShiftRightJam128Extra$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJam64Extra$(OBJ) \
s_shiftRightJam128$(OBJ) \
s_shiftRightJam128Extra$(OBJ) \
s_shiftRightJam256M$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_add128$(OBJ) \
s_add256M$(OBJ) \
s_sub128$(OBJ) \
s_sub256M$(OBJ) \
s_mul64ByShifted32To128$(OBJ) \
s_mul64To128$(OBJ) \
s_mul128By32$(OBJ) \
s_mul128To256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80UIToCommonNaN$(OBJ) \
s_commonNaNToExtF80UI$(OBJ) \
s_propagateNaNExtF80UI$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128UIToCommonNaN$(OBJ) \
s_commonNaNToF128UI$(OBJ) \
s_propagateNaNF128UI$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_normSubnormalExtF80Sig$(OBJ) \
s_roundPackToExtF80$(OBJ) \
s_normRoundPackToExtF80$(OBJ) \
s_addMagsExtF80$(OBJ) \
s_subMagsExtF80$(OBJ) \
s_normSubnormalF128Sig$(OBJ) \
s_roundPackToF128$(OBJ) \
s_normRoundPackToF128$(OBJ) \
s_addMagsF128$(OBJ) \
s_subMagsF128$(OBJ) \
s_mulAddF128$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80_to_ui32$(OBJ) \
extF80_to_ui64$(OBJ) \
extF80_to_i32$(OBJ) \
extF80_to_i64$(OBJ) \
extF80_to_ui32_r_minMag$(OBJ) \
extF80_to_ui64_r_minMag$(OBJ) \
extF80_to_i32_r_minMag$(OBJ) \
extF80_to_i64_r_minMag$(OBJ) \
extF80_to_f16$(OBJ) \
extF80_to_f32$(OBJ) \
extF80_to_f64$(OBJ) \
extF80_to_f128$(OBJ) \
extF80_roundToInt$(OBJ) \
extF80_add$(OBJ) \
extF80_sub$(OBJ) \
extF80_mul$(OBJ) \
extF80_div$(OBJ) \
extF80_rem$(OBJ) \
extF80_sqrt$(OBJ) \
extF80_eq$(OBJ) \
extF80_le$(OBJ) \
extF80_lt$(OBJ) \
extF80_eq_signaling$(OBJ) \
extF80_le_quiet$(OBJ) \
extF80_lt_quiet$(OBJ) \
extF80_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128_to_ui32$(OBJ) \
f128_to_ui64$(OBJ) \
f128_to_i32$(OBJ) \
f128_to_i64$(OBJ) \
f128_to_ui32_r_minMag$(OBJ) \
f128_to_ui64_r_minMag$(OBJ) \
f128_to_i32_r_minMag$(OBJ) \
f128_to_i64_r_minMag$(OBJ) \
f128_to_f16$(OBJ) \
f128_to_f32$(OBJ) \
f128_to_extF80$(OBJ) \
f128_to_f64$(OBJ) \
f128_roundToInt$(OBJ) \
f128_add$(OBJ) \
f128_sub$(OBJ) \
f128_mul$(OBJ) \
f128_mulAdd$(OBJ) \
f128_div$(OBJ) \
f128_rem$(OBJ) \
f128_sqrt$(OBJ) \
f128_eq$(OBJ) \
f128_le$(OBJ) \
f128_lt$(OBJ) \
f128_eq_signaling$(OBJ) \
f128_le_quiet$(OBJ) \
f128_lt_quiet$(OBJ) \
f128_isSignalingNaN$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)

108
softfloat/build/Win64-MinGW-w64/platform.h
View File

@ -1,54 +1,54 @@
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
#define INLINE inline
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define SOFTFLOAT_BUILTIN_CLZ 1
#define SOFTFLOAT_INTRINSIC_INT128 1
#include "opts-GCC.h"
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#ifdef __GNUC_STDC_INLINE__
#define INLINE inline
#else
#define INLINE extern inline
#endif
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
#define SOFTFLOAT_BUILTIN_CLZ 1
#define SOFTFLOAT_INTRINSIC_INT128 1
#include "opts-GCC.h"

787
softfloat/build/template-FAST_INT64/Makefile
View File

@ -1,396 +1,391 @@
#=============================================================================
#
# This Makefile template is part of the SoftFloat IEEE Floating-Point
# Arithmetic Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
# Edit lines marked with `==>'. See "SoftFloat-source.html".
==> SOURCE_DIR ?= ../../source
==> SPECIALIZE_TYPE ?= 8086
==> SOFTFLOAT_OPTS ?= \
==> -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
==> -DSOFTFLOAT_FAST_DIV64TO32
==> DELETE = rm -f
==> C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
==> COMPILE_C = \
==> cc -c -DSOFTFLOAT_FAST_INT64 $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
==> MAKELIB = ar crs $@
==> OBJ = .o
==> LIB = .a
==> OTHER_HEADERS =
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_eq128$(OBJ) \
s_le128$(OBJ) \
s_lt128$(OBJ) \
s_shortShiftLeft128$(OBJ) \
s_shortShiftRight128$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJam64Extra$(OBJ) \
s_shortShiftRightJam128$(OBJ) \
s_shortShiftRightJam128Extra$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJam64Extra$(OBJ) \
s_shiftRightJam128$(OBJ) \
s_shiftRightJam128Extra$(OBJ) \
s_shiftRightJam256M$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_add128$(OBJ) \
s_add256M$(OBJ) \
s_sub128$(OBJ) \
s_sub256M$(OBJ) \
s_mul64ByShifted32To128$(OBJ) \
s_mul64To128$(OBJ) \
s_mul128By32$(OBJ) \
s_mul128To256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80UIToCommonNaN$(OBJ) \
s_commonNaNToExtF80UI$(OBJ) \
s_propagateNaNExtF80UI$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128UIToCommonNaN$(OBJ) \
s_commonNaNToF128UI$(OBJ) \
s_propagateNaNF128UI$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundToI64$(OBJ) \
s_normSubnormalBF16Sig$(OBJ) \
s_roundPackToBF16$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_normSubnormalExtF80Sig$(OBJ) \
s_roundPackToExtF80$(OBJ) \
s_normRoundPackToExtF80$(OBJ) \
s_addMagsExtF80$(OBJ) \
s_subMagsExtF80$(OBJ) \
s_normSubnormalF128Sig$(OBJ) \
s_roundPackToF128$(OBJ) \
s_normRoundPackToF128$(OBJ) \
s_addMagsF128$(OBJ) \
s_subMagsF128$(OBJ) \
s_mulAddF128$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128$(OBJ) \
i64_to_f128M$(OBJ) \
bf16_isSignalingNaN$(OBJ) \
bf16_to_f32$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_bf16$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80_to_ui32$(OBJ) \
extF80_to_ui64$(OBJ) \
extF80_to_i32$(OBJ) \
extF80_to_i64$(OBJ) \
extF80_to_ui32_r_minMag$(OBJ) \
extF80_to_ui64_r_minMag$(OBJ) \
extF80_to_i32_r_minMag$(OBJ) \
extF80_to_i64_r_minMag$(OBJ) \
extF80_to_f16$(OBJ) \
extF80_to_f32$(OBJ) \
extF80_to_f64$(OBJ) \
extF80_to_f128$(OBJ) \
extF80_roundToInt$(OBJ) \
extF80_add$(OBJ) \
extF80_sub$(OBJ) \
extF80_mul$(OBJ) \
extF80_div$(OBJ) \
extF80_rem$(OBJ) \
extF80_sqrt$(OBJ) \
extF80_eq$(OBJ) \
extF80_le$(OBJ) \
extF80_lt$(OBJ) \
extF80_eq_signaling$(OBJ) \
extF80_le_quiet$(OBJ) \
extF80_lt_quiet$(OBJ) \
extF80_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128_to_ui32$(OBJ) \
f128_to_ui64$(OBJ) \
f128_to_i32$(OBJ) \
f128_to_i64$(OBJ) \
f128_to_ui32_r_minMag$(OBJ) \
f128_to_ui64_r_minMag$(OBJ) \
f128_to_i32_r_minMag$(OBJ) \
f128_to_i64_r_minMag$(OBJ) \
f128_to_f16$(OBJ) \
f128_to_f32$(OBJ) \
f128_to_extF80$(OBJ) \
f128_to_f64$(OBJ) \
f128_roundToInt$(OBJ) \
f128_add$(OBJ) \
f128_sub$(OBJ) \
f128_mul$(OBJ) \
f128_mulAdd$(OBJ) \
f128_div$(OBJ) \
f128_rem$(OBJ) \
f128_sqrt$(OBJ) \
f128_eq$(OBJ) \
f128_le$(OBJ) \
f128_lt$(OBJ) \
f128_eq_signaling$(OBJ) \
f128_le_quiet$(OBJ) \
f128_lt_quiet$(OBJ) \
f128_isSignalingNaN$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)
#=============================================================================
#
# This Makefile template is part of the SoftFloat IEEE Floating-Point
# Arithmetic Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
# Edit lines marked with `==>'. See "SoftFloat-source.html".
==> SOURCE_DIR ?= ../../source
==> SPECIALIZE_TYPE ?= 8086
==> SOFTFLOAT_OPTS ?= \
==> -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
==> -DSOFTFLOAT_FAST_DIV64TO32
==> DELETE = rm -f
==> C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
==> COMPILE_C = \
==> cc -c -DSOFTFLOAT_FAST_INT64 $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
==> MAKELIB = ar crs $@
==> OBJ = .o
==> LIB = .a
==> OTHER_HEADERS =
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_eq128$(OBJ) \
s_le128$(OBJ) \
s_lt128$(OBJ) \
s_shortShiftLeft128$(OBJ) \
s_shortShiftRight128$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJam64Extra$(OBJ) \
s_shortShiftRightJam128$(OBJ) \
s_shortShiftRightJam128Extra$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJam64Extra$(OBJ) \
s_shiftRightJam128$(OBJ) \
s_shiftRightJam128Extra$(OBJ) \
s_shiftRightJam256M$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_add128$(OBJ) \
s_add256M$(OBJ) \
s_sub128$(OBJ) \
s_sub256M$(OBJ) \
s_mul64ByShifted32To128$(OBJ) \
s_mul64To128$(OBJ) \
s_mul128By32$(OBJ) \
s_mul128To256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80UIToCommonNaN$(OBJ) \
s_commonNaNToExtF80UI$(OBJ) \
s_propagateNaNExtF80UI$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128UIToCommonNaN$(OBJ) \
s_commonNaNToF128UI$(OBJ) \
s_propagateNaNF128UI$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_normSubnormalExtF80Sig$(OBJ) \
s_roundPackToExtF80$(OBJ) \
s_normRoundPackToExtF80$(OBJ) \
s_addMagsExtF80$(OBJ) \
s_subMagsExtF80$(OBJ) \
s_normSubnormalF128Sig$(OBJ) \
s_roundPackToF128$(OBJ) \
s_normRoundPackToF128$(OBJ) \
s_addMagsF128$(OBJ) \
s_subMagsF128$(OBJ) \
s_mulAddF128$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80_to_ui32$(OBJ) \
extF80_to_ui64$(OBJ) \
extF80_to_i32$(OBJ) \
extF80_to_i64$(OBJ) \
extF80_to_ui32_r_minMag$(OBJ) \
extF80_to_ui64_r_minMag$(OBJ) \
extF80_to_i32_r_minMag$(OBJ) \
extF80_to_i64_r_minMag$(OBJ) \
extF80_to_f16$(OBJ) \
extF80_to_f32$(OBJ) \
extF80_to_f64$(OBJ) \
extF80_to_f128$(OBJ) \
extF80_roundToInt$(OBJ) \
extF80_add$(OBJ) \
extF80_sub$(OBJ) \
extF80_mul$(OBJ) \
extF80_div$(OBJ) \
extF80_rem$(OBJ) \
extF80_sqrt$(OBJ) \
extF80_eq$(OBJ) \
extF80_le$(OBJ) \
extF80_lt$(OBJ) \
extF80_eq_signaling$(OBJ) \
extF80_le_quiet$(OBJ) \
extF80_lt_quiet$(OBJ) \
extF80_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128_to_ui32$(OBJ) \
f128_to_ui64$(OBJ) \
f128_to_i32$(OBJ) \
f128_to_i64$(OBJ) \
f128_to_ui32_r_minMag$(OBJ) \
f128_to_ui64_r_minMag$(OBJ) \
f128_to_i32_r_minMag$(OBJ) \
f128_to_i64_r_minMag$(OBJ) \
f128_to_f16$(OBJ) \
f128_to_f32$(OBJ) \
f128_to_extF80$(OBJ) \
f128_to_f64$(OBJ) \
f128_roundToInt$(OBJ) \
f128_add$(OBJ) \
f128_sub$(OBJ) \
f128_mul$(OBJ) \
f128_mulAdd$(OBJ) \
f128_div$(OBJ) \
f128_rem$(OBJ) \
f128_sqrt$(OBJ) \
f128_eq$(OBJ) \
f128_le$(OBJ) \
f128_lt$(OBJ) \
f128_eq_signaling$(OBJ) \
f128_le_quiet$(OBJ) \
f128_lt_quiet$(OBJ) \
f128_isSignalingNaN$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)

100
softfloat/build/template-FAST_INT64/platform.h
View File

@ -1,50 +1,50 @@
/*============================================================================
This C header template is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
// Edit lines marked with `==>'. See "SoftFloat-source.html".
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
==> #define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
==> #define INLINE inline
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
==> #define THREAD_LOCAL _Thread_local
/*============================================================================
This C header template is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
// Edit lines marked with `==>'. See "SoftFloat-source.html".
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
==> #define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
==> #define INLINE inline
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
==> #define THREAD_LOCAL _Thread_local

650
softfloat/build/template-not-FAST_INT64/Makefile
View File

@ -1,325 +1,325 @@
#=============================================================================
#
# This Makefile template is part of the SoftFloat IEEE Floating-Point
# Arithmetic Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
# Edit lines marked with `==>'. See "SoftFloat-source.html".
==> SOURCE_DIR ?= ../../source
==> SPECIALIZE_TYPE ?= 8086
==> SOFTFLOAT_OPTS ?= \
==> -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
==> -DSOFTFLOAT_FAST_DIV64TO32
==> DELETE = rm -f
==> C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
==> COMPILE_C = cc -c $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
==> MAKELIB = ar crs $@
==> OBJ = .o
==> LIB = .a
==> OTHER_HEADERS =
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_compare96M$(OBJ) \
s_compare128M$(OBJ) \
s_shortShiftLeft64To96M$(OBJ) \
s_shortShiftLeftM$(OBJ) \
s_shiftLeftM$(OBJ) \
s_shortShiftRightM$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJamM$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJamM$(OBJ) \
s_shiftRightM$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_addM$(OBJ) \
s_addCarryM$(OBJ) \
s_addComplCarryM$(OBJ) \
s_negXM$(OBJ) \
s_sub1XM$(OBJ) \
s_subM$(OBJ) \
s_mul64To128M$(OBJ) \
s_mul128MTo256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
s_remStepMBy32$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80MToCommonNaN$(OBJ) \
s_commonNaNToExtF80M$(OBJ) \
s_propagateNaNExtF80M$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128MToCommonNaN$(OBJ) \
s_commonNaNToF128M$(OBJ) \
s_propagateNaNF128M$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundMToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundMToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_tryPropagateNaNExtF80M$(OBJ) \
s_invalidExtF80M$(OBJ) \
s_normExtF80SigM$(OBJ) \
s_roundPackMToExtF80M$(OBJ) \
s_normRoundPackMToExtF80M$(OBJ) \
s_addExtF80M$(OBJ) \
s_compareNonnormExtF80M$(OBJ) \
s_isNaNF128M$(OBJ) \
s_tryPropagateNaNF128M$(OBJ) \
s_invalidF128M$(OBJ) \
s_shiftNormSigF128M$(OBJ) \
s_roundPackMToF128M$(OBJ) \
s_normRoundPackMToF128M$(OBJ) \
s_addF128M$(OBJ) \
s_mulAddF128M$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)
#=============================================================================
#
# This Makefile template is part of the SoftFloat IEEE Floating-Point
# Arithmetic Package, Release 3e, by John R. Hauser.
#
# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
# University of California. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions, and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions, and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the University nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#=============================================================================
# Edit lines marked with `==>'. See "SoftFloat-source.html".
==> SOURCE_DIR ?= ../../source
==> SPECIALIZE_TYPE ?= 8086
==> SOFTFLOAT_OPTS ?= \
==> -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
==> -DSOFTFLOAT_FAST_DIV64TO32
==> DELETE = rm -f
==> C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
==> COMPILE_C = cc -c $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
==> MAKELIB = ar crs $@
==> OBJ = .o
==> LIB = .a
==> OTHER_HEADERS =
.PHONY: all
all: softfloat$(LIB)
OBJS_PRIMITIVES = \
s_compare96M$(OBJ) \
s_compare128M$(OBJ) \
s_shortShiftLeft64To96M$(OBJ) \
s_shortShiftLeftM$(OBJ) \
s_shiftLeftM$(OBJ) \
s_shortShiftRightM$(OBJ) \
s_shortShiftRightJam64$(OBJ) \
s_shortShiftRightJamM$(OBJ) \
s_shiftRightJam32$(OBJ) \
s_shiftRightJam64$(OBJ) \
s_shiftRightJamM$(OBJ) \
s_shiftRightM$(OBJ) \
s_countLeadingZeros8$(OBJ) \
s_countLeadingZeros16$(OBJ) \
s_countLeadingZeros32$(OBJ) \
s_countLeadingZeros64$(OBJ) \
s_addM$(OBJ) \
s_addCarryM$(OBJ) \
s_addComplCarryM$(OBJ) \
s_negXM$(OBJ) \
s_sub1XM$(OBJ) \
s_subM$(OBJ) \
s_mul64To128M$(OBJ) \
s_mul128MTo256M$(OBJ) \
s_approxRecip_1Ks$(OBJ) \
s_approxRecip32_1$(OBJ) \
s_approxRecipSqrt_1Ks$(OBJ) \
s_approxRecipSqrt32_1$(OBJ) \
s_remStepMBy32$(OBJ) \
OBJS_SPECIALIZE = \
softfloat_raiseFlags$(OBJ) \
s_f16UIToCommonNaN$(OBJ) \
s_commonNaNToF16UI$(OBJ) \
s_propagateNaNF16UI$(OBJ) \
s_f32UIToCommonNaN$(OBJ) \
s_commonNaNToF32UI$(OBJ) \
s_propagateNaNF32UI$(OBJ) \
s_f64UIToCommonNaN$(OBJ) \
s_commonNaNToF64UI$(OBJ) \
s_propagateNaNF64UI$(OBJ) \
extF80M_isSignalingNaN$(OBJ) \
s_extF80MToCommonNaN$(OBJ) \
s_commonNaNToExtF80M$(OBJ) \
s_propagateNaNExtF80M$(OBJ) \
f128M_isSignalingNaN$(OBJ) \
s_f128MToCommonNaN$(OBJ) \
s_commonNaNToF128M$(OBJ) \
s_propagateNaNF128M$(OBJ) \
OBJS_OTHERS = \
s_roundToUI32$(OBJ) \
s_roundMToUI64$(OBJ) \
s_roundToI32$(OBJ) \
s_roundMToI64$(OBJ) \
s_normSubnormalF16Sig$(OBJ) \
s_roundPackToF16$(OBJ) \
s_normRoundPackToF16$(OBJ) \
s_addMagsF16$(OBJ) \
s_subMagsF16$(OBJ) \
s_mulAddF16$(OBJ) \
s_normSubnormalF32Sig$(OBJ) \
s_roundPackToF32$(OBJ) \
s_normRoundPackToF32$(OBJ) \
s_addMagsF32$(OBJ) \
s_subMagsF32$(OBJ) \
s_mulAddF32$(OBJ) \
s_normSubnormalF64Sig$(OBJ) \
s_roundPackToF64$(OBJ) \
s_normRoundPackToF64$(OBJ) \
s_addMagsF64$(OBJ) \
s_subMagsF64$(OBJ) \
s_mulAddF64$(OBJ) \
s_tryPropagateNaNExtF80M$(OBJ) \
s_invalidExtF80M$(OBJ) \
s_normExtF80SigM$(OBJ) \
s_roundPackMToExtF80M$(OBJ) \
s_normRoundPackMToExtF80M$(OBJ) \
s_addExtF80M$(OBJ) \
s_compareNonnormExtF80M$(OBJ) \
s_isNaNF128M$(OBJ) \
s_tryPropagateNaNF128M$(OBJ) \
s_invalidF128M$(OBJ) \
s_shiftNormSigF128M$(OBJ) \
s_roundPackMToF128M$(OBJ) \
s_normRoundPackMToF128M$(OBJ) \
s_addF128M$(OBJ) \
s_mulAddF128M$(OBJ) \
softfloat_state$(OBJ) \
ui32_to_f16$(OBJ) \
ui32_to_f32$(OBJ) \
ui32_to_f64$(OBJ) \
ui32_to_extF80M$(OBJ) \
ui32_to_f128M$(OBJ) \
ui64_to_f16$(OBJ) \
ui64_to_f32$(OBJ) \
ui64_to_f64$(OBJ) \
ui64_to_extF80M$(OBJ) \
ui64_to_f128M$(OBJ) \
i32_to_f16$(OBJ) \
i32_to_f32$(OBJ) \
i32_to_f64$(OBJ) \
i32_to_extF80M$(OBJ) \
i32_to_f128M$(OBJ) \
i64_to_f16$(OBJ) \
i64_to_f32$(OBJ) \
i64_to_f64$(OBJ) \
i64_to_extF80M$(OBJ) \
i64_to_f128M$(OBJ) \
f16_to_ui32$(OBJ) \
f16_to_ui64$(OBJ) \
f16_to_i32$(OBJ) \
f16_to_i64$(OBJ) \
f16_to_ui32_r_minMag$(OBJ) \
f16_to_ui64_r_minMag$(OBJ) \
f16_to_i32_r_minMag$(OBJ) \
f16_to_i64_r_minMag$(OBJ) \
f16_to_f32$(OBJ) \
f16_to_f64$(OBJ) \
f16_to_extF80M$(OBJ) \
f16_to_f128M$(OBJ) \
f16_roundToInt$(OBJ) \
f16_add$(OBJ) \
f16_sub$(OBJ) \
f16_mul$(OBJ) \
f16_mulAdd$(OBJ) \
f16_div$(OBJ) \
f16_rem$(OBJ) \
f16_sqrt$(OBJ) \
f16_eq$(OBJ) \
f16_le$(OBJ) \
f16_lt$(OBJ) \
f16_eq_signaling$(OBJ) \
f16_le_quiet$(OBJ) \
f16_lt_quiet$(OBJ) \
f16_isSignalingNaN$(OBJ) \
f32_to_ui32$(OBJ) \
f32_to_ui64$(OBJ) \
f32_to_i32$(OBJ) \
f32_to_i64$(OBJ) \
f32_to_ui32_r_minMag$(OBJ) \
f32_to_ui64_r_minMag$(OBJ) \
f32_to_i32_r_minMag$(OBJ) \
f32_to_i64_r_minMag$(OBJ) \
f32_to_f16$(OBJ) \
f32_to_f64$(OBJ) \
f32_to_extF80M$(OBJ) \
f32_to_f128M$(OBJ) \
f32_roundToInt$(OBJ) \
f32_add$(OBJ) \
f32_sub$(OBJ) \
f32_mul$(OBJ) \
f32_mulAdd$(OBJ) \
f32_div$(OBJ) \
f32_rem$(OBJ) \
f32_sqrt$(OBJ) \
f32_eq$(OBJ) \
f32_le$(OBJ) \
f32_lt$(OBJ) \
f32_eq_signaling$(OBJ) \
f32_le_quiet$(OBJ) \
f32_lt_quiet$(OBJ) \
f32_isSignalingNaN$(OBJ) \
f64_to_ui32$(OBJ) \
f64_to_ui64$(OBJ) \
f64_to_i32$(OBJ) \
f64_to_i64$(OBJ) \
f64_to_ui32_r_minMag$(OBJ) \
f64_to_ui64_r_minMag$(OBJ) \
f64_to_i32_r_minMag$(OBJ) \
f64_to_i64_r_minMag$(OBJ) \
f64_to_f16$(OBJ) \
f64_to_f32$(OBJ) \
f64_to_extF80M$(OBJ) \
f64_to_f128M$(OBJ) \
f64_roundToInt$(OBJ) \
f64_add$(OBJ) \
f64_sub$(OBJ) \
f64_mul$(OBJ) \
f64_mulAdd$(OBJ) \
f64_div$(OBJ) \
f64_rem$(OBJ) \
f64_sqrt$(OBJ) \
f64_eq$(OBJ) \
f64_le$(OBJ) \
f64_lt$(OBJ) \
f64_eq_signaling$(OBJ) \
f64_le_quiet$(OBJ) \
f64_lt_quiet$(OBJ) \
f64_isSignalingNaN$(OBJ) \
extF80M_to_ui32$(OBJ) \
extF80M_to_ui64$(OBJ) \
extF80M_to_i32$(OBJ) \
extF80M_to_i64$(OBJ) \
extF80M_to_ui32_r_minMag$(OBJ) \
extF80M_to_ui64_r_minMag$(OBJ) \
extF80M_to_i32_r_minMag$(OBJ) \
extF80M_to_i64_r_minMag$(OBJ) \
extF80M_to_f16$(OBJ) \
extF80M_to_f32$(OBJ) \
extF80M_to_f64$(OBJ) \
extF80M_to_f128M$(OBJ) \
extF80M_roundToInt$(OBJ) \
extF80M_add$(OBJ) \
extF80M_sub$(OBJ) \
extF80M_mul$(OBJ) \
extF80M_div$(OBJ) \
extF80M_rem$(OBJ) \
extF80M_sqrt$(OBJ) \
extF80M_eq$(OBJ) \
extF80M_le$(OBJ) \
extF80M_lt$(OBJ) \
extF80M_eq_signaling$(OBJ) \
extF80M_le_quiet$(OBJ) \
extF80M_lt_quiet$(OBJ) \
f128M_to_ui32$(OBJ) \
f128M_to_ui64$(OBJ) \
f128M_to_i32$(OBJ) \
f128M_to_i64$(OBJ) \
f128M_to_ui32_r_minMag$(OBJ) \
f128M_to_ui64_r_minMag$(OBJ) \
f128M_to_i32_r_minMag$(OBJ) \
f128M_to_i64_r_minMag$(OBJ) \
f128M_to_f16$(OBJ) \
f128M_to_f32$(OBJ) \
f128M_to_f64$(OBJ) \
f128M_to_extF80M$(OBJ) \
f128M_roundToInt$(OBJ) \
f128M_add$(OBJ) \
f128M_sub$(OBJ) \
f128M_mul$(OBJ) \
f128M_mulAdd$(OBJ) \
f128M_div$(OBJ) \
f128M_rem$(OBJ) \
f128M_sqrt$(OBJ) \
f128M_eq$(OBJ) \
f128M_le$(OBJ) \
f128M_lt$(OBJ) \
f128M_eq_signaling$(OBJ) \
f128M_le_quiet$(OBJ) \
f128M_lt_quiet$(OBJ) \
OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
$(OBJS_ALL): \
$(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
$(SOURCE_DIR)/include/primitives.h
$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
$(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
$(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
$(SOURCE_DIR)/include/softfloat.h
$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$*.c
$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
softfloat$(LIB): $(OBJS_ALL)
$(DELETE) $@
$(MAKELIB) $^
.PHONY: clean
clean:
$(DELETE) $(OBJS_ALL) softfloat$(LIB)

100
softfloat/build/template-not-FAST_INT64/platform.h
View File

@ -1,50 +1,50 @@
/*============================================================================
This C header template is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
// Edit lines marked with `==>'. See "SoftFloat-source.html".
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
==> #define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
==> #define INLINE inline
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
==> #define THREAD_LOCAL _Thread_local
/*============================================================================
This C header template is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
// Edit lines marked with `==>'. See "SoftFloat-source.html".
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
==> #define LITTLEENDIAN 1
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
==> #define INLINE inline
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
==> #define THREAD_LOCAL _Thread_local

516
softfloat/doc/SoftFloat-history.html
View File

@ -1,258 +1,258 @@
<HTML>
<HEAD>
<TITLE>Berkeley SoftFloat History</TITLE>
</HEAD>
<BODY>
<H1>History of Berkeley SoftFloat, to Release 3e</H1>
<P>
John R. Hauser<BR>
2018 January 20<BR>
</P>
<H3>Release 3e (2018 January)</H3>
<UL>
<LI>
Changed the default numeric code for optional rounding mode <CODE>odd</CODE>
(round to odd, also known as <EM>jamming</EM>) from 5 to 6.
<LI>
Modified the behavior of rounding mode <CODE>odd</CODE> when rounding to an
integer value (either conversion to an integer format or a
&lsquo;<CODE>roundToInt</CODE>&rsquo; function).
Previously, for those cases only, rounding mode <CODE>odd</CODE> acted the same
as rounding to minimum magnitude.
Now all operations are rounded consistently.
<LI>
Fixed some errors in the specialization code modeling Intel x86 floating-point,
specifically the integers returned on invalid operations and the propagation of
NaN payloads in a few rare cases.
<LI>
Added specialization code modeling ARM floating-point, conforming to VFPv2 or
later.
<LI>
Added an example target for ARM processors.
<LI>
Fixed a minor bug whereby function <CODE>f16_to_ui64</CODE> might return a
different integer than expected in the case that the floating-point operand is
negative.
<LI>
Added example target-specific optimization for GCC, employing GCC instrinsics
and support for <NOBR>128-bit</NOBR> integer arithmetic.
<LI>
Made other minor improvements.
</UL>
<H3>Release 3d (2017 August)</H3>
<UL>
<LI>
Fixed bugs in the square root functions for <NOBR>64-bit</NOBR>
double-precision, <NOBR>80-bit</NOBR> double-extended-precision, and
<NOBR>128-bit</NOBR> quadruple-precision.
For <NOBR>64-bit</NOBR> double-precision (<CODE>f64_sqrt</CODE>), the result
could sometimes be off by <NOBR>1 unit</NOBR> in the last place
(<NOBR>1 ulp</NOBR>) from what it should be.
For the larger formats, the square root could be wrong in a large portion of
the less-significant bits.
(A bug in <CODE>f128_sqrt</CODE> was first reported by Alexei Sibidanov.)
</UL>
<H3>Release 3c (2017 February)</H3>
<UL>
<LI>
Added optional rounding mode <CODE>odd</CODE> (round to odd, also known as
<EM>jamming</EM>).
<LI>
Corrected the documentation concerning non-canonical representations in
<NOBR>80-bit</NOBR> double-extended-precision.
</UL>
<H3>Release 3b (2016 July)</H3>
<UL>
<LI>
Implemented the common <NOBR>16-bit</NOBR> &ldquo;half-precision&rdquo;
floating-point format (<CODE>float16_t</CODE>).
<LI>
Made the integer values returned on invalid conversions to integer formats
be determined by the port-specific specialization instead of being the same for
all ports.
<LI>
Added preprocessor macro <CODE>THREAD_LOCAL</CODE> to allow the floating-point
state (modes and exception flags) to be made per-thread.
<LI>
Modified the provided Makefiles to allow some options to be overridden from the
<CODE>make</CODE> command.
<LI>
Made other minor improvements.
</UL>
<H3>Release 3a (2015 October)</H3>
<UL>
<LI>
Replaced the license text supplied by the University of California, Berkeley.
</UL>
<H3>Release 3 (2015 February)</H3>
<UL>
<LI>
Complete rewrite, funded by the University of California, Berkeley, and
consequently having a different use license than earlier releases.
Major changes included renaming most types and functions, upgrading some
algorithms, restructuring the source files, and making SoftFloat into a true
library.
<LI>
Added functions to convert between floating-point and unsigned integers, both
<NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR> (<CODE>uint32_t</CODE> and
<CODE>uint64_t</CODE>).
<LI>
Added functions for fused multiply-add, for all supported floating-point
formats except <NOBR>80-bit</NOBR> double-extended-precision.
<LI>
Added support for a fifth rounding mode, <CODE>near_maxMag</CODE> (round to
nearest, with ties to maximum magnitude, away from zero).
<LI>
Dropped the <CODE>timesoftfloat</CODE> program (now part of the Berkeley
TestFloat package).
</UL>
<H3>Release 2c (2015 January)</H3>
<UL>
<LI>
Fixed mistakes affecting some <NOBR>64-bit</NOBR> processors.
<LI>
Further improved the documentation and the wording for the legal restrictions
on using SoftFloat releases <NOBR>through 2c</NOBR> (not applicable to
<NOBR>Release 3</NOBR> or later).
</UL>
<H3>Release 2b (2002 May)</H3>
<UL>
<LI>
Made minor updates to the documentation, including improved wording for the
legal restrictions on using SoftFloat.
</UL>
<H3>Release 2a (1998 December)</H3>
<UL>
<LI>
Added functions to convert between <NOBR>64-bit</NOBR> integers
(<CODE>int64</CODE>) and all supported floating-point formats.
<LI>
Fixed a bug in all <NOBR>64-bit</NOBR>-version square root functions except
<CODE>float32_sqrt</CODE> that caused the result sometimes to be off by
<NOBR>1 unit</NOBR> in the last place (<NOBR>1 ulp</NOBR>) from what it should
be.
(Bug discovered by Paul Donahue.)
<LI>
Improved the Makefiles.
</UL>
<H3>Release 2 (1997 June)</H3>
<UL>
<LI>
Created the <NOBR>64-bit</NOBR> (<CODE>bits64</CODE>) version, adding the
<CODE>floatx80</CODE> and <CODE>float128</CODE> formats.
<LI>
Changed the source directory structure, splitting the sources into a
<CODE>bits32</CODE> and a <CODE>bits64</CODE> version.
Renamed <CODE>environment.h</CODE> to <CODE>milieu.h</CODE> to avoid confusion
with environment variables.
<LI>
Fixed a small error that caused <CODE>float64_round_to_int</CODE> often to
round the wrong way in nearest/even mode when the operand was between
2<SUP>20</SUP> and 2<SUP>21</SUP> and halfway between two integers.
</UL>
<H3>Release 1a (1996 July)</H3>
<UL>
<LI>
Corrected a mistake that caused borderline underflow cases not to raise the
underflow flag when they should have.
(Problem reported by Doug Priest.)
<LI>
Added the <CODE>float_detect_tininess</CODE> variable to control whether
tininess is detected before or after rounding.
</UL>
<H3>Release 1 (1996 July)</H3>
<UL>
<LI>
Original release, based on work done for the International Computer Science
Institute (ICSI) in Berkeley, California.
</UL>
</BODY>
<HTML>
<HEAD>
<TITLE>Berkeley SoftFloat History</TITLE>
</HEAD>
<BODY>
<H1>History of Berkeley SoftFloat, to Release 3e</H1>
<P>
John R. Hauser<BR>
2018 January 20<BR>
</P>
<H3>Release 3e (2018 January)</H3>
<UL>
<LI>
Changed the default numeric code for optional rounding mode <CODE>odd</CODE>
(round to odd, also known as <EM>jamming</EM>) from 5 to 6.
<LI>
Modified the behavior of rounding mode <CODE>odd</CODE> when rounding to an
integer value (either conversion to an integer format or a
&lsquo;<CODE>roundToInt</CODE>&rsquo; function).
Previously, for those cases only, rounding mode <CODE>odd</CODE> acted the same
as rounding to minimum magnitude.
Now all operations are rounded consistently.
<LI>
Fixed some errors in the specialization code modeling Intel x86 floating-point,
specifically the integers returned on invalid operations and the propagation of
NaN payloads in a few rare cases.
<LI>
Added specialization code modeling ARM floating-point, conforming to VFPv2 or
later.
<LI>
Added an example target for ARM processors.
<LI>
Fixed a minor bug whereby function <CODE>f16_to_ui64</CODE> might return a
different integer than expected in the case that the floating-point operand is
negative.
<LI>
Added example target-specific optimization for GCC, employing GCC instrinsics
and support for <NOBR>128-bit</NOBR> integer arithmetic.
<LI>
Made other minor improvements.
</UL>
<H3>Release 3d (2017 August)</H3>
<UL>
<LI>
Fixed bugs in the square root functions for <NOBR>64-bit</NOBR>
double-precision, <NOBR>80-bit</NOBR> double-extended-precision, and
<NOBR>128-bit</NOBR> quadruple-precision.
For <NOBR>64-bit</NOBR> double-precision (<CODE>f64_sqrt</CODE>), the result
could sometimes be off by <NOBR>1 unit</NOBR> in the last place
(<NOBR>1 ulp</NOBR>) from what it should be.
For the larger formats, the square root could be wrong in a large portion of
the less-significant bits.
(A bug in <CODE>f128_sqrt</CODE> was first reported by Alexei Sibidanov.)
</UL>
<H3>Release 3c (2017 February)</H3>
<UL>
<LI>
Added optional rounding mode <CODE>odd</CODE> (round to odd, also known as
<EM>jamming</EM>).
<LI>
Corrected the documentation concerning non-canonical representations in
<NOBR>80-bit</NOBR> double-extended-precision.
</UL>
<H3>Release 3b (2016 July)</H3>
<UL>
<LI>
Implemented the common <NOBR>16-bit</NOBR> &ldquo;half-precision&rdquo;
floating-point format (<CODE>float16_t</CODE>).
<LI>
Made the integer values returned on invalid conversions to integer formats
be determined by the port-specific specialization instead of being the same for
all ports.
<LI>
Added preprocessor macro <CODE>THREAD_LOCAL</CODE> to allow the floating-point
state (modes and exception flags) to be made per-thread.
<LI>
Modified the provided Makefiles to allow some options to be overridden from the
<CODE>make</CODE> command.
<LI>
Made other minor improvements.
</UL>
<H3>Release 3a (2015 October)</H3>
<UL>
<LI>
Replaced the license text supplied by the University of California, Berkeley.
</UL>
<H3>Release 3 (2015 February)</H3>
<UL>
<LI>
Complete rewrite, funded by the University of California, Berkeley, and
consequently having a different use license than earlier releases.
Major changes included renaming most types and functions, upgrading some
algorithms, restructuring the source files, and making SoftFloat into a true
library.
<LI>
Added functions to convert between floating-point and unsigned integers, both
<NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR> (<CODE>uint32_t</CODE> and
<CODE>uint64_t</CODE>).
<LI>
Added functions for fused multiply-add, for all supported floating-point
formats except <NOBR>80-bit</NOBR> double-extended-precision.
<LI>
Added support for a fifth rounding mode, <CODE>near_maxMag</CODE> (round to
nearest, with ties to maximum magnitude, away from zero).
<LI>
Dropped the <CODE>timesoftfloat</CODE> program (now part of the Berkeley
TestFloat package).
</UL>
<H3>Release 2c (2015 January)</H3>
<UL>
<LI>
Fixed mistakes affecting some <NOBR>64-bit</NOBR> processors.
<LI>
Further improved the documentation and the wording for the legal restrictions
on using SoftFloat releases <NOBR>through 2c</NOBR> (not applicable to
<NOBR>Release 3</NOBR> or later).
</UL>
<H3>Release 2b (2002 May)</H3>
<UL>
<LI>
Made minor updates to the documentation, including improved wording for the
legal restrictions on using SoftFloat.
</UL>
<H3>Release 2a (1998 December)</H3>
<UL>
<LI>
Added functions to convert between <NOBR>64-bit</NOBR> integers
(<CODE>int64</CODE>) and all supported floating-point formats.
<LI>
Fixed a bug in all <NOBR>64-bit</NOBR>-version square root functions except
<CODE>float32_sqrt</CODE> that caused the result sometimes to be off by
<NOBR>1 unit</NOBR> in the last place (<NOBR>1 ulp</NOBR>) from what it should
be.
(Bug discovered by Paul Donahue.)
<LI>
Improved the Makefiles.
</UL>
<H3>Release 2 (1997 June)</H3>
<UL>
<LI>
Created the <NOBR>64-bit</NOBR> (<CODE>bits64</CODE>) version, adding the
<CODE>floatx80</CODE> and <CODE>float128</CODE> formats.
<LI>
Changed the source directory structure, splitting the sources into a
<CODE>bits32</CODE> and a <CODE>bits64</CODE> version.
Renamed <CODE>environment.h</CODE> to <CODE>milieu.h</CODE> to avoid confusion
with environment variables.
<LI>
Fixed a small error that caused <CODE>float64_round_to_int</CODE> often to
round the wrong way in nearest/even mode when the operand was between
2<SUP>20</SUP> and 2<SUP>21</SUP> and halfway between two integers.
</UL>
<H3>Release 1a (1996 July)</H3>
<UL>
<LI>
Corrected a mistake that caused borderline underflow cases not to raise the
underflow flag when they should have.
(Problem reported by Doug Priest.)
<LI>
Added the <CODE>float_detect_tininess</CODE> variable to control whether
tininess is detected before or after rounding.
</UL>
<H3>Release 1 (1996 July)</H3>
<UL>
<LI>
Original release, based on work done for the International Computer Science
Institute (ICSI) in Berkeley, California.
</UL>
</BODY>

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114
softfloat/source/8086-SSE/extF80M_isSignalingNaN.c
View File

@ -1,57 +1,57 @@
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "platform.h"
#include "softfloat.h"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
bool extF80M_isSignalingNaN( const extFloat80_t *aPtr )
{
const struct extFloat80M *aSPtr;
uint64_t uiA0;
aSPtr = (const struct extFloat80M *) aPtr;
if ( (aSPtr->signExp & 0x7FFF) != 0x7FFF ) return false;
uiA0 = aSPtr->signif;
return
! (uiA0 & UINT64_C( 0x4000000000000000 ))
&& (uiA0 & UINT64_C( 0x3FFFFFFFFFFFFFFF));
}
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "platform.h"
#include "softfloat.h"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
bool extF80M_isSignalingNaN( const extFloat80_t *aPtr )
{
const struct extFloat80M *aSPtr;
uint64_t uiA0;
aSPtr = (const struct extFloat80M *) aPtr;
if ( (aSPtr->signExp & 0x7FFF) != 0x7FFF ) return false;
uiA0 = aSPtr->signif;
return
! (uiA0 & UINT64_C( 0x4000000000000000 ))
&& (uiA0 & UINT64_C( 0x3FFFFFFFFFFFFFFF));
}

120
softfloat/source/8086-SSE/f128M_isSignalingNaN.c
View File

@ -1,60 +1,60 @@
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "platform.h"
#include "primitives.h"
#include "softfloat.h"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
bool f128M_isSignalingNaN( const float128_t *aPtr )
{
const uint32_t *aWPtr;
uint32_t uiA96;
aWPtr = (const uint32_t *) aPtr;
uiA96 = aWPtr[indexWordHi( 4 )];
if ( (uiA96 & 0x7FFF8000) != 0x7FFF0000 ) return false;
return
((uiA96 & 0x00007FFF) != 0)
|| ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
| aWPtr[indexWord( 4, 0 )])
!= 0);
}
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "platform.h"
#include "primitives.h"
#include "softfloat.h"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
bool f128M_isSignalingNaN( const float128_t *aPtr )
{
const uint32_t *aWPtr;
uint32_t uiA96;
aWPtr = (const uint32_t *) aPtr;
uiA96 = aWPtr[indexWordHi( 4 )];
if ( (uiA96 & 0x7FFF8000) != 0x7FFF0000 ) return false;
return
((uiA96 & 0x00007FFF) != 0)
|| ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
| aWPtr[indexWord( 4, 0 )])
!= 0);
}

59
softfloat/source/8086-SSE/s_bf16UIToCommonNaN.c
View File

@ -1,59 +0,0 @@
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "platform.h"
#include "specialize.h"
#include "softfloat.h"
/*----------------------------------------------------------------------------
| Assuming `uiA' has the bit pattern of a BF16 NaN, converts
| this NaN to the common NaN form, and stores the resulting common NaN at the
| location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid
| exception is raised.
*----------------------------------------------------------------------------*/
void softfloat_bf16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr )
{
if ( softfloat_isSigNaNBF16UI( uiA ) ) {
softfloat_raiseFlags( softfloat_flag_invalid );
}
zPtr->sign = uiA>>15;
zPtr->v64 = (uint_fast64_t) uiA<<56;
zPtr->v0 = 0;
}

51
softfloat/source/8086-SSE/s_commonNaNToBF16UI.c
View File

@ -1,51 +0,0 @@
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "platform.h"
#include "specialize.h"
/*----------------------------------------------------------------------------
| Converts the common NaN pointed to by `aPtr' into a BF16 NaN, and
| returns the bit pattern of this value as an unsigned integer.
*----------------------------------------------------------------------------*/
uint_fast16_t softfloat_commonNaNToBF16UI( const struct commonNaN *aPtr )
{
return (uint_fast16_t) aPtr->sign<<15 | 0x7FC0 | aPtr->v64>>56;
}

112
softfloat/source/8086-SSE/s_commonNaNToExtF80M.c
View File

@ -1,56 +1,56 @@
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "platform.h"
#include "internals.h"
#include "specialize.h"
/*----------------------------------------------------------------------------
| Converts the common NaN pointed to by `aPtr' into an 80-bit extended
| floating-point NaN, and stores this NaN at the location pointed to by
| `zSPtr'.
*----------------------------------------------------------------------------*/
void
softfloat_commonNaNToExtF80M(
const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
{
zSPtr->signExp = packToExtF80UI64( aPtr->sign, 0x7FFF );
zSPtr->signif = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
}
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "platform.h"
#include "internals.h"
#include "specialize.h"
/*----------------------------------------------------------------------------
| Converts the common NaN pointed to by `aPtr' into an 80-bit extended
| floating-point NaN, and stores this NaN at the location pointed to by
| `zSPtr'.
*----------------------------------------------------------------------------*/
void
softfloat_commonNaNToExtF80M(
const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
{
zSPtr->signExp = packToExtF80UI64( aPtr->sign, 0x7FFF );
zSPtr->signif = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
}

112
softfloat/source/8086-SSE/s_commonNaNToExtF80UI.c
View File

@ -1,56 +1,56 @@
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "platform.h"
#include "primitives.h"
#include "specialize.h"
/*----------------------------------------------------------------------------
| Converts the common NaN pointed to by `aPtr' into an 80-bit extended
| floating-point NaN, and returns the bit pattern of this value as an unsigned
| integer.
*----------------------------------------------------------------------------*/
struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
{
struct uint128 uiZ;
uiZ.v64 = (uint_fast16_t) aPtr->sign<<15 | 0x7FFF;
uiZ.v0 = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
return uiZ;
}
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "platform.h"
#include "primitives.h"
#include "specialize.h"
/*----------------------------------------------------------------------------
| Converts the common NaN pointed to by `aPtr' into an 80-bit extended
| floating-point NaN, and returns the bit pattern of this value as an unsigned
| integer.
*----------------------------------------------------------------------------*/
struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
{
struct uint128 uiZ;
uiZ.v64 = (uint_fast16_t) aPtr->sign<<15 | 0x7FFF;
uiZ.v0 = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
return uiZ;
}

112
softfloat/source/8086-SSE/s_commonNaNToF128M.c
View File

@ -1,56 +1,56 @@
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "platform.h"
#include "primitives.h"
#include "specialize.h"
/*----------------------------------------------------------------------------
| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point
| NaN, and stores this NaN at the location pointed to by `zWPtr'. Argument
| `zWPtr' points to an array of four 32-bit elements that concatenate in the
| platform's normal endian order to form a 128-bit floating-point value.
*----------------------------------------------------------------------------*/
void
softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
{
softfloat_shortShiftRight128M( (const uint32_t *) &aPtr->v0, 16, zWPtr );
zWPtr[indexWordHi( 4 )] |= (uint32_t) aPtr->sign<<31 | 0x7FFF8000;
}
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "platform.h"
#include "primitives.h"
#include "specialize.h"
/*----------------------------------------------------------------------------
| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point
| NaN, and stores this NaN at the location pointed to by `zWPtr'. Argument
| `zWPtr' points to an array of four 32-bit elements that concatenate in the
| platform's normal endian order to form a 128-bit floating-point value.
*----------------------------------------------------------------------------*/
void
softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
{
softfloat_shortShiftRight128M( (const uint32_t *) &aPtr->v0, 16, zWPtr );
zWPtr[indexWordHi( 4 )] |= (uint32_t) aPtr->sign<<31 | 0x7FFF8000;
}

110
softfloat/source/8086-SSE/s_commonNaNToF128UI.c
View File

@ -1,55 +1,55 @@
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "platform.h"
#include "primitives.h"
#include "specialize.h"
/*----------------------------------------------------------------------------
| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point
| NaN, and returns the bit pattern of this value as an unsigned integer.
*----------------------------------------------------------------------------*/
struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
{
struct uint128 uiZ;
uiZ = softfloat_shortShiftRight128( aPtr->v64, aPtr->v0, 16 );
uiZ.v64 |= (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FFF800000000000 );
return uiZ;
}
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "platform.h"
#include "primitives.h"
#include "specialize.h"
/*----------------------------------------------------------------------------
| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point
| NaN, and returns the bit pattern of this value as an unsigned integer.
*----------------------------------------------------------------------------*/
struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
{
struct uint128 uiZ;
uiZ = softfloat_shortShiftRight128( aPtr->v64, aPtr->v0, 16 );
uiZ.v64 |= (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FFF800000000000 );
return uiZ;
}

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