adds generator changed output

CMakeLists.txt

@@ -109,16 +109,6 @@ if(TARGET yaml-cpp::yaml-cpp)
     target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp)
 endif()
 
-if(WITH_LLVM)
-    find_package(LLVM)
-    target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS})
-    target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS})
-
-    if(BUILD_SHARED_LIBS)
-        target_link_libraries(${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES})
-    endif()
-endif()
-
 set_target_properties(${PROJECT_NAME} PROPERTIES
     VERSION ${PROJECT_VERSION}
     FRAMEWORK FALSE

gen_input/templates/CORENAME.h.gtl

@@ -131,8 +131,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     uint8_t* get_regs_base_ptr() override;
 
-    inline uint64_t get_icount() { return reg.icount; }
-
     inline bool should_stop() { return interrupt_sim; }
 
     inline uint64_t stop_code() { return interrupt_sim; }
@@ -141,8 +139,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
 
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
 
 #pragma pack(push, 1)
     struct ${coreDef.name}_regs {<%

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -96,7 +96,7 @@ protected:
     using this_class = vm_impl<ARCH>;
     using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
 
-    continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
+    continuation_e gen_single_inst_behavior(virt_addr_t&, jit_holder&) override;
     enum globals_e {TVAL = 0, GLOBALS_SIZE};
     void gen_block_prologue(jit_holder& jh) override;
     void gen_block_epilogue(jit_holder& jh) override;
@@ -221,7 +221,7 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
     }()) {}
 
 template <typename ARCH>
-continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
+continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
     phys_addr_t paddr(pc);
@@ -233,7 +233,6 @@ continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
         return JUMP_TO_SELF;
-    ++inst_cnt;
     uint32_t inst_index = instr_decoder.decode_instr(instr);
     compile_func f = nullptr;
     if(inst_index < instr_descr.size())

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -199,9 +199,6 @@ template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
     volatile CODE_WORD x = insn;
     insn = 2 * x;
 }
-
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
-
 // according to
 // https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
 #ifdef __GCC__

gen_input/templates/llvm/CORENAME.cpp.gtl

@@ -101,7 +101,7 @@ protected:
         return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
     }
 
-    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
+    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, BasicBlock *) override;
 
     void gen_leave_behavior(BasicBlock *leave_blk) override;
     void gen_raise_trap(uint16_t trap_id, uint16_t cause);
@@ -244,7 +244,7 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 
 template <typename ARCH>
 std::tuple<continuation_e, BasicBlock *>
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, BasicBlock *this_block) {
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
@@ -256,9 +256,10 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
     auto res = this->core.read(paddr, 4, data);
     if (res != iss::Ok) 
         return std::make_tuple(ILLEGAL_FETCH, nullptr);
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001)
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001){
+        this->builder.CreateBr(this->leave_blk);
         return std::make_tuple(JUMP_TO_SELF, nullptr);
-    ++inst_cnt;
+        }
     uint32_t inst_index = instr_decoder.decode_instr(instr);
     compile_func f = nullptr;
     if(inst_index < instr_descr.size())
@@ -340,6 +341,10 @@ void vm_impl<ARCH>::gen_instr_epilogue(BasicBlock *bb) {
     auto* icount_val = this->builder.CreateAdd(
         this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::ICOUNT), get_reg_ptr(arch::traits<ARCH>::ICOUNT)), this->gen_const(64U, 1));
     this->builder.CreateStore(icount_val, get_reg_ptr(arch::traits<ARCH>::ICOUNT), false);
+    //increment cyclecount
+    auto* cycle_val = this->builder.CreateAdd(
+        this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::CYCLE), get_reg_ptr(arch::traits<ARCH>::CYCLE)), this->gen_const(64U, 1));
+    this->builder.CreateStore(cycle_val, get_reg_ptr(arch::traits<ARCH>::CYCLE), false);
 }
 
 } // namespace ${coreDef.name.toLowerCase()}

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -83,21 +83,21 @@ protected:
     using vm_base<ARCH>::get_reg_ptr;
 
     using this_class = vm_impl<ARCH>;
-    using compile_ret_t = std::tuple<continuation_e>;
+    using compile_ret_t = continuation_e;
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
 
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 <%
 if(fcsr != null) {%>
     inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}   
-
-    void add_prologue(tu_builder& tu) override;
 <%}%>
+    void add_prologue(tu_builder& tu) override;
+
     void setup_module(std::string m) override {
         super::setup_module(m);
     }
 
-    compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, tu_builder&) override;
+    compile_ret_t gen_single_inst_behavior(virt_addr_t &, tu_builder&) override;
 
     void gen_trap_behavior(tu_builder& tu) override;
 
@@ -176,6 +176,7 @@ private:
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
         pc=pc+ ${instr.length/8};
         gen_set_pc(tu, pc, traits::NEXT_PC);
+        tu("(*cycle)++;");
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         <%instr.behavior.eachLine{%>${it}
@@ -225,8 +226,8 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
     }()) {}
 
 template <typename ARCH>
-std::tuple<continuation_e>
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
+continuation_e
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, tu_builder& tu) {
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
@@ -238,7 +239,6 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001) 
         return JUMP_TO_SELF;
-    ++inst_cnt;
     uint32_t inst_index = instr_decoder.decode_instr(instr);
     compile_func f = nullptr;
     if(inst_index < instr_descr.size())
@@ -273,10 +273,12 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP),32));
     tu("return *next_pc;");
 }
-<%
-if(fcsr != null) {%>
 template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
     std::ostringstream os;
+    os << tu.add_reg_ptr("trap_state", arch::traits<ARCH>::TRAP_STATE, this->regs_base_ptr);
+    os << tu.add_reg_ptr("pending_trap", arch::traits<ARCH>::PENDING_TRAP, this->regs_base_ptr);
+    os << tu.add_reg_ptr("cycle", arch::traits<ARCH>::CYCLE, this->regs_base_ptr);
+<%if(fcsr != null) {%>
     os << "uint32_t (*fget_flags)()=" << (uintptr_t)&fget_flags << ";\\n";
     os << "uint32_t (*fadd_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fadd_s << ";\\n";
     os << "uint32_t (*fsub_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fsub_s << ";\\n";
@@ -303,9 +305,9 @@ template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
     os << "uint64_t (*fcvt_32_64)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_32_64 << ";\\n";
     os << "uint32_t (*fcvt_64_32)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_64_32 << ";\\n";
     os << "uint32_t (*unbox_s)(uint64_t v)=" << (uintptr_t)&unbox_s << ";\\n";
+    <%}%>
     tu.add_prologue(os.str());
 }
-<%}%>
 
 } // namespace ${coreDef.name.toLowerCase()}
 

src/vm/asmjit/vm_tgc5c.cpp

@@ -94,7 +94,7 @@ protected:
     using this_class = vm_impl<ARCH>;
     using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
 
-    continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
+    continuation_e gen_single_inst_behavior(virt_addr_t&, jit_holder&) override;
     enum globals_e {TVAL = 0, GLOBALS_SIZE};
     void gen_block_prologue(jit_holder& jh) override;
     void gen_block_epilogue(jit_holder& jh) override;
@@ -4780,7 +4780,7 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
     }()) {}
 
 template <typename ARCH>
-continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
+continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
     phys_addr_t paddr(pc);
@@ -4792,7 +4792,6 @@ continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
         return JUMP_TO_SELF;
-    ++inst_cnt;
     uint32_t inst_index = instr_decoder.decode_instr(instr);
     compile_func f = nullptr;
     if(inst_index < instr_descr.size())

src/vm/interp/vm_tgc5c.cpp

@@ -275,9 +275,6 @@ template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
     volatile CODE_WORD x = insn;
     insn = 2 * x;
 }
-
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
-
 // according to
 // https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
 #ifdef __GCC__
@@ -709,9 +706,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
-                                        int8_t res_27 = super::template read_mem<int8_t>(traits::MEM, load_address);
+                                        int8_t res_1 = super::template read_mem<int8_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        int8_t res = (int8_t)res_27;
+                                        int8_t res = (int8_t)res_1;
                                         if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -740,9 +737,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
-                                        int16_t res_28 = super::template read_mem<int16_t>(traits::MEM, load_address);
+                                        int16_t res_2 = super::template read_mem<int16_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        int16_t res = (int16_t)res_28;
+                                        int16_t res = (int16_t)res_2;
                                         if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -771,9 +768,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
-                                        int32_t res_29 = super::template read_mem<int32_t>(traits::MEM, load_address);
+                                        int32_t res_3 = super::template read_mem<int32_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        int32_t res = (int32_t)res_29;
+                                        int32_t res = (int32_t)res_3;
                                         if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -802,9 +799,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
-                                        uint8_t res_30 = super::template read_mem<uint8_t>(traits::MEM, load_address);
+                                        uint8_t res_4 = super::template read_mem<uint8_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint8_t res = res_30;
+                                        uint8_t res = res_4;
                                         if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -833,9 +830,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
-                                        uint16_t res_31 = super::template read_mem<uint16_t>(traits::MEM, load_address);
+                                        uint16_t res_5 = super::template read_mem<uint16_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint16_t res = res_31;
+                                        uint16_t res = res_5;
                                         if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -1541,9 +1538,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     else {
                                         uint32_t xrs1 = *(X+rs1);
                                         if(rd != 0) {
-                                            uint32_t res_32 = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                            uint32_t res_6 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                            uint32_t xrd = res_32;
+                                            uint32_t xrd = res_6;
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrs1);
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                             *(X+rd) = xrd;
@@ -1576,9 +1573,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-                                        uint32_t res_33 = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_7 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = res_33;
+                                        uint32_t xrd = res_7;
                                         uint32_t xrs1 = *(X+rs1);
                                         if(rs1 != 0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd | xrs1);
@@ -1611,9 +1608,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-                                        uint32_t res_34 = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_8 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = res_34;
+                                        uint32_t xrd = res_8;
                                         uint32_t xrs1 = *(X+rs1);
                                         if(rs1 != 0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ xrs1);
@@ -1646,9 +1643,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-                                        uint32_t res_35 = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_9 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = res_35;
+                                        uint32_t xrd = res_9;
                                         super::template write_mem<uint32_t>(traits::CSR, csr, (uint32_t)zimm);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         if(rd != 0) {
@@ -1678,9 +1675,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-                                        uint32_t res_36 = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_10 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = res_36;
+                                        uint32_t xrd = res_10;
                                         if(zimm != 0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd | (uint32_t)zimm);
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
@@ -1712,9 +1709,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-                                        uint32_t res_37 = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_11 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = res_37;
+                                        uint32_t xrd = res_11;
                                         if(zimm != 0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ ((uint32_t)zimm));
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
@@ -2049,9 +2046,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                         uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm ));
-                        int32_t res_38 = super::template read_mem<int32_t>(traits::MEM, offs);
+                        int32_t res_12 = super::template read_mem<int32_t>(traits::MEM, offs);
                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                        *(X+rd + 8) = (uint32_t)(int32_t)res_38;
+                        *(X+rd + 8) = (uint32_t)(int32_t)res_12;
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -2475,9 +2472,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         }
                         else {
                             uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm ));
-                            int32_t res_39 = super::template read_mem<int32_t>(traits::MEM, offs);
+                            int32_t res_13 = super::template read_mem<int32_t>(traits::MEM, offs);
                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                            *(X+rd) = (uint32_t)(int32_t)res_39;
+                            *(X+rd) = (uint32_t)(int32_t)res_13;
                         }
                     }
                     break;

src/vm/llvm/vm_tgc5c.cpp

@@ -97,7 +97,7 @@ protected:
         return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
     }
 
-    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
+    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, BasicBlock *) override;
 
     void gen_leave_behavior(BasicBlock *leave_blk) override;
     void gen_raise_trap(uint16_t trap_id, uint16_t cause);
@@ -4937,7 +4937,7 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 
 template <typename ARCH>
 std::tuple<continuation_e, BasicBlock *>
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, BasicBlock *this_block) {
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
@@ -4949,9 +4949,10 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
     auto res = this->core.read(paddr, 4, data);
     if (res != iss::Ok) 
         return std::make_tuple(ILLEGAL_FETCH, nullptr);
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001)
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001){
+        this->builder.CreateBr(this->leave_blk);
         return std::make_tuple(JUMP_TO_SELF, nullptr);
-    ++inst_cnt;
+        }
     uint32_t inst_index = instr_decoder.decode_instr(instr);
     compile_func f = nullptr;
     if(inst_index < instr_descr.size())
@@ -5033,6 +5034,10 @@ void vm_impl<ARCH>::gen_instr_epilogue(BasicBlock *bb) {
     auto* icount_val = this->builder.CreateAdd(
         this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::ICOUNT), get_reg_ptr(arch::traits<ARCH>::ICOUNT)), this->gen_const(64U, 1));
     this->builder.CreateStore(icount_val, get_reg_ptr(arch::traits<ARCH>::ICOUNT), false);
+    //increment cyclecount
+    auto* cycle_val = this->builder.CreateAdd(
+        this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::CYCLE), get_reg_ptr(arch::traits<ARCH>::CYCLE)), this->gen_const(64U, 1));
+    this->builder.CreateStore(cycle_val, get_reg_ptr(arch::traits<ARCH>::CYCLE), false);
 }
 
 } // namespace tgc5c