Merge remote-tracking branch 'origin/develop'

https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git

CMakeLists.txt

@@ -109,6 +109,16 @@ if(TARGET yaml-cpp::yaml-cpp)
     target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp)
 endif()
 
+if(WITH_LLVM)
+    find_package(LLVM)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS})
+    target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS})
+
+    if(BUILD_SHARED_LIBS)
+        target_link_libraries(${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES})
+    endif()
+endif()
+
 set_target_properties(${PROJECT_NAME} PROPERTIES
     VERSION ${PROJECT_VERSION}
     FRAMEWORK FALSE

gen_input/templates/CORENAME.h.gtl

@@ -131,6 +131,8 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     uint8_t* get_regs_base_ptr() override;
 
+    inline uint64_t get_icount() { return reg.icount; }
+
     inline bool should_stop() { return interrupt_sim; }
 
     inline uint64_t stop_code() { return interrupt_sim; }
@@ -139,6 +141,8 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
 
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
 
 #pragma pack(push, 1)
     struct ${coreDef.name}_regs {<%

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -96,7 +96,7 @@ protected:
     using this_class = vm_impl<ARCH>;
     using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
 
-    continuation_e gen_single_inst_behavior(virt_addr_t&, jit_holder&) override;
+    continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
     enum globals_e {TVAL = 0, GLOBALS_SIZE};
     void gen_block_prologue(jit_holder& jh) override;
     void gen_block_epilogue(jit_holder& jh) override;
@@ -221,7 +221,7 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
     }()) {}
 
 template <typename ARCH>
-continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) {
+continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
     phys_addr_t paddr(pc);
@@ -233,6 +233,7 @@ continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_hold
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
         return JUMP_TO_SELF;
+    ++inst_cnt;
     uint32_t inst_index = instr_decoder.decode_instr(instr);
     compile_func f = nullptr;
     if(inst_index < instr_descr.size())

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -199,6 +199,9 @@ template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
     volatile CODE_WORD x = insn;
     insn = 2 * x;
 }
+
+template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
+
 // according to
 // https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
 #ifdef __GCC__

gen_input/templates/llvm/CORENAME.cpp.gtl

@@ -101,7 +101,7 @@ protected:
         return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
     }
 
-    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, BasicBlock *) override;
+    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
 
     void gen_leave_behavior(BasicBlock *leave_blk) override;
     void gen_raise_trap(uint16_t trap_id, uint16_t cause);
@@ -244,7 +244,7 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 
 template <typename ARCH>
 std::tuple<continuation_e, BasicBlock *>
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, BasicBlock *this_block) {
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
@@ -256,10 +256,9 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, BasicBlock *this_block)
     auto res = this->core.read(paddr, 4, data);
     if (res != iss::Ok) 
         return std::make_tuple(ILLEGAL_FETCH, nullptr);
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001){
-        this->builder.CreateBr(this->leave_blk);
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001)
         return std::make_tuple(JUMP_TO_SELF, nullptr);
-        }
+    ++inst_cnt;
     uint32_t inst_index = instr_decoder.decode_instr(instr);
     compile_func f = nullptr;
     if(inst_index < instr_descr.size())
@@ -341,10 +340,6 @@ void vm_impl<ARCH>::gen_instr_epilogue(BasicBlock *bb) {
     auto* icount_val = this->builder.CreateAdd(
         this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::ICOUNT), get_reg_ptr(arch::traits<ARCH>::ICOUNT)), this->gen_const(64U, 1));
     this->builder.CreateStore(icount_val, get_reg_ptr(arch::traits<ARCH>::ICOUNT), false);
-    //increment cyclecount
-    auto* cycle_val = this->builder.CreateAdd(
-        this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::CYCLE), get_reg_ptr(arch::traits<ARCH>::CYCLE)), this->gen_const(64U, 1));
-    this->builder.CreateStore(cycle_val, get_reg_ptr(arch::traits<ARCH>::CYCLE), false);
 }
 
 } // namespace ${coreDef.name.toLowerCase()}

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -83,21 +83,21 @@ protected:
     using vm_base<ARCH>::get_reg_ptr;
 
     using this_class = vm_impl<ARCH>;
-    using compile_ret_t = continuation_e;
+    using compile_ret_t = std::tuple<continuation_e>;
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
 
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 <%
 if(fcsr != null) {%>
     inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}   
-<%}%>
-    void add_prologue(tu_builder& tu) override;
 
+    void add_prologue(tu_builder& tu) override;
+<%}%>
     void setup_module(std::string m) override {
         super::setup_module(m);
     }
 
-    compile_ret_t gen_single_inst_behavior(virt_addr_t &, tu_builder&) override;
+    compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, tu_builder&) override;
 
     void gen_trap_behavior(tu_builder& tu) override;
 
@@ -176,7 +176,6 @@ private:
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
         pc=pc+ ${instr.length/8};
         gen_set_pc(tu, pc, traits::NEXT_PC);
-        tu("(*cycle)++;");
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         <%instr.behavior.eachLine{%>${it}
@@ -226,8 +225,8 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
     }()) {}
 
 template <typename ARCH>
-continuation_e
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, tu_builder& tu) {
+std::tuple<continuation_e>
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
@@ -239,6 +238,7 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, tu_builder& tu) {
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001) 
         return JUMP_TO_SELF;
+    ++inst_cnt;
     uint32_t inst_index = instr_decoder.decode_instr(instr);
     compile_func f = nullptr;
     if(inst_index < instr_descr.size())
@@ -273,12 +273,10 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP),32));
     tu("return *next_pc;");
 }
+<%
+if(fcsr != null) {%>
 template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
     std::ostringstream os;
-    os << tu.add_reg_ptr("trap_state", arch::traits<ARCH>::TRAP_STATE, this->regs_base_ptr);
-    os << tu.add_reg_ptr("pending_trap", arch::traits<ARCH>::PENDING_TRAP, this->regs_base_ptr);
-    os << tu.add_reg_ptr("cycle", arch::traits<ARCH>::CYCLE, this->regs_base_ptr);
-<%if(fcsr != null) {%>
     os << "uint32_t (*fget_flags)()=" << (uintptr_t)&fget_flags << ";\\n";
     os << "uint32_t (*fadd_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fadd_s << ";\\n";
     os << "uint32_t (*fsub_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fsub_s << ";\\n";
@@ -305,9 +303,9 @@ template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
     os << "uint64_t (*fcvt_32_64)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_32_64 << ";\\n";
     os << "uint32_t (*fcvt_64_32)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_64_32 << ";\\n";
     os << "uint32_t (*unbox_s)(uint64_t v)=" << (uintptr_t)&unbox_s << ";\\n";
-    <%}%>
     tu.add_prologue(os.str());
 }
+<%}%>
 
 } // namespace ${coreDef.name.toLowerCase()}
 

src/iss/arch/riscv_hart_common.h

@@ -36,14 +36,11 @@
 #define _RISCV_HART_COMMON
 
 #include "iss/vm_types.h"
-#include <array>
 #include <cstdint>
 #include <elfio/elfio.hpp>
 #include <fmt/format.h>
 #include <iss/arch_if.h>
 #include <iss/log_categories.h>
-#include <limits>
-#include <sstream>
 #include <string>
 #include <unordered_map>
 #include <util/logging.h>
@@ -59,6 +56,8 @@
 namespace iss {
 namespace arch {
 
+enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
+
 enum features_e { FEAT_NONE, FEAT_PMP = 1, FEAT_EXT_N = 2, FEAT_CLIC = 4, FEAT_DEBUG = 8, FEAT_TCM = 16 };
 
 enum riscv_csr {
@@ -314,16 +313,11 @@ inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t* const
 }
 struct riscv_hart_common {
     riscv_hart_common(){};
-    ~riscv_hart_common() {
-        if(io_buf.str().length()) {
-            CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
-        }
-    };
+    ~riscv_hart_common(){};
     std::unordered_map<std::string, uint64_t> symbol_table;
     uint64_t entry_address{0};
-    uint64_t tohost = std::numeric_limits<uint64_t>::max();
-    uint64_t fromhost = std::numeric_limits<uint64_t>::max();
-    std::stringstream io_buf;
+    uint64_t tohost = tohost_dflt;
+    uint64_t fromhost = fromhost_dflt;
 
     bool read_elf_file(std::string name, uint8_t expected_elf_class,
                        std::function<iss::status(uint64_t, uint64_t, const uint8_t* const)> cb) {
@@ -371,10 +365,11 @@ struct riscv_hart_common {
                 }
                 try {
                     tohost = symbol_table.at("tohost");
-                } catch(std::out_of_range& e) {
-                }
                     try {
                         fromhost = symbol_table.at("fromhost");
+                    } catch(std::out_of_range& e) {
+                        fromhost = tohost + 0x40;
+                    }
                 } catch(std::out_of_range& e) {
                 }
             }
@@ -382,33 +377,6 @@ struct riscv_hart_common {
         }
         return false;
     };
-    iss::status execute_sys_write(arch_if* aif, const std::array<uint64_t, 8>& loaded_payload, unsigned mem_type) {
-        uint64_t fd = loaded_payload[1];
-        uint64_t buf_ptr = loaded_payload[2];
-        uint64_t len = loaded_payload[3];
-        std::vector<char> buf(len);
-        if(aif->read(address_type::PHYSICAL, access_type::DEBUG_READ, mem_type, buf_ptr, len, reinterpret_cast<uint8_t*>(buf.data()))) {
-            CPPLOG(ERR) << "SYS_WRITE buffer read went wrong";
-            return iss::Err;
-        }
-        // we disregard the fd and just log to stdout
-        for(size_t i = 0; i < len; i++) {
-            if(buf[i] == '\n' || buf[i] == '\0') {
-                CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
-                io_buf.str("");
-            } else
-                io_buf << buf[i];
-        }
-
-        // Not sure what the correct return value should be
-        uint8_t ret_val = 1;
-        if(fromhost != std::numeric_limits<uint64_t>::max())
-            if(aif->write(address_type::PHYSICAL, access_type::DEBUG_WRITE, mem_type, fromhost, 1, &ret_val)) {
-                CPPLOG(ERR) << "Fromhost write went wrong";
-                return iss::Err;
-            }
-        return iss::Ok;
-    }
 };
 
 } // namespace arch

src/iss/arch/riscv_hart_m_p.h

@@ -41,11 +41,7 @@
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
 #include "riscv_hart_common.h"
-#include "util/logging.h"
-#include <algorithm>
-#include <cstdint>
 #include <elfio/elf_types.hpp>
-#include <limits>
 #include <stdexcept>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -348,6 +344,7 @@ protected:
     int64_t instret_offset{0};
     uint64_t minstret_csr{0};
     reg_t fault_data;
+    bool tohost_lower_written = false;
     riscv_instrumentation_if instr_if;
 
     semihosting_cb_t<reg_t> semihosting_cb;
@@ -357,6 +354,7 @@ protected:
     using csr_page_type = typename csr_type::page_type;
     mem_type mem;
     csr_type csr;
+    std::stringstream uart_buf;
     std::unordered_map<reg_t, uint64_t> ptw;
     std::unordered_map<uint64_t, uint8_t> atomic_reservation;
     std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
@@ -448,6 +446,7 @@ riscv_hart_m_p<BASE, FEAT, LOGCAT>::riscv_hart_m_p(feature_config cfg)
     csr[marchid] = traits<BASE>::MARCHID_VAL;
     csr[mimpid] = 1;
 
+    uart_buf.str("");
     if(traits<BASE>::FLEN > 0) {
         csr_rd_cb[fcsr] = &this_class::read_fcsr;
         csr_wr_cb[fcsr] = &this_class::write_fcsr;
@@ -611,7 +610,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
     try {
         switch(space) {
         case traits<BASE>::MEM: {
-            auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : std::min<unsigned>(length, sizeof(reg_t));
+            auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : length;
             if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) {
                 fault_data = addr;
                 if(is_debug(access))
@@ -721,8 +720,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
                 return iss::Err;
             }
             try {
-                auto alignment = std::min<unsigned>(length, sizeof(reg_t));
-                if(length > 1 && (addr & (alignment - 1)) && !is_debug(access)) {
+                if(length > 1 && (addr & (length - 1)) && (access & access_type::DEBUG) != access_type::DEBUG) {
                     this->reg.trap_state = (1UL << 31) | 6 << 16;
                     fault_data = addr;
                     return iss::Err;
@@ -742,7 +740,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
                 } else {
                     res = write_mem(phys_addr, length, data);
                 }
-                if(unlikely(res != iss::Ok && !is_debug(access))) {
+                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
                     this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data = addr;
                 }
@@ -752,6 +750,38 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
                 fault_data = ta.addr;
                 return iss::Err;
             }
+
+            if((addr + length) > mem.size())
+                return iss::Err;
+            switch(addr) {
+            case 0x10013000: // UART0 base, TXFIFO reg
+            case 0x10023000: // UART1 base, TXFIFO reg
+                uart_buf << (char)data[0];
+                if(((char)data[0]) == '\n' || data[0] == 0) {
+                    std::cout << uart_buf.str();
+                    uart_buf.str("");
+                }
+                return iss::Ok;
+            case 0x10008000: { // HFROSC base, hfrosccfg reg
+                auto& p = mem(addr / mem.page_size);
+                auto offs = addr & mem.page_addr_mask;
+                std::copy(data, data + length, p.data() + offs);
+                auto& x = *(p.data() + offs + 3);
+                if(x & 0x40)
+                    x |= 0x80; // hfroscrdy = 1 if hfroscen==1
+                return iss::Ok;
+            }
+            case 0x10008008: { // HFROSC base, pllcfg reg
+                auto& p = mem(addr / mem.page_size);
+                auto offs = addr & mem.page_addr_mask;
+                std::copy(data, data + length, p.data() + offs);
+                auto& x = *(p.data() + offs + 3);
+                x |= 0x80; // set pll lock upon writing
+                return iss::Ok;
+            } break;
+            default: {
+            }
+            }
         } break;
         case traits<BASE>::CSR: {
             if(length != sizeof(reg_t))
@@ -1064,52 +1094,60 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read_mem(phys_addr_t paddr, unsi
 
 template <typename BASE, features_e FEAT, typename LOGCAT>
 iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
+    switch(paddr.val) {
+    // TODO remove UART, Peripherals should not be part of the ISS
+    case 0xFFFF0000: // UART0 base, TXFIFO reg
+        if(((char)data[0]) == '\n' || data[0] == 0) {
+            CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
+            uart_buf.str("");
+        } else if(((char)data[0]) != '\r')
+            uart_buf << (char)data[0];
+        break;
+    default: {
         mem_type::page_type& p = mem(paddr.val / mem.page_size);
         std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
         // tohost handling in case of riscv-test
-    // according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754:
         if(paddr.access && iss::access_type::FUNC) {
-        if(paddr.val == tohost) {
-            reg_t cur_data = *reinterpret_cast<const reg_t*>(data);
-            // Extract Device (bits 63:56)
-            uint8_t device = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 56) & 0xFF;
-            // Extract Command (bits 55:48)
-            uint8_t command = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 48) & 0xFF;
-            // Extract payload (bits 47:0)
-            uint64_t payload_addr = cur_data & 0xFFFFFFFFFFFFULL;
-            if(payload_addr & 1) {
-                CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr
+            auto tohost_upper =
+                (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
+            auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
+            if(tohost_lower || tohost_upper) {
+                uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
+                // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
+                if(tohost_upper && (tohost_lower || tohost_lower_written)) {
+                    switch(hostvar >> 48) {
+                    case 0:
+                        if(hostvar != 0x1) {
+                            CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
                                           << "), stopping simulation";
-                this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-                this->interrupt_sim = payload_addr;
-                return iss::Ok;
-            } else if(device == 0 && command == 0) {
-                std::array<uint64_t, 8> loaded_payload;
-                if(read(address_type::PHYSICAL, access_type::DEBUG_READ, traits<BASE>::MEM, payload_addr, 8 * sizeof(uint64_t),
-                        reinterpret_cast<uint8_t*>(loaded_payload.data())) == iss::Err)
-                    CPPLOG(ERR) << "Syscall read went wrong";
-                uint64_t syscall_num = loaded_payload.at(0);
-                if(syscall_num == 64) { // SYS_WRITE
-                    return execute_sys_write(this, loaded_payload, traits<BASE>::MEM);
                         } else {
-                    CPPLOG(ERR) << "tohost syscall with number 0x" << std::hex << syscall_num << std::dec << " (" << syscall_num
-                                << ") not implemented";
+                            CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
+                                         << "), stopping simulation";
+                        }
                         this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-                    this->interrupt_sim = payload_addr;
-                    return iss::Ok;
+                        this->interrupt_sim = hostvar;
+                        break;
+                    case 0x0101: {
+                        char c = static_cast<char>(hostvar & 0xff);
+                        if(c == '\n' || c == 0) {
+                            CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
+                            uart_buf.str("");
+                        } else
+                            uart_buf << c;
+                    } break;
+                    default:
+                        break;
                     }
-            } else {
-                CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command;
-                this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-                this->interrupt_sim = payload_addr;
-                return iss::Ok;
-            }
-        }
-        if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
+                    tohost_lower_written = false;
+                } else if(tohost_lower)
+                    tohost_lower_written = true;
+            } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
                 uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
                 *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
             }
         }
+    }
+    }
     return iss::Ok;
 }
 

src/iss/arch/riscv_hart_msu_vp.h

@@ -41,11 +41,6 @@
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
 #include "riscv_hart_common.h"
-#include "util/logging.h"
-#include <algorithm>
-#include <cstdint>
-#include <elfio/elf_types.hpp>
-#include <limits>
 #include <stdexcept>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -398,6 +393,7 @@ protected:
     uint64_t minstret_csr{0};
     reg_t fault_data;
     std::array<vm_info, 2> vm;
+    bool tohost_lower_written = false;
     riscv_instrumentation_if instr_if;
 
     std::function<void(arch_if*, reg_t, reg_t)> semihosting_cb;
@@ -408,6 +404,7 @@ protected:
     mem_type mem;
     csr_type csr;
     void update_vm_info();
+    std::stringstream uart_buf;
     std::unordered_map<reg_t, uint64_t> ptw;
     std::unordered_map<uint64_t, uint8_t> atomic_reservation;
     std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
@@ -462,6 +459,7 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
     csr[marchid] = traits<BASE>::MARCHID_VAL;
     csr[mimpid] = 1;
 
+    uart_buf.str("");
     for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) {
         csr_rd_cb[addr] = &this_class::read_null;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
@@ -582,7 +580,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
     try {
         switch(space) {
         case traits<BASE>::MEM: {
-            auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : std::min<unsigned>(length, sizeof(reg_t));
+            auto alignment = is_fetch(access) ? (traits<BASE>::MISA_VAL & 0x100 ? 2 : 4) : length;
             if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) {
                 fault_data = addr;
                 if(access && iss::access_type::DEBUG)
@@ -701,7 +699,6 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
             }
             phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
             try {
-                // TODO: There is no check for alignment
                 if(unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary
                     vm_info vm = hart_state_type::decode_vm_info(this->reg.PRIV, state.satp);
                     if(vm.levels != 0) { // VM is active
@@ -724,6 +721,40 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                 fault_data = ta.addr;
                 return iss::Err;
             }
+
+            if((paddr.val + length) > mem.size())
+                return iss::Err;
+            switch(paddr.val) {
+            case 0x10013000: // UART0 base, TXFIFO reg
+            case 0x10023000: // UART1 base, TXFIFO reg
+                uart_buf << (char)data[0];
+                if(((char)data[0]) == '\n' || data[0] == 0) {
+                    // CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
+                    // '"<<uart_buf.str()<<"'";
+                    std::cout << uart_buf.str();
+                    uart_buf.str("");
+                }
+                return iss::Ok;
+            case 0x10008000: { // HFROSC base, hfrosccfg reg
+                auto& p = mem(paddr.val / mem.page_size);
+                auto offs = paddr.val & mem.page_addr_mask;
+                std::copy(data, data + length, p.data() + offs);
+                auto& x = *(p.data() + offs + 3);
+                if(x & 0x40)
+                    x |= 0x80; // hfroscrdy = 1 if hfroscen==1
+                return iss::Ok;
+            }
+            case 0x10008008: { // HFROSC base, pllcfg reg
+                auto& p = mem(paddr.val / mem.page_size);
+                auto offs = paddr.val & mem.page_addr_mask;
+                std::copy(data, data + length, p.data() + offs);
+                auto& x = *(p.data() + offs + 3);
+                x |= 0x80; // set pll lock upon writing
+                return iss::Ok;
+            } break;
+            default: {
+            }
+            }
         } break;
         case traits<BASE>::CSR: {
             if(length != sizeof(reg_t))
@@ -993,52 +1024,62 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
+    switch(paddr.val) {
+    case 0xFFFF0000: // UART0 base, TXFIFO reg
+        if(((char)data[0]) == '\n' || data[0] == 0) {
+            CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
+            uart_buf.str("");
+        } else if(((char)data[0]) != '\r')
+            uart_buf << (char)data[0];
+        break;
+    default: {
         mem_type::page_type& p = mem(paddr.val / mem.page_size);
         std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
         // tohost handling in case of riscv-test
-    // according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754:
         if(paddr.access && iss::access_type::FUNC) {
-        if(paddr.val == tohost) {
-            reg_t cur_data = *reinterpret_cast<const reg_t*>(data);
-            // Extract Device (bits 63:56)
-            uint8_t device = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 56) & 0xFF;
-            // Extract Command (bits 55:48)
-            uint8_t command = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 48) & 0xFF;
-            // Extract payload (bits 47:0)
-            uint64_t payload_addr = cur_data & 0xFFFFFFFFFFFFULL;
-            if(payload_addr & 1) {
-                CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr
+            auto tohost_upper =
+                (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
+            auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
+            if(tohost_lower || tohost_upper) {
+                uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
+                // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
+                if(tohost_upper && (tohost_lower || tohost_lower_written)) {
+                    switch(hostvar >> 48) {
+                    case 0:
+                        if(hostvar != 0x1) {
+                            CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
                                           << "), stopping simulation";
-                this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-                this->interrupt_sim = payload_addr;
-                return iss::Ok;
-            } else if(device == 0 && command == 0) {
-                std::array<uint64_t, 8> loaded_payload;
-                if(read(address_type::PHYSICAL, access_type::DEBUG_READ, traits<BASE>::MEM, payload_addr, 8 * sizeof(uint64_t),
-                        reinterpret_cast<uint8_t*>(loaded_payload.data())) == iss::Err)
-                    CPPLOG(ERR) << "Syscall read went wrong";
-                uint64_t syscall_num = loaded_payload.at(0);
-                if(syscall_num == 64) { // SYS_WRITE
-                    return execute_sys_write(this, loaded_payload, traits<BASE>::MEM);
                         } else {
-                    CPPLOG(ERR) << "tohost syscall with number 0x" << std::hex << syscall_num << std::dec << " (" << syscall_num
-                                << ") not implemented";
+                            CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
+                                         << "), stopping simulation";
+                        }
                         this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-                    this->interrupt_sim = payload_addr;
-                    return iss::Ok;
+                        this->interrupt_sim = hostvar;
+#ifndef WITH_TCC
+                        throw(iss::simulation_stopped(hostvar));
+#endif
+                        break;
+                    case 0x0101: {
+                        char c = static_cast<char>(hostvar & 0xff);
+                        if(c == '\n' || c == 0) {
+                            CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
+                            uart_buf.str("");
+                        } else
+                            uart_buf << c;
+                    } break;
+                    default:
+                        break;
                     }
-            } else {
-                CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command;
-                this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-                this->interrupt_sim = payload_addr;
-                return iss::Ok;
-            }
-        }
-        if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
+                    tohost_lower_written = false;
+                } else if(tohost_lower)
+                    tohost_lower_written = true;
+            } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
                 uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
                 *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
             }
         }
+    }
+    }
     return iss::Ok;
 }
 

src/iss/arch/riscv_hart_mu_p.h

@@ -41,11 +41,6 @@
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
 #include "riscv_hart_common.h"
-#include "util/logging.h"
-#include <algorithm>
-#include <cstdint>
-#include <elfio/elf_types.hpp>
-#include <limits>
 #include <stdexcept>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -375,6 +370,7 @@ protected:
     int64_t instret_offset{0};
     uint64_t minstret_csr{0};
     reg_t fault_data;
+    bool tohost_lower_written = false;
     riscv_instrumentation_if instr_if;
 
     semihosting_cb_t<reg_t> semihosting_cb;
@@ -384,6 +380,7 @@ protected:
     using csr_page_type = typename csr_type::page_type;
     mem_type mem;
     csr_type csr;
+    std::stringstream uart_buf;
     std::unordered_map<reg_t, uint64_t> ptw;
     std::unordered_map<uint64_t, uint8_t> atomic_reservation;
     std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
@@ -478,6 +475,7 @@ riscv_hart_mu_p<BASE, FEAT, LOGCAT>::riscv_hart_mu_p(feature_config cfg)
     csr[marchid] = traits<BASE>::MARCHID_VAL;
     csr[mimpid] = 1;
 
+    uart_buf.str("");
     if(traits<BASE>::FLEN > 0) {
         csr_rd_cb[fcsr] = &this_class::read_fcsr;
         csr_wr_cb[fcsr] = &this_class::write_fcsr;
@@ -785,7 +783,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read(const address_type type, c
                     return iss::Err;
                 }
             }
-            auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : std::min<unsigned>(length, sizeof(reg_t));
+            auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : length;
             if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) {
                 fault_data = addr;
                 if(is_debug(access))
@@ -904,8 +902,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write(const address_type type,
                 return iss::Err;
             }
             try {
-                auto alignment = std::min<unsigned>(length, sizeof(reg_t));
-                if(length > 1 && (addr & (alignment - 1)) && !is_debug(access)) {
+                if(length > 1 && (addr & (length - 1)) && (access & access_type::DEBUG) != access_type::DEBUG) {
                     this->reg.trap_state = (1UL << 31) | 6 << 16;
                     fault_data = addr;
                     return iss::Err;
@@ -935,6 +932,38 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write(const address_type type,
                 fault_data = ta.addr;
                 return iss::Err;
             }
+
+            if((addr + length) > mem.size())
+                return iss::Err;
+            switch(addr) {
+            case 0x10013000: // UART0 base, TXFIFO reg
+            case 0x10023000: // UART1 base, TXFIFO reg
+                uart_buf << (char)data[0];
+                if(((char)data[0]) == '\n' || data[0] == 0) {
+                    std::cout << uart_buf.str();
+                    uart_buf.str("");
+                }
+                return iss::Ok;
+            case 0x10008000: { // HFROSC base, hfrosccfg reg
+                auto& p = mem(addr / mem.page_size);
+                auto offs = addr & mem.page_addr_mask;
+                std::copy(data, data + length, p.data() + offs);
+                auto& x = *(p.data() + offs + 3);
+                if(x & 0x40)
+                    x |= 0x80; // hfroscrdy = 1 if hfroscen==1
+                return iss::Ok;
+            }
+            case 0x10008008: { // HFROSC base, pllcfg reg
+                auto& p = mem(addr / mem.page_size);
+                auto offs = addr & mem.page_addr_mask;
+                std::copy(data, data + length, p.data() + offs);
+                auto& x = *(p.data() + offs + 3);
+                x |= 0x80; // set pll lock upon writing
+                return iss::Ok;
+            } break;
+            default: {
+            }
+            }
         } break;
         case traits<BASE>::CSR: {
             if(length != sizeof(reg_t))
@@ -1283,54 +1312,66 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read_mem(phys_addr_t paddr, uns
     }
     return iss::Ok;
 }
+
 template <typename BASE, features_e FEAT, typename LOGCAT>
 iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
+    switch(paddr.val) {
+    // TODO remove UART, Peripherals should not be part of the ISS
+    case 0xFFFF0000: // UART0 base, TXFIFO reg
+        if(((char)data[0]) == '\n' || data[0] == 0) {
+            CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
+            uart_buf.str("");
+        } else if(((char)data[0]) != '\r')
+            uart_buf << (char)data[0];
+        break;
+    default: {
         mem_type::page_type& p = mem(paddr.val / mem.page_size);
         std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
         // tohost handling in case of riscv-test
-    // according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754:
         if(paddr.access && iss::access_type::FUNC) {
-        if(paddr.val == tohost) {
-            reg_t cur_data = *reinterpret_cast<const reg_t*>(data);
-            // Extract Device (bits 63:56)
-            uint8_t device = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 56) & 0xFF;
-            // Extract Command (bits 55:48)
-            uint8_t command = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 48) & 0xFF;
-            // Extract payload (bits 47:0)
-            uint64_t payload_addr = cur_data & 0xFFFFFFFFFFFFULL;
-            if(payload_addr & 1) {
-                CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr
+            auto tohost_upper =
+                (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
+            auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
+            if(tohost_lower || tohost_upper) {
+                uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
+                // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
+                if(tohost_upper && (tohost_lower || tohost_lower_written)) {
+                    switch(hostvar >> 48) {
+                    case 0:
+                        if(hostvar != 0x1) {
+                            CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
                                           << "), stopping simulation";
-                this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-                this->interrupt_sim = payload_addr;
-                return iss::Ok;
-            } else if(device == 0 && command == 0) {
-                std::array<uint64_t, 8> loaded_payload;
-                if(read(address_type::PHYSICAL, access_type::DEBUG_READ, traits<BASE>::MEM, payload_addr, 8 * sizeof(uint64_t),
-                        reinterpret_cast<uint8_t*>(loaded_payload.data())) == iss::Err)
-                    CPPLOG(ERR) << "Syscall read went wrong";
-                uint64_t syscall_num = loaded_payload.at(0);
-                if(syscall_num == 64) { // SYS_WRITE
-                    return execute_sys_write(this, loaded_payload, traits<BASE>::MEM);
                         } else {
-                    CPPLOG(ERR) << "tohost syscall with number 0x" << std::hex << syscall_num << std::dec << " (" << syscall_num
-                                << ") not implemented";
+                            CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
+                                         << "), stopping simulation";
+                        }
                         this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-                    this->interrupt_sim = payload_addr;
-                    return iss::Ok;
+                        this->interrupt_sim = hostvar;
+#ifndef WITH_TCC
+                        throw(iss::simulation_stopped(hostvar));
+#endif
+                        break;
+                    case 0x0101: {
+                        char c = static_cast<char>(hostvar & 0xff);
+                        if(c == '\n' || c == 0) {
+                            CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
+                            uart_buf.str("");
+                        } else
+                            uart_buf << c;
+                    } break;
+                    default:
+                        break;
                     }
-            } else {
-                CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command;
-                this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-                this->interrupt_sim = payload_addr;
-                return iss::Ok;
-            }
-        }
-        if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
+                    tohost_lower_written = false;
+                } else if(tohost_lower)
+                    tohost_lower_written = true;
+            } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
                 uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
                 *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
             }
         }
+    }
+    }
     return iss::Ok;
 }
 

src/vm/asmjit/vm_tgc5c.cpp

@@ -94,7 +94,7 @@ protected:
     using this_class = vm_impl<ARCH>;
     using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
 
-    continuation_e gen_single_inst_behavior(virt_addr_t&, jit_holder&) override;
+    continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
     enum globals_e {TVAL = 0, GLOBALS_SIZE};
     void gen_block_prologue(jit_holder& jh) override;
     void gen_block_epilogue(jit_holder& jh) override;
@@ -4780,7 +4780,7 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
     }()) {}
 
 template <typename ARCH>
-continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) {
+continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
     phys_addr_t paddr(pc);
@@ -4792,6 +4792,7 @@ continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_hold
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
         return JUMP_TO_SELF;
+    ++inst_cnt;
     uint32_t inst_index = instr_decoder.decode_instr(instr);
     compile_func f = nullptr;
     if(inst_index < instr_descr.size())

src/vm/interp/vm_tgc5c.cpp

@@ -275,6 +275,9 @@ template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
     volatile CODE_WORD x = insn;
     insn = 2 * x;
 }
+
+template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
+
 // according to
 // https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
 #ifdef __GCC__
@@ -706,9 +709,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
-                                        int8_t res_1 = super::template read_mem<int8_t>(traits::MEM, load_address);
+                                        int8_t res_27 = super::template read_mem<int8_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        int8_t res = (int8_t)res_1;
+                                        int8_t res = (int8_t)res_27;
                                         if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -737,9 +740,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
-                                        int16_t res_2 = super::template read_mem<int16_t>(traits::MEM, load_address);
+                                        int16_t res_28 = super::template read_mem<int16_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        int16_t res = (int16_t)res_2;
+                                        int16_t res = (int16_t)res_28;
                                         if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -768,9 +771,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
-                                        int32_t res_3 = super::template read_mem<int32_t>(traits::MEM, load_address);
+                                        int32_t res_29 = super::template read_mem<int32_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        int32_t res = (int32_t)res_3;
+                                        int32_t res = (int32_t)res_29;
                                         if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -799,9 +802,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
-                                        uint8_t res_4 = super::template read_mem<uint8_t>(traits::MEM, load_address);
+                                        uint8_t res_30 = super::template read_mem<uint8_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint8_t res = res_4;
+                                        uint8_t res = res_30;
                                         if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -830,9 +833,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
-                                        uint16_t res_5 = super::template read_mem<uint16_t>(traits::MEM, load_address);
+                                        uint16_t res_31 = super::template read_mem<uint16_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint16_t res = res_5;
+                                        uint16_t res = res_31;
                                         if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -1538,9 +1541,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     else {
                                         uint32_t xrs1 = *(X+rs1);
                                         if(rd != 0) {
-                                            uint32_t res_6 = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                            uint32_t res_32 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                            uint32_t xrd = res_6;
+                                            uint32_t xrd = res_32;
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrs1);
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                             *(X+rd) = xrd;
@@ -1573,9 +1576,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-                                        uint32_t res_7 = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_33 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = res_7;
+                                        uint32_t xrd = res_33;
                                         uint32_t xrs1 = *(X+rs1);
                                         if(rs1 != 0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd | xrs1);
@@ -1608,9 +1611,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-                                        uint32_t res_8 = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_34 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = res_8;
+                                        uint32_t xrd = res_34;
                                         uint32_t xrs1 = *(X+rs1);
                                         if(rs1 != 0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ xrs1);
@@ -1643,9 +1646,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-                                        uint32_t res_9 = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_35 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = res_9;
+                                        uint32_t xrd = res_35;
                                         super::template write_mem<uint32_t>(traits::CSR, csr, (uint32_t)zimm);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         if(rd != 0) {
@@ -1675,9 +1678,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-                                        uint32_t res_10 = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_36 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = res_10;
+                                        uint32_t xrd = res_36;
                                         if(zimm != 0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd | (uint32_t)zimm);
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
@@ -1709,9 +1712,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-                                        uint32_t res_11 = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_37 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = res_11;
+                                        uint32_t xrd = res_37;
                                         if(zimm != 0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ ((uint32_t)zimm));
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
@@ -2046,9 +2049,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                         uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm ));
-                        int32_t res_12 = super::template read_mem<int32_t>(traits::MEM, offs);
+                        int32_t res_38 = super::template read_mem<int32_t>(traits::MEM, offs);
                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                        *(X+rd + 8) = (uint32_t)(int32_t)res_12;
+                        *(X+rd + 8) = (uint32_t)(int32_t)res_38;
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -2472,9 +2475,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         }
                         else {
                             uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm ));
-                            int32_t res_13 = super::template read_mem<int32_t>(traits::MEM, offs);
+                            int32_t res_39 = super::template read_mem<int32_t>(traits::MEM, offs);
                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                            *(X+rd) = (uint32_t)(int32_t)res_13;
+                            *(X+rd) = (uint32_t)(int32_t)res_39;
                         }
                     }
                     break;

src/vm/llvm/vm_tgc5c.cpp

@@ -97,7 +97,7 @@ protected:
         return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
     }
 
-    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, BasicBlock *) override;
+    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
 
     void gen_leave_behavior(BasicBlock *leave_blk) override;
     void gen_raise_trap(uint16_t trap_id, uint16_t cause);
@@ -4937,7 +4937,7 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 
 template <typename ARCH>
 std::tuple<continuation_e, BasicBlock *>
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, BasicBlock *this_block) {
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
@@ -4949,10 +4949,9 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, BasicBlock *this_block)
     auto res = this->core.read(paddr, 4, data);
     if (res != iss::Ok) 
         return std::make_tuple(ILLEGAL_FETCH, nullptr);
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001){
-        this->builder.CreateBr(this->leave_blk);
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001)
         return std::make_tuple(JUMP_TO_SELF, nullptr);
-        }
+    ++inst_cnt;
     uint32_t inst_index = instr_decoder.decode_instr(instr);
     compile_func f = nullptr;
     if(inst_index < instr_descr.size())
@@ -5034,10 +5033,6 @@ void vm_impl<ARCH>::gen_instr_epilogue(BasicBlock *bb) {
     auto* icount_val = this->builder.CreateAdd(
         this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::ICOUNT), get_reg_ptr(arch::traits<ARCH>::ICOUNT)), this->gen_const(64U, 1));
     this->builder.CreateStore(icount_val, get_reg_ptr(arch::traits<ARCH>::ICOUNT), false);
-    //increment cyclecount
-    auto* cycle_val = this->builder.CreateAdd(
-        this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::CYCLE), get_reg_ptr(arch::traits<ARCH>::CYCLE)), this->gen_const(64U, 1));
-    this->builder.CreateStore(cycle_val, get_reg_ptr(arch::traits<ARCH>::CYCLE), false);
 }
 
 } // namespace tgc5c