adds updated generated files

.project

@@ -23,6 +23,5 @@
 		<nature>org.eclipse.cdt.core.ccnature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-		<nature>org.eclipse.linuxtools.tmf.project.nature</nature>
 	</natures>
 </projectDescription>

CMakeLists.txt

@@ -186,10 +186,7 @@ install(TARGETS tgc-sim
 ###############################################################################
 if(TARGET scc-sysc)
 	project(dbt-rise-tgc_sc VERSION 1.0.0)
-    add_library(${PROJECT_NAME} 
-    	src/sysc/core_complex.cpp
-    	src/sysc/register_tgc_c.cpp
-    )
+    add_library(${PROJECT_NAME} src/sysc/core_complex.cpp)
     target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
     target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
     foreach(F IN LISTS TGC_SOURCES)

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -34,9 +34,10 @@ def nativeTypeSize(int size){
     if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
 %>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/iss.h>
 #include <iss/interp/vm_base.h>
 #include <util/logging.h>
@@ -314,21 +315,3 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 }
 } // namespace interp
 } // namespace iss
-
-#include <iss/factory.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()|m_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* lcpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()>();
-            return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
-        }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()|mu_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* lcpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()>();
-            return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
-        })
-};
-}
-}

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -31,6 +31,7 @@
  *******************************************************************************/
 
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
@@ -206,7 +207,7 @@ private:
             ${it}<%}%>
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc=pc+4;
+        pc=pc+ ${instr.length/8};
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();<%instr.behavior.eachLine{%>
         ${it}<%}%>
@@ -309,23 +310,5 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
     if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }
-} // namesapce tcc
+}
 } // namespace iss
-
-#include <iss/factory.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()|m_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* lcpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()>();
-            return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
-        }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()|mu_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* lcpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()>();
-            return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
-        })
-};
-}
-}

src/iss/arch/riscv_hart_m_p.h

@@ -619,9 +619,9 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
             }
             return std::make_pair(entry, true);
         }
-        throw std::runtime_error("memory load file is not a valid elf file");
+        throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name));
     }
-    throw std::runtime_error("memory load file not found");
+    throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
 }
 
 template<typename BASE, features_e FEAT>

src/iss/arch/riscv_hart_msu_vp.h

@@ -588,9 +588,9 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
             }
             return std::make_pair(entry, true);
         }
-        throw std::runtime_error("memory load file is not a valid elf file");
+        throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name));
     }
-    throw std::runtime_error("memory load file not found");
+    throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
 }
 
 template <typename BASE>

src/iss/arch/riscv_hart_mu_p.h

@@ -690,9 +690,9 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
             }
             return std::make_pair(entry, true);
         }
-        throw std::runtime_error("memory load file is not a valid elf file");
+        throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name));
     }
-    throw std::runtime_error("memory load file not found");
+    throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
 }
 
 template<typename BASE, features_e FEAT>

src/iss/arch/tgc_c.h

@@ -53,7 +53,7 @@ template <> struct traits<tgc_c> {
     static constexpr std::array<const char*, 36> reg_aliases{
         {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
 
-    enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, INSTR_ALIGNMENT=2, RFS=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, CSR_SIZE=4096, MUL_LEN=64};
+    enum constants {MISA_VAL=1073746180, MARCHID_VAL=2147483651, XLEN=32, INSTR_ALIGNMENT=2, RFS=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, CSR_SIZE=4096, MUL_LEN=64};
 
     constexpr static unsigned FP_REGS_SIZE = 0;
 

src/iss/factory.h

@@ -34,12 +34,6 @@
 #define _ISS_FACTORY_H_
 
 #include <iss/iss.h>
-#include <memory>
-#include <unordered_map>
-#include <functional>
-#include <string>
-#include <algorithm>
-#include <vector>
 
 namespace iss {
 
@@ -63,48 +57,6 @@ std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_
     return {nullptr, nullptr};
 }
 
-
-class core_factory {
-    using cpu_ptr = std::unique_ptr<iss::arch_if>;
-    using vm_ptr= std::unique_ptr<iss::vm_if>;
-    using base_t = std::tuple<cpu_ptr, vm_ptr>;
-    using create_fn = std::function<base_t(unsigned, void*) >;
-    using registry_t = std::unordered_map<std::string, create_fn> ;
-
-    registry_t registry;
-
-    core_factory() = default;
-    core_factory(const core_factory &) = delete;
-    core_factory & operator=(const core_factory &) = delete;
-
-public:
-    static core_factory & instance() { static core_factory bf; return bf; }
-
-    bool register_creator(const std::string &, create_fn const&);
-
-    base_t create(const std::string &, unsigned gdb_port=0, void* init_data=nullptr) const;
-
-    std::vector<std::string> get_names() {
-        std::vector<std::string> keys{registry.size()};
-        std::transform(std::begin(registry), std::end(registry), std::begin(keys), [](std::pair<std::string, create_fn> const& p){
-            return p.first;
-        });
-        return keys;
-    }
-};
-
-inline bool core_factory::register_creator(const std::string & className, create_fn const& fn) {
-    registry[className] = fn;
-    return true;
-}
-
-inline core_factory::base_t core_factory::create(const std::string &className, unsigned gdb_port, void* data) const {
-    registry_t::const_iterator regEntry = registry.find(className);
-    if (regEntry != registry.end())
-        return regEntry->second(gdb_port, data);
-    return {nullptr, nullptr};
-}
-
 }
 
 #endif /* _ISS_FACTORY_H_ */

src/main.cpp

@@ -33,7 +33,7 @@
 #include <iostream>
 #include <vector>
 #include <array>
-#include <iss/factory.h>
+#include "iss/factory.h"
 
 #include <boost/lexical_cast.hpp>
 #include <boost/program_options.hpp>
@@ -113,24 +113,53 @@ int main(int argc, char *argv[]) {
         iss::init_jit_debug(argc, argv);
 #endif
         bool dump = clim.count("dump-ir");
-        auto & f = iss::core_factory::instance();
         // instantiate the simulator
         iss::vm_ptr vm{nullptr};
         iss::cpu_ptr cpu{nullptr};
         std::string isa_opt(clim["isa"].as<std::string>());
-        if(isa_opt.size()==0 || isa_opt == "?") {
-            std::cout<<"Available cores: "<<util::join(f.get_names(), ", ")<<std::endl;
-            return 0;
-        } else if (isa_opt.find('|') != std::string::npos) {
-            std::tie(cpu, vm) = f.create(isa_opt+"|"+clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else {
-            auto base_isa = isa_opt.substr(0, 5);
-            if(base_isa=="tgc_d" || base_isa=="tgc_e") {
-                isa_opt += "|mu_p_clic_pmp|"+clim["backend"].as<std::string>();
-            } else {
-                isa_opt += "|m_p|"+clim["backend"].as<std::string>();
-            }
-            std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as<unsigned>());
+        if (isa_opt == "tgc_c") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_c_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#ifdef CORE_TGC_B
+        if (isa_opt == "tgc_b") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_C_XRB_NN
+        if (isa_opt == "tgc_c_xrb_nn") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_c_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_D
+        if (isa_opt == "tgc_d") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_d_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_D_XRB_MAC
+        if (isa_opt == "tgc_d_xrb_mac") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_d_xrb_mac_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_D_XRB_NN
+        if (isa_opt == "tgc_d_xrb_nn") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_d_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_E
+        if (isa_opt == "tgc_e") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_e_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+        {
+            LOG(ERR) << "Illegal argument value for '--isa': " << isa_opt << std::endl;
+            return 127;
         }
         if(!cpu ){
             LOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " <<clim["backend"].as<std::string>()<< std::endl;

src/sysc/register_tgc_c.cpp

@@ -1,33 +0,0 @@
-/*
- * register_tgc_c.cpp
- *
- *  Created on: Jul 5, 2023
- *      Author: eyck
- */
-
-
-
-
-#include <iss/factory.h>
-#include <iss/arch/tgc_c.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-#include "sc_core_adapter.h"
-#include "core_complex.h"
-
-namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            arch::tgc_c* lcpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
-            return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
-        }),
-        core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            arch::tgc_c* lcpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
-            return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
-        })
-};
-}
-}

src/sysc/sc_core_adapter.h

@@ -1,148 +0,0 @@
-/*
- * sc_core_adapter.h
- *
- *  Created on: Jul 5, 2023
- *      Author: eyck
- */
-
-#ifndef _SYSC_SC_CORE_ADAPTER_H_
-#define _SYSC_SC_CORE_ADAPTER_H_
-
-
-#include <scc/report.h>
-#include <util/ities.h>
-#include "core_complex.h"
-#include <iss/iss.h>
-#include <iss/vm_types.h>
-#include <iostream>
-
-
-template<typename PLAT>
-class sc_core_adapter : public PLAT {
-public:
-    using reg_t       = typename iss::arch::traits<typename PLAT::core>::reg_t;
-    using phys_addr_t = typename iss::arch::traits<typename PLAT::core>::phys_addr_t;
-    using heart_state_t = typename PLAT::hart_state_type;
-    sc_core_adapter(sysc::tgfs::core_complex *owner)
-    : owner(owner) { }
-
-    uint32_t get_mode() { return this->reg.PRIV; }
-
-    inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
-
-    inline bool get_interrupt_execution() { return this->interrupt_sim; }
-
-    heart_state_t &get_state() { return this->state; }
-
-    void notify_phase(iss::arch_if::exec_phase p) override {
-        if (p == iss::arch_if::ISTART)
-            owner->sync(this->instr_if.get_total_cycles());
-    }
-
-    iss::sync_type needed_sync() const override { return iss::PRE_SYNC; }
-
-    void disass_output(uint64_t pc, const std::string instr) override {
-        static constexpr std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
-        if (!owner->disass_output(pc, instr)) {
-            std::stringstream s;
-            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
-              << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
-              << this->reg.icount + this->cycle_offset << "]";
-            SCCDEBUG(owner->name())<<"disass: "
-                << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
-                << std::setfill(' ') << std::left << instr << s.str();
-        }
-    };
-
-    iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) override {
-        if (addr.access && iss::access_type::DEBUG)
-            return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
-        else {
-            return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? iss::Ok : iss::Err;
-        }
-    }
-
-    iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) override {
-        if (addr.access && iss::access_type::DEBUG)
-            return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
-        else {
-            auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
-            // clear MTIP on mtimecmp write
-            if (addr.val == 0x2004000) {
-                reg_t val;
-                this->read_csr(iss::arch::mip, val);
-                if (val & (1ULL << 7)) this->write_csr(iss::arch::mip, val & ~(1ULL << 7));
-            }
-            return res;
-        }
-    }
-
-    iss::status read_csr(unsigned addr, reg_t &val) override {
-#ifndef CWR_SYSTEMC
-        if((addr==iss::arch::time || addr==iss::arch::timeh) && owner->mtime_o.get_interface(0)){
-            uint64_t time_val;
-            bool ret = owner->mtime_o->nb_peek(time_val);
-            if (addr == iss::arch::time) {
-                val = static_cast<reg_t>(time_val);
-            } else if (addr == iss::arch::timeh) {
-                if (sizeof(reg_t) != 4) return iss::Err;
-                val = static_cast<reg_t>(time_val >> 32);
-            }
-            return ret?Ok:Err;
-#else
-        if((addr==iss::arch::time || addr==iss::arch::timeh)){
-            uint64_t time_val = owner->mtime_i.read();
-            if (addr == iss::arch::time) {
-                val = static_cast<reg_t>(time_val);
-            } else if (addr == iss::arch::timeh) {
-                if (sizeof(reg_t) != 4) return iss::Err;
-                val = static_cast<reg_t>(time_val >> 32);
-            }
-            return iss::Ok;
-#endif
-        } else {
-            return PLAT::read_csr(addr, val);
-        }
-    }
-
-    void wait_until(uint64_t flags) override {
-        SCCDEBUG(owner->name()) << "Sleeping until interrupt";
-        while(this->reg.pending_trap == 0 && (this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
-            sc_core::wait(wfi_evt);
-        }
-        PLAT::wait_until(flags);
-    }
-
-    void local_irq(short id, bool value) {
-        reg_t mask = 0;
-        switch (id) {
-        case 3: // SW
-            mask = 1 << 3;
-            break;
-        case 7: // timer
-            mask = 1 << 7;
-            break;
-        case 11: // external
-            mask = 1 << 11;
-            break;
-        default:
-            if(id>15) mask = 1 << id;
-            break;
-        }
-        if (value) {
-            this->csr[iss::arch::mip] |= mask;
-            wfi_evt.notify();
-        } else
-            this->csr[iss::arch::mip] &= ~mask;
-        this->check_interrupt();
-        if(value)
-            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
-    }
-
-private:
-    sysc::tgfs::core_complex *const owner;
-    sc_event wfi_evt;
-};
-
-
-#endif /* _SYSC_SC_CORE_ADAPTER_H_ */

src/vm/interp/vm_tgc_c.cpp

@@ -30,9 +30,10 @@
  *
  *******************************************************************************/
 
-#include <iss/arch/tgc_c.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
+#include <iss/arch/tgc_c.h>
+#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/iss.h>
 #include <iss/interp/vm_base.h>
 #include <util/logging.h>
@@ -388,7 +389,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = *PC + (int32_t)imm;
+                                        *(X+rd) = (uint32_t)(*PC + (int32_t)imm);
                                     }
                                 }
                             }
@@ -418,9 +419,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         if(rd !=  0) {
-                                            *(X+rd) = *PC +  4;
+                                            *(X+rd) = (uint32_t)(*PC +  4);
                                         }
-                                        *NEXT_PC = *PC + (int32_t)sext<21>(imm);
+                                        *NEXT_PC = (uint32_t)(*PC + (int32_t)sext<21>(imm));
                                         this->core.reg.last_branch = 1;
                                     }
                                 }
@@ -447,13 +448,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t new_pc = (*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 0x1;
+                                    uint32_t new_pc = (uint32_t)((*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 0x1);
                                     if(new_pc % traits::INSTR_ALIGNMENT) {
                                         raise(0,  0);
                                     }
                                     else {
                                         if(rd !=  0) {
-                                            *(X+rd) = *PC +  4;
+                                            *(X+rd) = (uint32_t)(*PC +  4);
                                         }
                                         *NEXT_PC = new_pc & ~ 0x1;
                                         this->core.reg.last_branch = 1;
@@ -487,7 +488,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
+                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -520,7 +521,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
+                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -553,7 +554,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
+                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -586,7 +587,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
+                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -619,7 +620,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
+                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -652,7 +653,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
+                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -680,7 +681,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
+                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
                                     int8_t read_res = super::template read_mem<int8_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LB;
                                     int8_t res = (int8_t)read_res;
@@ -711,7 +712,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
+                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
                                     int16_t read_res = super::template read_mem<int16_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LH;
                                     int16_t res = (int16_t)read_res;
@@ -742,7 +743,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
+                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
                                     int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LW;
                                     int32_t res = (int32_t)read_res;
@@ -773,10 +774,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
+                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
                                     uint8_t read_res = super::template read_mem<uint8_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LBU;
-                                    uint8_t res = (uint8_t)read_res;
+                                    uint8_t res = read_res;
                                     if(rd !=  0) {
                                         *(X+rd) = (uint32_t)res;
                                     }
@@ -804,10 +805,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
+                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
                                     uint16_t read_res = super::template read_mem<uint16_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LHU;
-                                    uint16_t res = (uint16_t)read_res;
+                                    uint16_t res = read_res;
                                     if(rd !=  0) {
                                         *(X+rd) = (uint32_t)res;
                                     }
@@ -835,8 +836,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
-                                    super::template write_mem<uint8_t>(traits::MEM, store_address, (int8_t)*(X+rs2));
+                                    uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                    super::template write_mem<uint8_t>(traits::MEM, store_address, (uint8_t)*(X+rs2));
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_SB;
                                 }
                             }
@@ -862,8 +863,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
-                                    super::template write_mem<uint16_t>(traits::MEM, store_address, (int16_t)*(X+rs2));
+                                    uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                    super::template write_mem<uint16_t>(traits::MEM, store_address, (uint16_t)*(X+rs2));
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_SH;
                                 }
                             }
@@ -889,8 +890,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
-                                    super::template write_mem<uint32_t>(traits::MEM, store_address, (int32_t)*(X+rs2));
+                                    uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                    super::template write_mem<uint32_t>(traits::MEM, store_address, (uint32_t)*(X+rs2));
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_SW;
                                 }
                             }
@@ -917,7 +918,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = *(X+rs1) + (int16_t)sext<12>(imm);
+                                        *(X+rd) = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
                                     }
                                 }
                             }
@@ -1133,7 +1134,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = (int32_t)*(X+rs1) >> shamt;
+                                        *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt);
                                     }
                                 }
                             }
@@ -1160,7 +1161,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = *(X+rs1) + *(X+rs2);
+                                        *(X+rd) = (uint32_t)(*(X+rs1) + *(X+rs2));
                                     }
                                 }
                             }
@@ -1187,7 +1188,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = *(X+rs1) - *(X+rs2);
+                                        *(X+rd) = (uint32_t)(*(X+rs1) - *(X+rs2));
                                     }
                                 }
                             }
@@ -1349,7 +1350,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = (int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN -  1));
+                                        *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN -  1)));
                                     }
                                 }
                             }
@@ -1426,7 +1427,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
-                                super::template write_mem<uint8_t>(traits::FENCE, traits::fence, pred <<  4 | succ);
+                                super::template write_mem<uint32_t>(traits::FENCE, traits::fence, (uint8_t)pred <<  4 | succ);
                                 if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_FENCE;
                             }
                 TRAP_FENCE:break;
@@ -1705,7 +1706,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
-                                super::template write_mem<uint16_t>(traits::FENCE, traits::fencei, imm);
+                                super::template write_mem<uint32_t>(traits::FENCE, traits::fencei, imm);
                                 if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_FENCE_I;
                             }
                 TRAP_FENCE_I:break;
@@ -1730,7 +1731,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
+                                    int64_t res = (int32_t)*(X+rs1) * (int32_t)*(X+rs2);
                                     if(rd != 0) {
                                         *(X+rd) = (uint32_t)res;
                                     }
@@ -1758,7 +1759,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
+                                    int64_t res = (int32_t)*(X+rs1) * (int32_t)*(X+rs2);
                                     if(rd != 0) {
                                         *(X+rd) = (uint32_t)(res >> traits::XLEN);
                                     }
@@ -1786,7 +1787,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    int64_t res = (int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2);
+                                    int64_t res = (int32_t)*(X+rs1) * *(X+rs2);
                                     if(rd != 0) {
                                         *(X+rd) = (uint32_t)(res >> traits::XLEN);
                                     }
@@ -1814,7 +1815,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint64_t res = (uint64_t)*(X+rs1) * (uint64_t)*(X+rs2);
+                                    uint64_t res = *(X+rs1) * *(X+rs2);
                                     if(rd != 0) {
                                         *(X+rd) = (uint32_t)(res >> traits::XLEN);
                                     }
@@ -1851,11 +1852,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                                 *(X+rd) = MMIN;
                                             }
                                             else {
-                                                *(X+rd) = dividend / divisor;
+                                                *(X+rd) = (uint32_t)(dividend / divisor);
                                             }
                                         }
                                         else {
-                                            *(X+rd) = (int32_t)- 1;
+                                            *(X+rd) = (uint32_t)- 1;
                                         }
                                     }
                                 }
@@ -1884,12 +1885,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 else {
                                     if(*(X+rs2) !=  0) {
                                         if(rd != 0) {
-                                            *(X+rd) = *(X+rs1) / *(X+rs2);
+                                            *(X+rd) = (uint32_t)(*(X+rs1) / *(X+rs2));
                                         }
                                     }
                                     else {
                                         if(rd != 0) {
-                                            *(X+rd) = (int32_t)- 1;
+                                            *(X+rd) = (uint32_t)- 1;
                                         }
                                     }
                                 }
@@ -1925,7 +1926,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         }
                                         else {
                                             if(rd != 0) {
-                                                *(X+rd) = (int32_t)*(X+rs1) % (int32_t)*(X+rs2);
+                                                *(X+rd) = (uint32_t)((int32_t)*(X+rs1) % (int32_t)*(X+rs2));
                                             }
                                         }
                                     }
@@ -1979,7 +1980,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     /* generate console output when executing the command */
                     auto mnemonic = fmt::format(
                         "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "caddi4spn"),
-                        fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+                        fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
@@ -1988,7 +1989,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                                 if(imm) {
-                                    *(X+rd +  8) = *(X+2) + imm;
+                                    *(X+rd +  8) = (uint32_t)(*(X+2) + imm);
                                 }
                                 else {
                                     raise(0,  2);
@@ -2012,10 +2013,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    uint32_t load_address = *(X+rs1 +  8) + uimm;
+                    uint32_t load_address = (uint32_t)(*(X+rs1 +  8) + uimm);
                     int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address);
                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CLW;
-                    *(X+rd +  8) = (int32_t)read_res;
+                    *(X+rd +  8) = (uint32_t)(int32_t)read_res;
                 }
                 TRAP_CLW:break;
             }// @suppress("No break at end of case")
@@ -2035,8 +2036,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    uint32_t load_address = *(X+rs1 +  8) + uimm;
-                    super::template write_mem<uint32_t>(traits::MEM, load_address, (int32_t)*(X+rs2 +  8));
+                    uint32_t load_address = (uint32_t)(*(X+rs1 +  8) + uimm);
+                    super::template write_mem<uint32_t>(traits::MEM, load_address, (uint32_t)*(X+rs2 +  8));
                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CSW;
                 }
                 TRAP_CSW:break;
@@ -2061,7 +2062,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rs1 !=  0) {
-                                        *(X+rs1) = *(X+rs1) + (int8_t)sext<6>(imm);
+                                        *(X+rs1) = (uint32_t)(*(X+rs1) + (int8_t)sext<6>(imm));
                                     }
                                 }
                             }
@@ -2094,8 +2095,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    *(X+1) = *PC +  2;
-                    *NEXT_PC = *PC + (int16_t)sext<12>(imm);
+                    *(X+1) = (uint32_t)(*PC +  2);
+                    *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<12>(imm));
                     this->core.reg.last_branch = 1;
                 }
                 TRAP_CJAL:break;
@@ -2120,7 +2121,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = (int8_t)sext<6>(imm);
+                                        *(X+rd) = (uint32_t)((int8_t)sext<6>(imm));
                                     }
                                 }
                             }
@@ -2145,7 +2146,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         raise(0,  2);
                     }
                     if(rd !=  0) {
-                        *(X+rd) = (int32_t)sext<18>(imm);
+                        *(X+rd) = (uint32_t)((int32_t)sext<18>(imm));
                     }
                 }
                 TRAP_CLUI:break;
@@ -2165,7 +2166,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                                 if(nzimm) {
-                                    *(X+2) = *(X+2) + (int16_t)sext<10>(nzimm);
+                                    *(X+2) = (uint32_t)(*(X+2) + (int16_t)sext<10>(nzimm));
                                 }
                                 else {
                                     raise(0,  2);
@@ -2222,11 +2223,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                     if(shamt) {
-                        *(X+rs1 +  8) = ((int32_t)*(X+rs1 +  8)) >> shamt;
+                        *(X+rs1 +  8) = (uint32_t)(((int32_t)*(X+rs1 +  8)) >> shamt);
                     }
                     else {
                         if(traits::XLEN ==  128) {
-                            *(X+rs1 +  8) = ((int32_t)*(X+rs1 +  8)) >>  64;
+                            *(X+rs1 +  8) = (uint32_t)(((int32_t)*(X+rs1 +  8)) >>  64);
                         }
                     }
                 }
@@ -2247,7 +2248,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    *(X+rs1 +  8) = *(X+rs1 +  8) & (int8_t)sext<6>(imm);
+                    *(X+rs1 +  8) = (uint32_t)(*(X+rs1 +  8) & (int8_t)sext<6>(imm));
                 }
                 TRAP_CANDI:break;
             }// @suppress("No break at end of case")
@@ -2266,7 +2267,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    *(X+rd +  8) = *(X+rd +  8) - *(X+rs2 +  8);
+                    *(X+rd +  8) = (uint32_t)(*(X+rd +  8) - *(X+rs2 +  8));
                 }
                 TRAP_CSUB:break;
             }// @suppress("No break at end of case")
@@ -2340,7 +2341,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                                *NEXT_PC = *PC + (int16_t)sext<12>(imm);
+                                *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<12>(imm));
                                 this->core.reg.last_branch = 1;
                             }
                 TRAP_CJ:break;
@@ -2361,7 +2362,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                                 if(*(X+rs1 +  8) ==  0) {
-                                    *NEXT_PC = *PC + (int16_t)sext<9>(imm);
+                                    *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<9>(imm));
                                     this->core.reg.last_branch = 1;
                                 }
                             }
@@ -2383,7 +2384,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                                 if(*(X+rs1 +  8) !=  0) {
-                                    *NEXT_PC = *PC + (int16_t)sext<9>(imm);
+                                    *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<9>(imm));
                                     this->core.reg.last_branch = 1;
                                 }
                             }
@@ -2434,10 +2435,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         raise(0,  2);
                     }
                     else {
-                        int32_t read_res = super::template read_mem<int32_t>(traits::MEM, *(X+2) + uimm);
+                        uint32_t offs = (uint32_t)(*(X+2) + uimm);
+                        int32_t read_res = super::template read_mem<int32_t>(traits::MEM, offs);
                         if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CLWSP;
-                        int32_t res = read_res;
-                        *(X+rd) = (int32_t)res;
+                        int32_t res = (int32_t)read_res;
+                        *(X+rd) = (uint32_t)res;
                     }
                 }
                 TRAP_CLWSP:break;
@@ -2525,7 +2527,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = *(X+rd) + *(X+rs2);
+                                        *(X+rd) = (uint32_t)(*(X+rd) + *(X+rs2));
                                     }
                                 }
                             }
@@ -2550,7 +2552,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     uint32_t new_pc = *(X+rs1);
-                                    *(X+1) = *PC +  2;
+                                    *(X+1) = (uint32_t)(*PC +  2);
                                     *NEXT_PC = new_pc & ~ 0x1;
                                     this->core.reg.last_branch = 1;
                                 }
@@ -2589,7 +2591,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t offs = *(X+2) + uimm;
+                                    uint32_t offs = (uint32_t)(*(X+2) + uimm);
                                     super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2));
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CSWSP;
                                 }
@@ -2645,21 +2647,3 @@ std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short por
 }
 } // namespace interp
 } // namespace iss
-
-#include <iss/factory.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned gdb_port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            arch::tgc_c* lcpu = new arch::riscv_hart_m_p<arch::tgc_c>();
-            return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
-        }),
-        core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned gdb_port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            arch::tgc_c* lcpu = new arch::riscv_hart_mu_p<arch::tgc_c>();
-            return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
-        })
-};
-}
-}