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base: DBT-RISE:edf456c59f9e5a7f69966e4ea6f2583d16ca3719
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DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
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compare: DBT-RISE:6ddb8da07ff815370b92550c1bd6752579bf41e5
Branches Tags
DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

1 Commits
edf456c59f ... 6ddb8da07f

Author SHA1 Message Date
Eyck Jentzsch
6ddb8da07f fixes missing rename 2024-08-02 11:58:51 +02:00
1 changed files with 4 additions and 4 deletions
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8
src/iss/arch/hwl.h
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@@ -51,8 +51,8 @@ public:
virtual ~hwl() = default; virtual ~hwl() = default;
protected: protected:
iss::status read_custom_csr_reg(unsigned addr, reg_t& val) override; iss::status read_custom_csr(unsigned addr, reg_t& val) override;
iss::status write_custom_csr_reg(unsigned addr, reg_t val) override; iss::status write_custom_csr(unsigned addr, reg_t val) override;
}; };
template <typename BASE> template <typename BASE>
@@ -68,7 +68,7 @@ inline hwl<BASE>::hwl(feature_config cfg)
} }
} }
template <typename BASE> inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t& val) { template <typename BASE> inline iss::status iss::arch::hwl<BASE>::read_custom_csr(unsigned addr, reg_t& val) {
switch(addr) { switch(addr) {
case 0x800: case 0x800:
val = this->reg.lpstart0; val = this->reg.lpstart0;
@@ -92,7 +92,7 @@ template <typename BASE> inline iss::status iss::arch::hwl<BASE>::read_custom_cs
return iss::Ok; return iss::Ok;
} }
template <typename BASE> inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) { template <typename BASE> inline iss::status iss::arch::hwl<BASE>::write_custom_csr(unsigned addr, reg_t val) {
switch(addr) { switch(addr) {
case 0x800: case 0x800:
this->reg.lpstart0 = val; this->reg.lpstart0 = val;