adds tracing functionality

CMakeLists.txt

@@ -80,7 +80,9 @@ target_force_link_libraries(${PROJECT_NAME} PRIVATE dbt-rise-core)
 get_target_property(DBT_CORE_INCL dbt-rise-core INTERFACE_INCLUDE_DIRECTORIES)
 target_include_directories(${PROJECT_NAME} INTERFACE ${DBT_CORE_INCL})
 get_target_property(DBT_CORE_DEFS dbt-rise-core INTERFACE_COMPILE_DEFINITIONS)
-target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
+if(NOT (DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND))
+	target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
+endif()
 
 target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine)
 if(TARGET jsoncpp::jsoncpp)

gen_input/templates/CORENAME.h.gtl

@@ -76,10 +76,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
     constexpr static char const* const core_type = "${coreDef.name}";
     
     static constexpr std::array<const char*, ${registers.size}> reg_names{
-        {"${registers.collect{it.name}.join('", "')}"}};
+        {"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
  
     static constexpr std::array<const char*, ${registers.size}> reg_aliases{
-        {"${registers.collect{it.alias}.join('", "')}"}};
+        {"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};
 
     enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
 

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -159,6 +159,7 @@ private:
     compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("${instr.name}_{:#010x}:", pc.val);
         vm_base<ARCH>::gen_sync(tu, PRE_SYNC,${idx});
+        uint64_t PC = pc.val;
         <%instr.fields.eachLine{%>${it}
         <%}%>if(this->disass_enabled){
             /* generate console output when executing the command */<%instr.disass.eachLine{%>

src/iss/arch/riscv_hart_m_p.h

@@ -304,9 +304,9 @@ protected:
          */
         const std::string core_type_name() const override { return traits<BASE>::core_type; }
 
-        uint64_t get_pc() override { return arch.reg.PC; };
+        uint64_t get_pc() override { return arch.reg.PC; }
 
-        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
+        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }
 
         uint64_t get_instr_word() override { return arch.reg.instruction; }
 
@@ -316,9 +316,11 @@ protected:
 
         uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
 
-        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
 
-        bool is_branch_taken() override { return arch.reg.last_branch; };
+        bool is_branch_taken() override { return arch.reg.last_branch; }
+
+        unsigned get_reg_num() override {return traits<BASE>::NUM_REGS;}
 
         riscv_hart_m_p<BASE, FEAT> &arch;
     };

src/iss/arch/riscv_hart_msu_vp.h

@@ -331,9 +331,9 @@ protected:
          */
         const std::string core_type_name() const override { return traits<BASE>::core_type; }
 
-        uint64_t get_pc() override { return arch.reg.PC; };
+        uint64_t get_pc() override { return arch.reg.PC; }
 
-        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
+        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }
 
         uint64_t get_instr_word() override { return arch.reg.instruction; }
 
@@ -343,9 +343,11 @@ protected:
 
         uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
 
-        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
 
-        bool is_branch_taken() override { return arch.reg.last_branch; };
+        bool is_branch_taken() override { return arch.reg.last_branch; }
+
+        unsigned get_reg_num() override {return traits<BASE>::NUM_REGS; }
 
         riscv_hart_msu_vp<BASE> &arch;
     };

src/iss/arch/riscv_hart_mu_p.h

@@ -329,9 +329,9 @@ protected:
          */
         const std::string core_type_name() const override { return traits<BASE>::core_type; }
 
-        uint64_t get_pc() override { return arch.reg.PC; };
+        uint64_t get_pc() override { return arch.reg.PC; }
 
-        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
+        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }
 
         uint64_t get_instr_word() override { return arch.reg.instruction; }
 
@@ -341,9 +341,11 @@ protected:
 
         uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
 
-        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
 
-        bool is_branch_taken() override { return arch.reg.last_branch; };
+        bool is_branch_taken() override { return arch.reg.last_branch; }
+
+        unsigned get_reg_num() override {return traits<BASE>::NUM_REGS; }
 
         riscv_hart_mu_p<BASE, FEAT> &arch;
     };

src/iss/arch/tgc5c.h

@@ -48,10 +48,10 @@ template <> struct traits<tgc5c> {
     constexpr static char const* const core_type = "TGC5C";
     
     static constexpr std::array<const char*, 36> reg_names{
-        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
+        {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}};
  
     static constexpr std::array<const char*, 36> reg_aliases{
-        {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
+        {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}};
 
     enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, XLEN=32ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL};
 
@@ -141,35 +141,35 @@ template <> struct traits<tgc5c> {
         DIVU = 54,
         REM = 55,
         REMU = 56,
-        CADDI4SPN = 57,
-        CLW = 58,
-        CSW = 59,
-        CADDI = 60,
-        CNOP = 61,
-        CJAL = 62,
-        CLI = 63,
-        CLUI = 64,
-        CADDI16SP = 65,
+        C__ADDI4SPN = 57,
+        C__LW = 58,
+        C__SW = 59,
+        C__ADDI = 60,
+        C__NOP = 61,
+        C__JAL = 62,
+        C__LI = 63,
+        C__LUI = 64,
+        C__ADDI16SP = 65,
         __reserved_clui = 66,
-        CSRLI = 67,
-        CSRAI = 68,
-        CANDI = 69,
-        CSUB = 70,
-        CXOR = 71,
-        COR = 72,
-        CAND = 73,
-        CJ = 74,
-        CBEQZ = 75,
-        CBNEZ = 76,
-        CSLLI = 77,
-        CLWSP = 78,
-        CMV = 79,
-        CJR = 80,
+        C__SRLI = 67,
+        C__SRAI = 68,
+        C__ANDI = 69,
+        C__SUB = 70,
+        C__XOR = 71,
+        C__OR = 72,
+        C__AND = 73,
+        C__J = 74,
+        C__BEQZ = 75,
+        C__BNEZ = 76,
+        C__SLLI = 77,
+        C__LWSP = 78,
+        C__MV = 79,
+        C__JR = 80,
         __reserved_cmv = 81,
-        CADD = 82,
-        CJALR = 83,
-        CEBREAK = 84,
-        CSWSP = 85,
+        C__ADD = 82,
+        C__JALR = 83,
+        C__EBREAK = 84,
+        C__SWSP = 85,
         DII = 86,
         MAX_OPCODE
     };

src/iss/plugin/README.md

@@ -0,0 +1,8 @@
+# pctrace
+
+Trace functionality to allow visualizing coverage in lcov and cachegrind tools. Use environment variables NOCOMPRES and REGDUMP to toggle functionality.
+- NOCOMPRES: any value turns off the LZ4 compression
+- REGDUMP: any value switches to tracing the registers instead. Also turns off compression.
+
+Known Bugs: 
+- currently does not work correctly with jit backends, the plugin cant tell if instructions are compressed. Additionaly the cost of instrs that raise a trap is not known. It takes the cost of the instrid -1 (0 at the moment).

src/iss/plugin/pctrace.cpp

@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  * Contributors:
- *       alex.com - initial implementation
+ *       alex@minres.com - initial implementation
  ******************************************************************************/
 
 #include <iss/arch_if.h>
@@ -55,11 +55,11 @@ using namespace rapidjson;
 using namespace std;
 
 #ifdef WITH_LZ4
-class lz4compress_steambuf: public std::streambuf {
+class lz4compress_streambuf: public std::streambuf {
 public:
-    lz4compress_steambuf(const lz4compress_steambuf&) = delete;
-    lz4compress_steambuf& operator=(const lz4compress_steambuf&) = delete;
-    lz4compress_steambuf(std::ostream &sink, size_t buf_size)
+    lz4compress_streambuf(const lz4compress_streambuf&) = delete;
+    lz4compress_streambuf& operator=(const lz4compress_streambuf&) = delete;
+    lz4compress_streambuf(std::ostream &sink, size_t buf_size)
     : sink(sink)
     , src_buf(buf_size)
     , dest_buf(LZ4F_compressBound(buf_size, nullptr))
@@ -74,7 +74,7 @@ public:
         sink.write(dest_buf.data(), ret);
     }
 
-    ~lz4compress_steambuf() {
+    ~lz4compress_streambuf() {
         close();
     }
 
@@ -126,17 +126,21 @@ private:
 pctrace::pctrace(std::string const &filename)
 : instr_if(nullptr)
 , filename(filename)
+, reg_dump(getenv("REGDUMP"))
+, no_compres(getenv("NOCOMPRES"))
 , output("output.trc")
 #ifdef WITH_LZ4
-, strbuf(new lz4compress_steambuf(output, 4096))
+, strbuf( (no_compres || reg_dump)? nullptr: new lz4compress_streambuf(output, 4096))
 , ostr(strbuf.get())
 #endif
-{ }
+{}
 
 pctrace::~pctrace() { }
 
 bool pctrace::registration(const char *const version, vm_if& vm) {
     instr_if = vm.get_arch()->get_instrumentation_if();
+    reg_base_ptr = reinterpret_cast<uint32_t*>(vm.get_arch()->get_regs_base_ptr());
+
     if(!instr_if) return false;
     const string  core_name = instr_if->core_type_name();
     if (filename.length() > 0) {
@@ -203,12 +207,22 @@ void pctrace::callback(instr_info_t iinfo) {
         if (entry.not_taken > 1)
             instr_if->update_last_instr_cycles(entry.not_taken);
     }
-#ifndef WITH_LZ4
-    output<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
-#else
-    auto rdbuf=ostr.rdbuf();
-    ostr<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
-#endif
-}
-}
+    if(no_compres|| reg_dump){
+        if(reg_dump){
+            for(size_t i=0; i< instr_if->get_reg_num(); ++i){
+                uint32_t reg_val = *(reg_base_ptr+i);
+                output << "0x" << std::setfill('0') << std::setw(8) << std::hex << reg_val << " ";
+            }
+            output<<"\n" ;
+        }
+        else{
+             output<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<std::endl;
+        }
+        
+    }else{
+        
+        ostr<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
+    }
 }
+}//namespace plugin
+}//namespace iss

src/iss/plugin/pctrace.h

@@ -39,11 +39,10 @@
 #include "iss/instrumentation_if.h"
 #include <string>
 #include <fstream>
-
-
+#include <cstdlib>
 namespace iss {
 namespace plugin {
-class lz4compress_steambuf;
+class lz4compress_streambuf;
 class pctrace : public iss::vm_plugin {
     struct instr_delay {
         std::string instr_name;
@@ -86,9 +85,13 @@ public:
 
 private:
     iss::instrumentation_if *instr_if  {nullptr};
+    uint32_t* reg_base_ptr {nullptr};
+    bool reg_dump {false};
+    bool no_compres {false};   
     std::ofstream output;
+
 #ifdef WITH_LZ4
-    std::unique_ptr<lz4compress_steambuf> strbuf;
+    std::unique_ptr<lz4compress_streambuf> strbuf;
     std::ostream ostr;
 #endif
     std::string filename;

src/vm/interp/vm_tgc5c.cpp

@@ -210,35 +210,35 @@ private:
         {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::DIVU},
         {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::REM},
         {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::REMU},
-        {16, 0b0000000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CADDI4SPN},
-        {16, 0b0100000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLW},
-        {16, 0b1100000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CSW},
-        {16, 0b0000000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CADDI},
-        {16, 0b0000000000000001, 0b1110111110000011, arch::traits<ARCH>::opcode_e::CNOP},
-        {16, 0b0010000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CJAL},
-        {16, 0b0100000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLI},
-        {16, 0b0110000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLUI},
-        {16, 0b0110000100000001, 0b1110111110000011, arch::traits<ARCH>::opcode_e::CADDI16SP},
+        {16, 0b0000000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__ADDI4SPN},
+        {16, 0b0100000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__LW},
+        {16, 0b1100000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__SW},
+        {16, 0b0000000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__ADDI},
+        {16, 0b0000000000000001, 0b1110111110000011, arch::traits<ARCH>::opcode_e::C__NOP},
+        {16, 0b0010000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__JAL},
+        {16, 0b0100000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__LI},
+        {16, 0b0110000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__LUI},
+        {16, 0b0110000100000001, 0b1110111110000011, arch::traits<ARCH>::opcode_e::C__ADDI16SP},
         {16, 0b0110000000000001, 0b1111000001111111, arch::traits<ARCH>::opcode_e::__reserved_clui},
-        {16, 0b1000000000000001, 0b1111110000000011, arch::traits<ARCH>::opcode_e::CSRLI},
-        {16, 0b1000010000000001, 0b1111110000000011, arch::traits<ARCH>::opcode_e::CSRAI},
-        {16, 0b1000100000000001, 0b1110110000000011, arch::traits<ARCH>::opcode_e::CANDI},
-        {16, 0b1000110000000001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::CSUB},
-        {16, 0b1000110000100001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::CXOR},
-        {16, 0b1000110001000001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::COR},
-        {16, 0b1000110001100001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::CAND},
-        {16, 0b1010000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CJ},
-        {16, 0b1100000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CBEQZ},
-        {16, 0b1110000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CBNEZ},
-        {16, 0b0000000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::CSLLI},
-        {16, 0b0100000000000010, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLWSP},
-        {16, 0b1000000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::CMV},
-        {16, 0b1000000000000010, 0b1111000001111111, arch::traits<ARCH>::opcode_e::CJR},
+        {16, 0b1000000000000001, 0b1111110000000011, arch::traits<ARCH>::opcode_e::C__SRLI},
+        {16, 0b1000010000000001, 0b1111110000000011, arch::traits<ARCH>::opcode_e::C__SRAI},
+        {16, 0b1000100000000001, 0b1110110000000011, arch::traits<ARCH>::opcode_e::C__ANDI},
+        {16, 0b1000110000000001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::C__SUB},
+        {16, 0b1000110000100001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::C__XOR},
+        {16, 0b1000110001000001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::C__OR},
+        {16, 0b1000110001100001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::C__AND},
+        {16, 0b1010000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__J},
+        {16, 0b1100000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__BEQZ},
+        {16, 0b1110000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__BNEZ},
+        {16, 0b0000000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::C__SLLI},
+        {16, 0b0100000000000010, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__LWSP},
+        {16, 0b1000000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::C__MV},
+        {16, 0b1000000000000010, 0b1111000001111111, arch::traits<ARCH>::opcode_e::C__JR},
         {16, 0b1000000000000010, 0b1111111111111111, arch::traits<ARCH>::opcode_e::__reserved_cmv},
-        {16, 0b1001000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::CADD},
-        {16, 0b1001000000000010, 0b1111000001111111, arch::traits<ARCH>::opcode_e::CJALR},
-        {16, 0b1001000000000010, 0b1111111111111111, arch::traits<ARCH>::opcode_e::CEBREAK},
-        {16, 0b1100000000000010, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CSWSP},
+        {16, 0b1001000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::C__ADD},
+        {16, 0b1001000000000010, 0b1111000001111111, arch::traits<ARCH>::opcode_e::C__JALR},
+        {16, 0b1001000000000010, 0b1111111111111111, arch::traits<ARCH>::opcode_e::C__EBREAK},
+        {16, 0b1100000000000010, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__SWSP},
         {16, 0b0000000000000000, 0b1111111111111111, arch::traits<ARCH>::opcode_e::DII},
     }};
 
@@ -485,7 +485,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0,  2);
                                     }
                                     else {
-                                        uint32_t new_pc = (uint32_t)((*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 0x1);
+                                        uint32_t addr_mask = (uint32_t)- 2;
+                                        uint32_t new_pc = (uint32_t)((*(X+rs1) + (int16_t)sext<12>(imm)) & addr_mask);
                                         if(new_pc % traits::INSTR_ALIGNMENT) {
                                             raise(0,  0);
                                         }
@@ -493,7 +494,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             if(rd !=  0) {
                                                 *(X+rd) = (uint32_t)(*PC +  4);
                                             }
-                                            *NEXT_PC = new_pc & ~ 0x1;
+                                            *NEXT_PC = new_pc;
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -719,9 +720,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
-                                        int8_t read_res = super::template read_mem<int8_t>(traits::MEM, load_address);
+                                        int8_t res_27 = super::template read_mem<int8_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        int8_t res = (int8_t)read_res;
+                                        int8_t res = (int8_t)res_27;
                                         if(rd !=  0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -750,9 +751,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
-                                        int16_t read_res = super::template read_mem<int16_t>(traits::MEM, load_address);
+                                        int16_t res_28 = super::template read_mem<int16_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        int16_t res = (int16_t)read_res;
+                                        int16_t res = (int16_t)res_28;
                                         if(rd !=  0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -781,9 +782,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
-                                        int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address);
+                                        int32_t res_29 = super::template read_mem<int32_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        int32_t res = (int32_t)read_res;
+                                        int32_t res = (int32_t)res_29;
                                         if(rd !=  0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -812,9 +813,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
-                                        uint8_t read_res = super::template read_mem<uint8_t>(traits::MEM, load_address);
+                                        uint8_t res_30 = super::template read_mem<uint8_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint8_t res = read_res;
+                                        uint8_t res = res_30;
                                         if(rd !=  0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -843,9 +844,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
-                                        uint16_t read_res = super::template read_mem<uint16_t>(traits::MEM, load_address);
+                                        uint16_t res_31 = super::template read_mem<uint16_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint16_t res = read_res;
+                                        uint16_t res = res_31;
                                         if(rd !=  0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -1543,9 +1544,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     else {
                                         uint32_t xrs1 = *(X+rs1);
                                         if(rd !=  0) {
-                                            uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                            uint32_t res_32 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                            uint32_t xrd = read_res;
+                                            uint32_t xrd = res_32;
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrs1);
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                             *(X+rd) = xrd;
@@ -1578,9 +1579,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0,  2);
                                     }
                                     else {
-                                        uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_33 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = read_res;
+                                        uint32_t xrd = res_33;
                                         uint32_t xrs1 = *(X+rs1);
                                         if(rs1 !=  0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd | xrs1);
@@ -1613,9 +1614,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0,  2);
                                     }
                                     else {
-                                        uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_34 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = read_res;
+                                        uint32_t xrd = res_34;
                                         uint32_t xrs1 = *(X+rs1);
                                         if(rs1 !=  0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ xrs1);
@@ -1648,9 +1649,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0,  2);
                                     }
                                     else {
-                                        uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_35 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = read_res;
+                                        uint32_t xrd = res_35;
                                         super::template write_mem<uint32_t>(traits::CSR, csr, (uint32_t)zimm);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         if(rd !=  0) {
@@ -1680,9 +1681,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0,  2);
                                     }
                                     else {
-                                        uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_36 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = read_res;
+                                        uint32_t xrd = res_36;
                                         if(zimm !=  0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd | (uint32_t)zimm);
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
@@ -1714,9 +1715,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0,  2);
                                     }
                                     else {
-                                        uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
+                                        uint32_t res_37 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        uint32_t xrd = read_res;
+                                        uint32_t xrd = res_37;
                                         if(zimm !=  0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ ((uint32_t)zimm));
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
@@ -1955,7 +1956,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         if(*(X+rs2) !=  0) {
-                                            uint32_t MMIN =  1 << (traits::XLEN - 1);
+                                            uint32_t MMIN = (uint32_t)1 << (traits::XLEN - 1);
                                             if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) {
                                                 if(rd != 0) {
                                                     *(X+rd) =  0;
@@ -2010,13 +2011,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CADDI4SPN: {
+                case arch::traits<ARCH>::opcode_e::C__ADDI4SPN: {
                     uint8_t rd = ((bit_sub<2,3>(instr)));
                     uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "caddi4spn"),
+                            "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"),
                             fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2034,14 +2035,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CLW: {
+                case arch::traits<ARCH>::opcode_e::C__LW: {
                     uint8_t rd = ((bit_sub<2,3>(instr)));
                     uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
                     uint8_t rs1 = ((bit_sub<7,3>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "clw"),
+                            "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"),
                             fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2051,20 +2052,20 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                         uint32_t offs = (uint32_t)(*(X+rs1 +  8) + uimm);
-                        int32_t read_res = super::template read_mem<int32_t>(traits::MEM, offs);
+                        int32_t res_38 = super::template read_mem<int32_t>(traits::MEM, offs);
                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                        *(X+rd +  8) = (uint32_t)(int32_t)read_res;
+                        *(X+rd +  8) = (uint32_t)(int32_t)res_38;
                     }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CSW: {
+                case arch::traits<ARCH>::opcode_e::C__SW: {
                     uint8_t rs2 = ((bit_sub<2,3>(instr)));
                     uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
                     uint8_t rs1 = ((bit_sub<7,3>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "csw"),
+                            "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"),
                             fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2079,13 +2080,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CADDI: {
+                case arch::traits<ARCH>::opcode_e::C__ADDI: {
                     uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
                     uint8_t rs1 = ((bit_sub<7,5>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "caddi"),
+                            "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"),
                             fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2105,11 +2106,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CNOP: {
+                case arch::traits<ARCH>::opcode_e::C__NOP: {
                     uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
-                        this->core.disass_output(pc.val, "cnop");
+                        this->core.disass_output(pc.val, "c__nop");
                     }
                     // used registers// calculate next pc value
                     *NEXT_PC = *PC + 2;
@@ -2118,12 +2119,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CJAL: {
+                case arch::traits<ARCH>::opcode_e::C__JAL: {
                     uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cjal"),
+                            "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.jal"),
                             fmt::arg("imm", imm));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2138,13 +2139,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CLI: {
+                case arch::traits<ARCH>::opcode_e::C__LI: {
                     uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
                     uint8_t rd = ((bit_sub<7,5>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "cli"),
+                            "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"),
                             fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2164,13 +2165,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CLUI: {
+                case arch::traits<ARCH>::opcode_e::C__LUI: {
                     uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17));
                     uint8_t rd = ((bit_sub<7,5>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "clui"),
+                            "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"),
                             fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2188,12 +2189,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CADDI16SP: {
+                case arch::traits<ARCH>::opcode_e::C__ADDI16SP: {
                     uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "caddi16sp"),
+                            "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c.addi16sp"),
                             fmt::arg("nzimm", nzimm));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2225,13 +2226,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CSRLI: {
+                case arch::traits<ARCH>::opcode_e::C__SRLI: {
                     uint8_t shamt = ((bit_sub<2,5>(instr)));
                     uint8_t rs1 = ((bit_sub<7,3>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrli"),
+                            "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"),
                             fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2244,13 +2245,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CSRAI: {
+                case arch::traits<ARCH>::opcode_e::C__SRAI: {
                     uint8_t shamt = ((bit_sub<2,5>(instr)));
                     uint8_t rs1 = ((bit_sub<7,3>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrai"),
+                            "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"),
                             fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2270,13 +2271,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CANDI: {
+                case arch::traits<ARCH>::opcode_e::C__ANDI: {
                     uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
                     uint8_t rs1 = ((bit_sub<7,3>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "candi"),
+                            "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"),
                             fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2289,13 +2290,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CSUB: {
+                case arch::traits<ARCH>::opcode_e::C__SUB: {
                     uint8_t rs2 = ((bit_sub<2,3>(instr)));
                     uint8_t rd = ((bit_sub<7,3>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "csub"),
+                            "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"),
                             fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2308,13 +2309,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CXOR: {
+                case arch::traits<ARCH>::opcode_e::C__XOR: {
                     uint8_t rs2 = ((bit_sub<2,3>(instr)));
                     uint8_t rd = ((bit_sub<7,3>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cxor"),
+                            "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"),
                             fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2327,13 +2328,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::COR: {
+                case arch::traits<ARCH>::opcode_e::C__OR: {
                     uint8_t rs2 = ((bit_sub<2,3>(instr)));
                     uint8_t rd = ((bit_sub<7,3>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cor"),
+                            "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"),
                             fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2346,13 +2347,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CAND: {
+                case arch::traits<ARCH>::opcode_e::C__AND: {
                     uint8_t rs2 = ((bit_sub<2,3>(instr)));
                     uint8_t rd = ((bit_sub<7,3>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cand"),
+                            "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"),
                             fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2365,12 +2366,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CJ: {
+                case arch::traits<ARCH>::opcode_e::C__J: {
                     uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cj"),
+                            "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"),
                             fmt::arg("imm", imm));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2383,13 +2384,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CBEQZ: {
+                case arch::traits<ARCH>::opcode_e::C__BEQZ: {
                     uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
                     uint8_t rs1 = ((bit_sub<7,3>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbeqz"),
+                            "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"),
                             fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2405,13 +2406,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CBNEZ: {
+                case arch::traits<ARCH>::opcode_e::C__BNEZ: {
                     uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
                     uint8_t rs1 = ((bit_sub<7,3>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbnez"),
+                            "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"),
                             fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2427,13 +2428,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CSLLI: {
+                case arch::traits<ARCH>::opcode_e::C__SLLI: {
                     uint8_t nzuimm = ((bit_sub<2,5>(instr)));
                     uint8_t rs1 = ((bit_sub<7,5>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "cslli"),
+                            "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"),
                             fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2453,13 +2454,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CLWSP: {
+                case arch::traits<ARCH>::opcode_e::C__LWSP: {
                     uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5));
                     uint8_t rd = ((bit_sub<7,5>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "clwsp"),
+                            "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"),
                             fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2473,20 +2474,20 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         }
                         else {
                             uint32_t offs = (uint32_t)(*(X+2) + uimm);
-                            int32_t read_res = super::template read_mem<int32_t>(traits::MEM, offs);
+                            int32_t res_39 = super::template read_mem<int32_t>(traits::MEM, offs);
                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                            *(X+rd) = (uint32_t)(int32_t)read_res;
+                            *(X+rd) = (uint32_t)(int32_t)res_39;
                         }
                     }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CMV: {
+                case arch::traits<ARCH>::opcode_e::C__MV: {
                     uint8_t rs2 = ((bit_sub<2,5>(instr)));
                     uint8_t rd = ((bit_sub<7,5>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cmv"),
+                            "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2506,12 +2507,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CJR: {
+                case arch::traits<ARCH>::opcode_e::C__JR: {
                     uint8_t rs1 = ((bit_sub<7,5>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjr"),
+                            "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"),
                             fmt::arg("rs1", name(rs1)));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2521,7 +2522,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs1 && rs1 < traits::RFS) {
-                                        *NEXT_PC = *(X+rs1 % traits::RFS) & ~ 0x1;
+                                        uint32_t addr_mask = (uint32_t)- 2;
+                                        *NEXT_PC = *(X+rs1 % traits::RFS) & addr_mask;
                                         this->core.reg.last_branch = 1;
                                     }
                                     else {
@@ -2543,13 +2545,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CADD: {
+                case arch::traits<ARCH>::opcode_e::C__ADD: {
                     uint8_t rs2 = ((bit_sub<2,5>(instr)));
                     uint8_t rd = ((bit_sub<7,5>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cadd"),
+                            "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2569,12 +2571,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CJALR: {
+                case arch::traits<ARCH>::opcode_e::C__JALR: {
                     uint8_t rs1 = ((bit_sub<7,5>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjalr"),
+                            "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"),
                             fmt::arg("rs1", name(rs1)));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2587,18 +2589,19 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0,  2);
                                     }
                                     else {
+                                        uint32_t addr_mask = (uint32_t)- 2;
                                         uint32_t new_pc = *(X+rs1);
                                         *(X+1) = (uint32_t)(*PC +  2);
-                                        *NEXT_PC = new_pc & ~ 0x1;
+                                        *NEXT_PC = new_pc & addr_mask;
                                         this->core.reg.last_branch = 1;
                                     }
                                 }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CEBREAK: {
+                case arch::traits<ARCH>::opcode_e::C__EBREAK: {
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
-                        this->core.disass_output(pc.val, "cebreak");
+                        this->core.disass_output(pc.val, "c__ebreak");
                     }
                     // used registers// calculate next pc value
                     *NEXT_PC = *PC + 2;
@@ -2608,13 +2611,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                     break;
                 }// @suppress("No break at end of case")
-                case arch::traits<ARCH>::opcode_e::CSWSP: {
+                case arch::traits<ARCH>::opcode_e::C__SWSP: {
                     uint8_t rs2 = ((bit_sub<2,5>(instr)));
                     uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "cswsp"),
+                            "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"),
                             fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
                         this->core.disass_output(pc.val, mnemonic);
                     }

src/vm/llvm/vm_tgc5c.cpp

@@ -269,64 +269,64 @@ private:
         {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem},
         /* instruction REMU, encoding '0b00000010000000000111000000110011' */
         {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu},
-        /* instruction CADDI4SPN, encoding '0b0000000000000000' */
-        {16, 0b0000000000000000, 0b1110000000000011, &this_class::__caddi4spn},
-        /* instruction CLW, encoding '0b0100000000000000' */
-        {16, 0b0100000000000000, 0b1110000000000011, &this_class::__clw},
-        /* instruction CSW, encoding '0b1100000000000000' */
-        {16, 0b1100000000000000, 0b1110000000000011, &this_class::__csw},
-        /* instruction CADDI, encoding '0b0000000000000001' */
-        {16, 0b0000000000000001, 0b1110000000000011, &this_class::__caddi},
-        /* instruction CNOP, encoding '0b0000000000000001' */
-        {16, 0b0000000000000001, 0b1110111110000011, &this_class::__cnop},
-        /* instruction CJAL, encoding '0b0010000000000001' */
-        {16, 0b0010000000000001, 0b1110000000000011, &this_class::__cjal},
-        /* instruction CLI, encoding '0b0100000000000001' */
-        {16, 0b0100000000000001, 0b1110000000000011, &this_class::__cli},
-        /* instruction CLUI, encoding '0b0110000000000001' */
-        {16, 0b0110000000000001, 0b1110000000000011, &this_class::__clui},
-        /* instruction CADDI16SP, encoding '0b0110000100000001' */
-        {16, 0b0110000100000001, 0b1110111110000011, &this_class::__caddi16sp},
+        /* instruction C__ADDI4SPN, encoding '0b0000000000000000' */
+        {16, 0b0000000000000000, 0b1110000000000011, &this_class::__c__addi4spn},
+        /* instruction C__LW, encoding '0b0100000000000000' */
+        {16, 0b0100000000000000, 0b1110000000000011, &this_class::__c__lw},
+        /* instruction C__SW, encoding '0b1100000000000000' */
+        {16, 0b1100000000000000, 0b1110000000000011, &this_class::__c__sw},
+        /* instruction C__ADDI, encoding '0b0000000000000001' */
+        {16, 0b0000000000000001, 0b1110000000000011, &this_class::__c__addi},
+        /* instruction C__NOP, encoding '0b0000000000000001' */
+        {16, 0b0000000000000001, 0b1110111110000011, &this_class::__c__nop},
+        /* instruction C__JAL, encoding '0b0010000000000001' */
+        {16, 0b0010000000000001, 0b1110000000000011, &this_class::__c__jal},
+        /* instruction C__LI, encoding '0b0100000000000001' */
+        {16, 0b0100000000000001, 0b1110000000000011, &this_class::__c__li},
+        /* instruction C__LUI, encoding '0b0110000000000001' */
+        {16, 0b0110000000000001, 0b1110000000000011, &this_class::__c__lui},
+        /* instruction C__ADDI16SP, encoding '0b0110000100000001' */
+        {16, 0b0110000100000001, 0b1110111110000011, &this_class::__c__addi16sp},
         /* instruction __reserved_clui, encoding '0b0110000000000001' */
         {16, 0b0110000000000001, 0b1111000001111111, &this_class::____reserved_clui},
-        /* instruction CSRLI, encoding '0b1000000000000001' */
-        {16, 0b1000000000000001, 0b1111110000000011, &this_class::__csrli},
-        /* instruction CSRAI, encoding '0b1000010000000001' */
-        {16, 0b1000010000000001, 0b1111110000000011, &this_class::__csrai},
-        /* instruction CANDI, encoding '0b1000100000000001' */
-        {16, 0b1000100000000001, 0b1110110000000011, &this_class::__candi},
-        /* instruction CSUB, encoding '0b1000110000000001' */
-        {16, 0b1000110000000001, 0b1111110001100011, &this_class::__csub},
-        /* instruction CXOR, encoding '0b1000110000100001' */
-        {16, 0b1000110000100001, 0b1111110001100011, &this_class::__cxor},
-        /* instruction COR, encoding '0b1000110001000001' */
-        {16, 0b1000110001000001, 0b1111110001100011, &this_class::__cor},
-        /* instruction CAND, encoding '0b1000110001100001' */
-        {16, 0b1000110001100001, 0b1111110001100011, &this_class::__cand},
-        /* instruction CJ, encoding '0b1010000000000001' */
-        {16, 0b1010000000000001, 0b1110000000000011, &this_class::__cj},
-        /* instruction CBEQZ, encoding '0b1100000000000001' */
-        {16, 0b1100000000000001, 0b1110000000000011, &this_class::__cbeqz},
-        /* instruction CBNEZ, encoding '0b1110000000000001' */
-        {16, 0b1110000000000001, 0b1110000000000011, &this_class::__cbnez},
-        /* instruction CSLLI, encoding '0b0000000000000010' */
-        {16, 0b0000000000000010, 0b1111000000000011, &this_class::__cslli},
-        /* instruction CLWSP, encoding '0b0100000000000010' */
-        {16, 0b0100000000000010, 0b1110000000000011, &this_class::__clwsp},
-        /* instruction CMV, encoding '0b1000000000000010' */
-        {16, 0b1000000000000010, 0b1111000000000011, &this_class::__cmv},
-        /* instruction CJR, encoding '0b1000000000000010' */
-        {16, 0b1000000000000010, 0b1111000001111111, &this_class::__cjr},
+        /* instruction C__SRLI, encoding '0b1000000000000001' */
+        {16, 0b1000000000000001, 0b1111110000000011, &this_class::__c__srli},
+        /* instruction C__SRAI, encoding '0b1000010000000001' */
+        {16, 0b1000010000000001, 0b1111110000000011, &this_class::__c__srai},
+        /* instruction C__ANDI, encoding '0b1000100000000001' */
+        {16, 0b1000100000000001, 0b1110110000000011, &this_class::__c__andi},
+        /* instruction C__SUB, encoding '0b1000110000000001' */
+        {16, 0b1000110000000001, 0b1111110001100011, &this_class::__c__sub},
+        /* instruction C__XOR, encoding '0b1000110000100001' */
+        {16, 0b1000110000100001, 0b1111110001100011, &this_class::__c__xor},
+        /* instruction C__OR, encoding '0b1000110001000001' */
+        {16, 0b1000110001000001, 0b1111110001100011, &this_class::__c__or},
+        /* instruction C__AND, encoding '0b1000110001100001' */
+        {16, 0b1000110001100001, 0b1111110001100011, &this_class::__c__and},
+        /* instruction C__J, encoding '0b1010000000000001' */
+        {16, 0b1010000000000001, 0b1110000000000011, &this_class::__c__j},
+        /* instruction C__BEQZ, encoding '0b1100000000000001' */
+        {16, 0b1100000000000001, 0b1110000000000011, &this_class::__c__beqz},
+        /* instruction C__BNEZ, encoding '0b1110000000000001' */
+        {16, 0b1110000000000001, 0b1110000000000011, &this_class::__c__bnez},
+        /* instruction C__SLLI, encoding '0b0000000000000010' */
+        {16, 0b0000000000000010, 0b1111000000000011, &this_class::__c__slli},
+        /* instruction C__LWSP, encoding '0b0100000000000010' */
+        {16, 0b0100000000000010, 0b1110000000000011, &this_class::__c__lwsp},
+        /* instruction C__MV, encoding '0b1000000000000010' */
+        {16, 0b1000000000000010, 0b1111000000000011, &this_class::__c__mv},
+        /* instruction C__JR, encoding '0b1000000000000010' */
+        {16, 0b1000000000000010, 0b1111000001111111, &this_class::__c__jr},
         /* instruction __reserved_cmv, encoding '0b1000000000000010' */
         {16, 0b1000000000000010, 0b1111111111111111, &this_class::____reserved_cmv},
-        /* instruction CADD, encoding '0b1001000000000010' */
-        {16, 0b1001000000000010, 0b1111000000000011, &this_class::__cadd},
-        /* instruction CJALR, encoding '0b1001000000000010' */
-        {16, 0b1001000000000010, 0b1111000001111111, &this_class::__cjalr},
-        /* instruction CEBREAK, encoding '0b1001000000000010' */
-        {16, 0b1001000000000010, 0b1111111111111111, &this_class::__cebreak},
-        /* instruction CSWSP, encoding '0b1100000000000010' */
-        {16, 0b1100000000000010, 0b1110000000000011, &this_class::__cswsp},
+        /* instruction C__ADD, encoding '0b1001000000000010' */
+        {16, 0b1001000000000010, 0b1111000000000011, &this_class::__c__add},
+        /* instruction C__JALR, encoding '0b1001000000000010' */
+        {16, 0b1001000000000010, 0b1111000001111111, &this_class::__c__jalr},
+        /* instruction C__EBREAK, encoding '0b1001000000000010' */
+        {16, 0b1001000000000010, 0b1111111111111111, &this_class::__c__ebreak},
+        /* instruction C__SWSP, encoding '0b1100000000000010' */
+        {16, 0b1100000000000010, 0b1110000000000011, &this_class::__c__swsp},
         /* instruction DII, encoding '0b0000000000000000' */
         {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii},
     }};
@@ -3194,9 +3194,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 57: CADDI4SPN */
-    std::tuple<continuation_e, BasicBlock*> __caddi4spn(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CADDI4SPN_0x{:X}",pc.val));
+    /* instruction 57: C__ADDI4SPN */
+    std::tuple<continuation_e, BasicBlock*> __c__addi4spn(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__ADDI4SPN_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,57);
         uint64_t PC = pc.val;
         uint8_t rd = ((bit_sub<2,3>(instr)));
@@ -3204,7 +3204,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "caddi4spn"),
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"),
                 fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3238,9 +3238,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 58: CLW */
-    std::tuple<continuation_e, BasicBlock*> __clw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CLW_0x{:X}",pc.val));
+    /* instruction 58: C__LW */
+    std::tuple<continuation_e, BasicBlock*> __c__lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__LW_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,58);
         uint64_t PC = pc.val;
         uint8_t rd = ((bit_sub<2,3>(instr)));
@@ -3249,7 +3249,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "clw"),
+                "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"),
                 fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3283,9 +3283,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 59: CSW */
-    std::tuple<continuation_e, BasicBlock*> __csw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CSW_0x{:X}",pc.val));
+    /* instruction 59: C__SW */
+    std::tuple<continuation_e, BasicBlock*> __c__sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__SW_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,59);
         uint64_t PC = pc.val;
         uint8_t rs2 = ((bit_sub<2,3>(instr)));
@@ -3294,7 +3294,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "csw"),
+                "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"),
                 fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3326,9 +3326,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 60: CADDI */
-    std::tuple<continuation_e, BasicBlock*> __caddi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CADDI_0x{:X}",pc.val));
+    /* instruction 60: C__ADDI */
+    std::tuple<continuation_e, BasicBlock*> __c__addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__ADDI_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,60);
         uint64_t PC = pc.val;
         uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
@@ -3336,7 +3336,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "caddi"),
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"),
                 fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3372,9 +3372,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 61: CNOP */
-    std::tuple<continuation_e, BasicBlock*> __cnop(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CNOP_0x{:X}",pc.val));
+    /* instruction 61: C__NOP */
+    std::tuple<continuation_e, BasicBlock*> __c__nop(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__NOP_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,61);
         uint64_t PC = pc.val;
         uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
@@ -3394,16 +3394,16 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 62: CJAL */
-    std::tuple<continuation_e, BasicBlock*> __cjal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CJAL_0x{:X}",pc.val));
+    /* instruction 62: C__JAL */
+    std::tuple<continuation_e, BasicBlock*> __c__jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__JAL_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,62);
         uint64_t PC = pc.val;
         uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cjal"),
+                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"),
                 fmt::arg("imm", imm));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3430,9 +3430,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 63: CLI */
-    std::tuple<continuation_e, BasicBlock*> __cli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CLI_0x{:X}",pc.val));
+    /* instruction 63: C__LI */
+    std::tuple<continuation_e, BasicBlock*> __c__li(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__LI_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,63);
         uint64_t PC = pc.val;
         uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
@@ -3440,7 +3440,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "cli"),
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"),
                 fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3471,9 +3471,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 64: CLUI */
-    std::tuple<continuation_e, BasicBlock*> __clui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CLUI_0x{:X}",pc.val));
+    /* instruction 64: C__LUI */
+    std::tuple<continuation_e, BasicBlock*> __c__lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__LUI_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,64);
         uint64_t PC = pc.val;
         uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17));
@@ -3481,7 +3481,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "clui"),
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"),
                 fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3510,16 +3510,16 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 65: CADDI16SP */
-    std::tuple<continuation_e, BasicBlock*> __caddi16sp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CADDI16SP_0x{:X}",pc.val));
+    /* instruction 65: C__ADDI16SP */
+    std::tuple<continuation_e, BasicBlock*> __c__addi16sp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__ADDI16SP_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,65);
         uint64_t PC = pc.val;
         uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9));
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "caddi16sp"),
+                "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"),
                 fmt::arg("nzimm", nzimm));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3576,9 +3576,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 67: CSRLI */
-    std::tuple<continuation_e, BasicBlock*> __csrli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CSRLI_0x{:X}",pc.val));
+    /* instruction 67: C__SRLI */
+    std::tuple<continuation_e, BasicBlock*> __c__srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__SRLI_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,67);
         uint64_t PC = pc.val;
         uint8_t shamt = ((bit_sub<2,5>(instr)));
@@ -3586,7 +3586,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrli"),
+                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"),
                 fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3613,9 +3613,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 68: CSRAI */
-    std::tuple<continuation_e, BasicBlock*> __csrai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CSRAI_0x{:X}",pc.val));
+    /* instruction 68: C__SRAI */
+    std::tuple<continuation_e, BasicBlock*> __c__srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__SRAI_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,68);
         uint64_t PC = pc.val;
         uint8_t shamt = ((bit_sub<2,5>(instr)));
@@ -3623,7 +3623,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrai"),
+                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"),
                 fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3668,9 +3668,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 69: CANDI */
-    std::tuple<continuation_e, BasicBlock*> __candi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CANDI_0x{:X}",pc.val));
+    /* instruction 69: C__ANDI */
+    std::tuple<continuation_e, BasicBlock*> __c__andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__ANDI_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,69);
         uint64_t PC = pc.val;
         uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
@@ -3678,7 +3678,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "candi"),
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"),
                 fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3707,9 +3707,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 70: CSUB */
-    std::tuple<continuation_e, BasicBlock*> __csub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CSUB_0x{:X}",pc.val));
+    /* instruction 70: C__SUB */
+    std::tuple<continuation_e, BasicBlock*> __c__sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__SUB_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,70);
         uint64_t PC = pc.val;
         uint8_t rs2 = ((bit_sub<2,3>(instr)));
@@ -3717,7 +3717,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "csub"),
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"),
                 fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3746,9 +3746,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 71: CXOR */
-    std::tuple<continuation_e, BasicBlock*> __cxor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CXOR_0x{:X}",pc.val));
+    /* instruction 71: C__XOR */
+    std::tuple<continuation_e, BasicBlock*> __c__xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__XOR_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,71);
         uint64_t PC = pc.val;
         uint8_t rs2 = ((bit_sub<2,3>(instr)));
@@ -3756,7 +3756,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cxor"),
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"),
                 fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3783,9 +3783,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 72: COR */
-    std::tuple<continuation_e, BasicBlock*> __cor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("COR_0x{:X}",pc.val));
+    /* instruction 72: C__OR */
+    std::tuple<continuation_e, BasicBlock*> __c__or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__OR_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,72);
         uint64_t PC = pc.val;
         uint8_t rs2 = ((bit_sub<2,3>(instr)));
@@ -3793,7 +3793,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cor"),
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"),
                 fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3820,9 +3820,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 73: CAND */
-    std::tuple<continuation_e, BasicBlock*> __cand(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CAND_0x{:X}",pc.val));
+    /* instruction 73: C__AND */
+    std::tuple<continuation_e, BasicBlock*> __c__and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__AND_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,73);
         uint64_t PC = pc.val;
         uint8_t rs2 = ((bit_sub<2,3>(instr)));
@@ -3830,7 +3830,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cand"),
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"),
                 fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3857,16 +3857,16 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 74: CJ */
-    std::tuple<continuation_e, BasicBlock*> __cj(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CJ_0x{:X}",pc.val));
+    /* instruction 74: C__J */
+    std::tuple<continuation_e, BasicBlock*> __c__j(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__J_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,74);
         uint64_t PC = pc.val;
         uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cj"),
+                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"),
                 fmt::arg("imm", imm));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3890,9 +3890,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 75: CBEQZ */
-    std::tuple<continuation_e, BasicBlock*> __cbeqz(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CBEQZ_0x{:X}",pc.val));
+    /* instruction 75: C__BEQZ */
+    std::tuple<continuation_e, BasicBlock*> __c__beqz(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__BEQZ_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,75);
         uint64_t PC = pc.val;
         uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
@@ -3900,7 +3900,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbeqz"),
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"),
                 fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3935,9 +3935,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 76: CBNEZ */
-    std::tuple<continuation_e, BasicBlock*> __cbnez(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CBNEZ_0x{:X}",pc.val));
+    /* instruction 76: C__BNEZ */
+    std::tuple<continuation_e, BasicBlock*> __c__bnez(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__BNEZ_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,76);
         uint64_t PC = pc.val;
         uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
@@ -3945,7 +3945,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbnez"),
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"),
                 fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -3980,9 +3980,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 77: CSLLI */
-    std::tuple<continuation_e, BasicBlock*> __cslli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CSLLI_0x{:X}",pc.val));
+    /* instruction 77: C__SLLI */
+    std::tuple<continuation_e, BasicBlock*> __c__slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__SLLI_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,77);
         uint64_t PC = pc.val;
         uint8_t nzuimm = ((bit_sub<2,5>(instr)));
@@ -3990,7 +3990,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "cslli"),
+                "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"),
                 fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -4024,9 +4024,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 78: CLWSP */
-    std::tuple<continuation_e, BasicBlock*> __clwsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CLWSP_0x{:X}",pc.val));
+    /* instruction 78: C__LWSP */
+    std::tuple<continuation_e, BasicBlock*> __c__lwsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__LWSP_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,78);
         uint64_t PC = pc.val;
         uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5));
@@ -4034,7 +4034,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "clwsp"),
+                "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"),
                 fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -4073,9 +4073,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 79: CMV */
-    std::tuple<continuation_e, BasicBlock*> __cmv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CMV_0x{:X}",pc.val));
+    /* instruction 79: C__MV */
+    std::tuple<continuation_e, BasicBlock*> __c__mv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__MV_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,79);
         uint64_t PC = pc.val;
         uint8_t rs2 = ((bit_sub<2,5>(instr)));
@@ -4083,7 +4083,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cmv"),
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"),
                 fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -4114,16 +4114,16 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 80: CJR */
-    std::tuple<continuation_e, BasicBlock*> __cjr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CJR_0x{:X}",pc.val));
+    /* instruction 80: C__JR */
+    std::tuple<continuation_e, BasicBlock*> __c__jr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__JR_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,80);
         uint64_t PC = pc.val;
         uint8_t rs1 = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjr"),
+                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"),
                 fmt::arg("rs1", name(rs1)));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -4177,9 +4177,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 82: CADD */
-    std::tuple<continuation_e, BasicBlock*> __cadd(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CADD_0x{:X}",pc.val));
+    /* instruction 82: C__ADD */
+    std::tuple<continuation_e, BasicBlock*> __c__add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__ADD_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,82);
         uint64_t PC = pc.val;
         uint8_t rs2 = ((bit_sub<2,5>(instr)));
@@ -4187,7 +4187,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cadd"),
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"),
                 fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -4223,16 +4223,16 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 83: CJALR */
-    std::tuple<continuation_e, BasicBlock*> __cjalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CJALR_0x{:X}",pc.val));
+    /* instruction 83: C__JALR */
+    std::tuple<continuation_e, BasicBlock*> __c__jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__JALR_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,83);
         uint64_t PC = pc.val;
         uint8_t rs1 = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjalr"),
+                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"),
                 fmt::arg("rs1", name(rs1)));
             std::vector<Value*> args {
                 this->core_ptr,
@@ -4269,9 +4269,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 84: CEBREAK */
-    std::tuple<continuation_e, BasicBlock*> __cebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CEBREAK_0x{:X}",pc.val));
+    /* instruction 84: C__EBREAK */
+    std::tuple<continuation_e, BasicBlock*> __c__ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__EBREAK_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,84);
         uint64_t PC = pc.val;
         if(this->disass_enabled){
@@ -4291,9 +4291,9 @@ private:
     	return returnValue;        
     }
     
-    /* instruction 85: CSWSP */
-    std::tuple<continuation_e, BasicBlock*> __cswsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("CSWSP_0x{:X}",pc.val));
+    /* instruction 85: C__SWSP */
+    std::tuple<continuation_e, BasicBlock*> __c__swsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("C__SWSP_0x{:X}",pc.val));
         this->gen_sync(PRE_SYNC,85);
         uint64_t PC = pc.val;
         uint8_t rs2 = ((bit_sub<2,5>(instr)));
@@ -4301,7 +4301,7 @@ private:
         if(this->disass_enabled){
             /* generate console output when executing the command */
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "cswsp"),
+                "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"),
                 fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
             std::vector<Value*> args {
                 this->core_ptr,