5 Commits

Author SHA1 Message Date
66dc28c239 scc update: scv4tlm -> scv 2021-03-30 11:13:04 +02:00
40470445f4 fix scv4tlm namespace hierarchy 2021-03-26 21:51:35 +01:00
ea3ff3c0cd build with SCV lib 2021-03-23 11:57:47 +01:00
c941890901 SCC refactoring 2021-03-22 14:50:53 +01:00
b7c0fb2b1c fix bitfield structure 2021-03-10 12:40:06 +01:00
4 changed files with 9 additions and 9 deletions

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@ -52,7 +52,7 @@ endif()
add_library(riscv SHARED ${LIB_SOURCES})
target_compile_options(riscv PRIVATE -Wno-shift-count-overflow)
target_include_directories(riscv PUBLIC incl ../external/elfio)
target_link_libraries(riscv PUBLIC softfloat scc-util)
target_link_libraries(riscv PUBLIC softfloat scc-util jsoncpp)
target_link_libraries(riscv PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
set_target_properties(riscv PROPERTIES
VERSION ${PROJECT_VERSION}
@ -120,4 +120,4 @@ install(TARGETS riscv riscv-sim
# CMAKE PACKAGING (for other CMake projects to use this one easily)
# _____________________________________________________________________________
#include(PackageConfigurator)
#include(PackageConfigurator)

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@ -302,7 +302,7 @@ public:
void write_mstatus(T val) {
auto mask = get_mask();
auto new_val = (mstatus.st.value & ~mask) | (val & mask);
auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
mstatus = new_val;
}

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@ -33,10 +33,10 @@
#ifndef _SYSC_SIFIVE_FE310_H_
#define _SYSC_SIFIVE_FE310_H_
#include "scc/initiator_mixin.h"
#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
#include "tlm/scc/initiator_mixin.h"
#include "scc/traceable.h"
#include "scc/utilities.h"
#include "scv4tlm/tlm_rec_initiator_socket.h"
#include <cci_configuration>
#include <tlm>
#include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
@ -75,7 +75,7 @@ class core_wrapper;
class core_complex : public sc_core::sc_module, public scc::traceable {
public:
scc::initiator_mixin<scv4tlm::tlm_rec_initiator_socket<32>> initiator{"intor"};
tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};

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@ -331,7 +331,7 @@ void core_complex::disass_output(uint64_t pc, const std::string instr_str) {
tr_handle.record_attribute("PC", pc);
tr_handle.record_attribute("INSTR", instr_str);
tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
tr_handle.record_attribute("MSTATUS", cpu->get_state().mstatus.st.value);
tr_handle.record_attribute("MSTATUS", cpu->get_state().mstatus.backing.val);
tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000);
#endif
}
@ -388,7 +388,7 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
if (is_fetch && tr_handle.is_active()) {
tr_handle.end_transaction();
}
auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this);
auto preExt = new tlm::scc::scv4tlm::tlm_recording_extension(tr_handle, this);
gp.set_extension(preExt);
}
#endif
@ -434,7 +434,7 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
sc_time delay{quantum_keeper.get_local_time()};
#ifdef WITH_SCV
if (m_db != nullptr && tr_handle.is_valid()) {
auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this);
auto preExt = new tlm::scc::scv4tlm::tlm_recording_extension(tr_handle, this);
gp.set_extension(preExt);
}
#endif