remove MSVC warning

add MSVC 16 compatibility
fix find_package use and debug access alignment check
2021-10-10 19:56:33 +02:00 · 2021-10-10 19:06:41 +02:00 · 2021-08-26 22:10:27 +02:00 · 2021-08-20 09:02:56 +02:00 · 2021-08-19 13:38:29 +02:00 · 2021-08-19 10:50:25 +02:00
17 changed files with 858 additions and 294 deletions
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,12 +1,13 @@
 cmake_minimum_required(VERSION 3.12)
-
-project(dbt-core-tgc VERSION 1.0.0)
+###############################################################################
+#
+###############################################################################
+project(dbt-rise-tgc VERSION 1.0.0)

 include(GNUInstallDirs)

-conan_basic_setup()
+find_package(elfio)

-find_package(Boost COMPONENTS program_options system thread filesystem REQUIRED)
 if(WITH_LLVM)
    if(DEFINED ENV{LLVM_HOME})
        find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
@@ -47,54 +48,56 @@ if(WITH_LLVM)
 endif()

 # Define the library
-add_library(${PROJECT_NAME} SHARED ${LIB_SOURCES})
+add_library(${PROJECT_NAME} ${LIB_SOURCES})
 # list code gen dependencies
 if(TARGET ${CORE_NAME}_cpp)
    add_dependencies(${PROJECT_NAME} ${CORE_NAME}_cpp)
 endif()

-target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
+if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
+     target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
+elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
+    target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
+endif()
 target_include_directories(${PROJECT_NAME} PUBLIC incl)
 target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp)
-target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
-target_link_libraries(${PROJECT_NAME} PUBLIC ${Boost_LIBRARIES} )
+if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
+    target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
+else()
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-core)
+endif()
+if(TARGET CONAN_PKG::elfio)
+    target_link_libraries(${PROJECT_NAME} PUBLIC CONAN_PKG::elfio)
+elseif(TARGET elfio::elfio)
+    target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)
+else()
+    message(FATAL_ERROR "No elfio library found, maybe a find_package() call is missing")
+endif()
+
 set_target_properties(${PROJECT_NAME} PROPERTIES
  VERSION ${PROJECT_VERSION}
  FRAMEWORK FALSE
-  PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
 )
-
-if(SystemC_FOUND)
-	add_library(${PROJECT_NAME}_sc src/sysc/core_complex.cpp)
-	target_compile_definitions(${PROJECT_NAME}_sc PUBLIC WITH_SYSTEMC)
-    target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_b.h)
-        target_compile_definitions(${PROJECT_NAME}_sc PRIVATE CORE_TGC_B)
-    endif()
-	if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_c.h)
-        target_compile_definitions(${PROJECT_NAME}_sc PRIVATE CORE_TGC_C)
-    endif()
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_d.h)
-        target_compile_definitions(${PROJECT_NAME}_sc PRIVATE CORE_TGC_D)
-    endif()
-	target_include_directories(${PROJECT_NAME}_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
-	
-	if(SCV_FOUND)   
-	    target_compile_definitions(${PROJECT_NAME}_sc PUBLIC WITH_SCV)
-	    target_include_directories(${PROJECT_NAME}_sc PUBLIC ${SCV_INCLUDE_DIRS})
-	endif()
-	target_link_libraries(${PROJECT_NAME}_sc PUBLIC ${PROJECT_NAME} scc)
-	if(WITH_LLVM)
-		target_link_libraries(${PROJECT_NAME}_sc PUBLIC ${llvm_libs})
-	endif()
-	set_target_properties(${PROJECT_NAME}_sc PROPERTIES
-	  VERSION ${PROJECT_VERSION}
-	  FRAMEWORK FALSE
-	  PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
+install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
+  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
+  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
+  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
+  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
+  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
+)
+install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss COMPONENT ${PROJECT_NAME}
+        DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # target directory
+        FILES_MATCHING # install only matched files
+        PATTERN "*.h" # select header files
        )
-endif()
-
+###############################################################################
+#
+###############################################################################
 project(tgc-sim)
+find_package(Boost COMPONENTS program_options thread REQUIRED)
+
 add_executable(${PROJECT_NAME} src/main.cpp)
 # This sets the include directory for the reference project. This is the -I flag in gcc.
 target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
@@ -103,19 +106,64 @@ if(WITH_LLVM)
    target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
 endif()
 # Links the target exe against the libraries
-target_link_libraries(${PROJECT_NAME} dbt-core-tgc)
-target_link_libraries(${PROJECT_NAME} jsoncpp)
-target_link_libraries(${PROJECT_NAME} ${Boost_LIBRARIES} )
+target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc)
+if(TARGET Boost::program_options)
+    target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options Boost::thread)
+else()
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY} ${BOOST_thread_LIBRARY})
+endif()
+target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS})
 if (Tcmalloc_FOUND)
-    target_link_libraries(${PROJECT_NAME} ${Tcmalloc_LIBRARIES})
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${Tcmalloc_LIBRARIES})
 endif(Tcmalloc_FOUND)

-install(TARGETS dbt-core-tgc tgc-sim
+install(TARGETS tgc-sim
  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
-  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # static lib
-  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} COMPONENT libs   # binaries
-  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # shared lib
-  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac
-  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} COMPONENT devel   # headers for mac (note the different component -> different package)
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
+  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
+  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
+  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME}  # headers for mac (note the different component -> different package)
  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
 )
+###############################################################################
+#
+###############################################################################
+project(dbt-rise-tgc_sc VERSION 1.0.0)
+
+include(SystemCPackage)
+if(SystemC_FOUND)
+    add_library(${PROJECT_NAME} src/sysc/core_complex.cpp)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_b.h)
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_B)
+    endif()
+    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_c.h)
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_C)
+    endif()
+    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_d.h)
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_D)
+    endif()
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc)
+    if(WITH_LLVM)
+        target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+    endif()
+    
+	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/core_complex.h)
+    set_target_properties(${PROJECT_NAME} PROPERTIES
+      VERSION ${PROJECT_VERSION}
+      FRAMEWORK FALSE
+      PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
+    )
+    install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
+	  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
+	  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
+	  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
+	  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
+	  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+	  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc   # headers for mac (note the different component -> different package)
+	  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
+	)    
+endif()
+
--- a/contrib/build.tcl
+++ b/contrib/build.tcl
@@ -0,0 +1,30 @@
+namespace eval Specification {
+    proc buildproc { args } {
+        global env
+        variable installDir
+        variable compiler
+        variable compiler [::scsh::get_backend_compiler]
+        #  set target $machine
+        set target [::scsh::machine]
+        set linkerOptions ""
+        set preprocessorOptions ""
+        set libversion $compiler
+        switch -exact -- $target {
+            "linux" {
+            	set install_dir $::env(TGFS_INSTALL_ROOT)
+                set incldir "${install_dir}/include"
+                set libdir "${install_dir}/lib64"
+                set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
+                # Set the Linker paths.
+                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc"]
+            }
+            default {
+               puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"
+               return
+            }
+        }
+        ::scsh::cwr_append_ipsimbld_opts preprocessor "$preprocessorOptions"
+        ::scsh::cwr_append_ipsimbld_opts linker       "$linkerOptions"
+    }
+    ::scsh::add_build_callback [namespace current]::buildproc
+}
--- a/contrib/tgc_import.cc
+++ b/contrib/tgc_import.cc
@@ -0,0 +1,4 @@
+
+#include "sysc/core_complex.h"
+
+void modules() { sysc::tgfs::core_complex i_core_complex("core_complex"); }
--- a/contrib/tgc_import.tcl
+++ b/contrib/tgc_import.tcl
@@ -0,0 +1,50 @@
+#############################################################################
+#
+#############################################################################
+proc getScriptDirectory {} {
+    set dispScriptFile [file normalize [info script]]
+    set scriptFolder [file dirname $dispScriptFile]
+    return $scriptFolder
+}
+if { $::env(SNPS_VP_PRODUCT) == "PAULTRA" } {
+    set hardware /HARDWARE/HW/HW
+} else {
+    set hardware /HARDWARE
+}
+
+set scriptDir [getScriptDirectory]
+set top_design_name core_complex
+set clocks clk_i
+set resets rst_i
+set model_prefix "i_"
+set model_postfix ""
+
+::pct::new_project
+::pct::open_library TLM2_PL
+::pct::clear_systemc_defines
+::pct::clear_systemc_include_path
+::pct::add_to_systemc_include_path $::env(TGFS_INSTALL_ROOT)/include
+::pct::set_import_protocol_generation_flag false
+::pct::set_update_existing_encaps_flag true
+::pct::set_dynamic_port_arrays_flag true
+::pct::set_import_scml_properties_flag true
+::pct::load_modules --set-category modules tgc_import.cc
+
+# Set Port Protocols correctly
+set block ${top_design_name}
+foreach clock ${clocks} {
+	::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${clock} SYSTEM_LIBRARY:CLOCK
+}
+foreach reset ${resets} {
+    ::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
+}
+::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
+
+# Set compile settings and look
+set block SYSTEM_LIBRARY:${top_design_name}
+::pct::set_encap_build_script $block/${top_design_name} $scriptDir/build.tcl
+::pct::set_background_color_rgb $block 255 255 255 255
+::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${top_design_name} 
+
+# export the result as component
+::pct::export_system_library ${top_design_name}  ${top_design_name}.xml
--- a/gen_input/CoreDSL-Instruction-Set-Description
+++ b/gen_input/CoreDSL-Instruction-Set-Description
--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@@ -296,6 +296,10 @@ inline bool is_count_limit_enabled(finish_cond_e cond){
    return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
 }

+inline bool is_jump_to_self_enabled(finish_cond_e cond){
+    return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
+}
+
 template <typename ARCH>
 typename vm_impl<ARCH>::compile_func vm_impl<ARCH>::decode_inst(code_word_t instr){
    for(auto& e: qlut[instr&0x3]){
@@ -307,7 +311,6 @@ typename vm_impl<ARCH>::compile_func vm_impl<ARCH>::decode_inst(code_word_t inst
 template <typename ARCH>
 typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
    // we fetch at max 4 byte, alignment is 2
-    enum {TRAP_ID=1<<16};
    code_word_t insn = 0;
    auto *const data = (uint8_t *)&insn;
    auto pc=start;
@@ -315,15 +318,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
            !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
        auto res = fetch_ins(pc, data);
        if(res!=iss::Ok){
-            auto new_pc = super::core.enter_trap(TRAP_ID, pc.val, 0);
-            res = fetch_ins(virt_addr_t{access_type::FETCH, new_pc}, data);
-            if(res!=iss::Ok) throw simulation_stopped(0);
-        }
-        if ((cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF &&
+            this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
+            pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
+        } else {
+            if (is_jump_to_self_enabled(cond) &&
                    (insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
            auto f = decode_inst(insn);
            pc = (this->*f)(pc, insn);
        }
+    }
    return pc;
 }

--- a/incl/iss/arch/riscv_hart_common.h
+++ b/incl/iss/arch/riscv_hart_common.h
@@ -104,12 +104,19 @@ enum riscv_csr {
    mie = 0x304,
    mtvec = 0x305,
    mcounteren = 0x306,
+    mtvt = 0x307, //CLIC
    // Machine Trap Handling
    mscratch = 0x340,
    mepc = 0x341,
    mcause = 0x342,
    mtval = 0x343,
    mip = 0x344,
+    mxnti = 0x345, //CLIC
+    mintstatus   = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
+    mscratchcsw  = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
+    mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
+    mintthresh   = 0x350, // MRW Interrupt-level threshold (CLIC) - addr subject to change
+    mclicbase    = 0x351, // MRW Base address for CLIC memory mapped registers (CLIC) - addr subject to change
    // Physical Memory Protection
    pmpcfg0 = 0x3A0,
    pmpcfg1 = 0x3A1,
--- a/incl/iss/arch/riscv_hart_m_p.h
+++ b/incl/iss/arch/riscv_hart_m_p.h
@@ -280,16 +280,17 @@ private:
    iss::status write_cycle(unsigned addr, reg_t val);
    iss::status read_instret(unsigned addr, reg_t &val);
    iss::status write_instret(unsigned addr, reg_t val);
-    iss::status read_mtvec(unsigned addr, reg_t &val);
+    iss::status read_tvec(unsigned addr, reg_t &val);
    iss::status read_time(unsigned addr, reg_t &val);
    iss::status read_status(unsigned addr, reg_t &val);
    iss::status write_status(unsigned addr, reg_t val);
+    iss::status write_cause(unsigned addr, reg_t val);
    iss::status read_ie(unsigned addr, reg_t &val);
    iss::status write_ie(unsigned addr, reg_t val);
    iss::status read_ip(unsigned addr, reg_t &val);
    iss::status write_ip(unsigned addr, reg_t val);
    iss::status read_hartid(unsigned addr, reg_t &val);
-    iss::status write_mepc(unsigned addr, reg_t val);
+    iss::status write_epc(unsigned addr, reg_t val);

    reg_t mhartid_reg{0x0};
    std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
@@ -353,6 +354,9 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
    csr_wr_cb[minstreth] = &this_class::write_instret;
    csr_rd_cb[mstatus] = &this_class::read_status;
    csr_wr_cb[mstatus] = &this_class::write_status;
+    csr_wr_cb[mcause] = &this_class::write_cause;
+    csr_rd_cb[mtvec] = &this_class::read_tvec;
+    csr_wr_cb[mepc] = &this_class::write_epc;
    csr_rd_cb[mip] = &this_class::read_ip;
    csr_wr_cb[mip] = &this_class::write_ip;
    csr_rd_cb[mie] = &this_class::read_ie;
@@ -360,8 +364,6 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
    csr_rd_cb[mhartid] = &this_class::read_hartid;
    csr_rd_cb[mcounteren] = &this_class::read_null;
    csr_wr_cb[mcounteren] = &this_class::write_null;
-    csr_rd_cb[mtvec] = &this_class::read_mtvec;
-    csr_wr_cb[mepc] = &this_class::write_mepc;
    csr_wr_cb[misa] = &this_class::write_null;
    csr_wr_cb[mvendorid] = &this_class::write_null;
    csr_wr_cb[marchid] = &this_class::write_null;
@@ -386,6 +388,7 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_fi
                if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
            if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
            if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
+            auto entry = reader.get_entry();
            for (const auto pseg : reader.segments) {
                const auto fsize = pseg->get_file_size(); // 0x42c/0x0
                const auto seg_data = pseg->get_data();
@@ -394,18 +397,39 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_fi
                            traits<BASE>::MEM, pseg->get_physical_address(),
                            fsize, reinterpret_cast<const uint8_t *const>(seg_data));
                    if (res != iss::Ok)
-                        LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex
+                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
                                   << pseg->get_physical_address();
                }
            }
-            for (const auto sec : reader.sections) {
-                if (sec->get_name() == ".tohost") {
+            for(const auto sec : reader.sections) {
+                if(sec->get_name() == ".symtab") {
+                    if ( SHT_SYMTAB == sec->get_type() ||
+                            SHT_DYNSYM == sec->get_type() ) {
+                        ELFIO::symbol_section_accessor symbols( reader, sec );
+                        auto sym_no = symbols.get_symbols_num();
+                        std::string   name;
+                        ELFIO::Elf64_Addr    value   = 0;
+                        ELFIO::Elf_Xword     size    = 0;
+                        unsigned char bind    = 0;
+                        unsigned char type    = 0;
+                        ELFIO::Elf_Half      section = 0;
+                        unsigned char other   = 0;
+                        for ( auto i = 0U; i < sym_no; ++i ) {
+                            symbols.get_symbol( i, name, value, size, bind, type, section, other );
+                            if(name=="tohost") {
+                                tohost = value;
+                            } else if(name=="fromhost") {
+                                fromhost = value;
+                            }
+                        }
+                    }
+                } else if (sec->get_name() == ".tohost") {
                    tohost = sec->get_address();
                    fromhost = tohost + 0x40;
                }
-            }

-            return std::make_pair(reader.get_entry(), true);
+            }
+            return std::make_pair(entry, true);
        }
        throw std::runtime_error("memory load file is not a valid elf file");
    }
@@ -517,7 +541,7 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
                return iss::Err;
            }
            try {
-                if(length>1 && (addr&(length-1))){
+                if(!(access && iss::access_type::DEBUG) &&  length>1 && (addr&(length-1))){
                    this->reg.trap_state = 1<<31 | 6<<16;
                    fault_data=addr;
                    return iss::Err;
@@ -700,7 +724,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned ad
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_mtvec(unsigned addr, reg_t &val) {
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_tvec(unsigned addr, reg_t &val) {
    val = csr[mtvec] & ~2;
    return iss::Ok;
 }
@@ -716,6 +740,11 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_status(unsigned
    return iss::Ok;
 }

+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cause(unsigned addr, reg_t val) {
+    csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))|0xf); //TODO: make exception code size configurable
+    return iss::Ok;
+}
+
 template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr, reg_t &val) {
    val = csr[mie];
    return iss::Ok;
@@ -746,7 +775,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned add
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_mepc(unsigned addr, reg_t val) {
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_epc(unsigned addr, reg_t val) {
    csr[addr] = val & get_pc_mask();
    return iss::Ok;
 }
@@ -919,7 +948,11 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
    this->reg.PRIV = PRIV_M;
    this->reg.trap_state = 0;
    std::array<char, 32> buffer;
+#if defined(_MSC_VER)
+    sprintf(buffer.data(), "0x%016llx", addr);
+#else
    sprintf(buffer.data(), "0x%016lx", addr);
+#endif
    if((flags&0xffffffff) != 0xffffffff)
    CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
                       << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
--- a/incl/iss/arch/riscv_hart_msu_vp.h
+++ b/incl/iss/arch/riscv_hart_msu_vp.h
@@ -392,6 +392,7 @@ private:
    iss::status read_time(unsigned addr, reg_t &val);
    iss::status read_status(unsigned addr, reg_t &val);
    iss::status write_status(unsigned addr, reg_t val);
+    iss::status write_cause(unsigned addr, reg_t val);
    iss::status read_ie(unsigned addr, reg_t &val);
    iss::status write_ie(unsigned addr, reg_t val);
    iss::status read_ip(unsigned addr, reg_t &val);
@@ -442,7 +443,12 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
        //csr_wr_cb[addr] = &this_class::write_reg;
    }
    // common regs
-    const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}};
+    const std::array<unsigned, 22> addrs{{
+        misa, mvendorid, marchid, mimpid,
+        mepc, mtvec, mscratch, mcause, mtval, mscratch,
+        sepc, stvec, sscratch, scause, stval, sscratch,
+        uepc, utvec, uscratch, ucause, utval, uscratch
+    }};
    for(auto addr: addrs) {
        csr_rd_cb[addr] = &this_class::read_reg;
        csr_wr_cb[addr] = &this_class::write_reg;
@@ -465,10 +471,19 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
    csr_wr_cb[minstreth] = &this_class::write_instret;
    csr_rd_cb[mstatus] = &this_class::read_status;
    csr_wr_cb[mstatus] = &this_class::write_status;
+    csr_wr_cb[mcause] = &this_class::write_cause;
    csr_rd_cb[sstatus] = &this_class::read_status;
    csr_wr_cb[sstatus] = &this_class::write_status;
+    csr_wr_cb[scause] = &this_class::write_cause;
    csr_rd_cb[ustatus] = &this_class::read_status;
    csr_wr_cb[ustatus] = &this_class::write_status;
+    csr_wr_cb[ucause] = &this_class::write_cause;
+    csr_rd_cb[mtvec] = &this_class::read_tvec;
+    csr_rd_cb[stvec] = &this_class::read_tvec;
+    csr_rd_cb[utvec] = &this_class::read_tvec;
+    csr_wr_cb[mepc] = &this_class::write_epc;
+    csr_wr_cb[sepc] = &this_class::write_epc;
+    csr_wr_cb[uepc] = &this_class::write_epc;
    csr_rd_cb[mip] = &this_class::read_ip;
    csr_wr_cb[mip] = &this_class::write_ip;
    csr_rd_cb[sip] = &this_class::read_ip;
@@ -484,8 +499,6 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
    csr_rd_cb[mhartid] = &this_class::read_hartid;
    csr_rd_cb[mcounteren] = &this_class::read_null;
    csr_wr_cb[mcounteren] = &this_class::write_null;
-    csr_rd_cb[mtvec] = &this_class::read_mtvec;
-    csr_wr_cb[mepc] = &this_class::write_mepc;
    csr_wr_cb[misa] = &this_class::write_null;
    csr_wr_cb[mvendorid] = &this_class::write_null;
    csr_wr_cb[marchid] = &this_class::write_null;
@@ -518,6 +531,7 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
                if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
            if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
            if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
+            auto entry = reader.get_entry();
            for (const auto pseg : reader.segments) {
                const auto fsize = pseg->get_file_size(); // 0x42c/0x0
                const auto seg_data = pseg->get_data();
@@ -530,14 +544,35 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
                                   << pseg->get_physical_address();
                }
            }
-            for (const auto sec : reader.sections) {
-                if (sec->get_name() == ".tohost") {
+            for(const auto sec : reader.sections) {
+                if(sec->get_name() == ".symtab") {
+                    if ( SHT_SYMTAB == sec->get_type() ||
+                            SHT_DYNSYM == sec->get_type() ) {
+                        ELFIO::symbol_section_accessor symbols( reader, sec );
+                        auto sym_no = symbols.get_symbols_num();
+                        std::string   name;
+                        ELFIO::Elf64_Addr    value   = 0;
+                        ELFIO::Elf_Xword     size    = 0;
+                        unsigned char bind    = 0;
+                        unsigned char type    = 0;
+                        ELFIO::Elf_Half      section = 0;
+                        unsigned char other   = 0;
+                        for ( auto i = 0U; i < sym_no; ++i ) {
+                            symbols.get_symbol( i, name, value, size, bind, type, section, other );
+                            if(name=="tohost") {
+                                tohost = value;
+                            } else if(name=="fromhost") {
+                                fromhost = value;
+                            }
+                        }
+                    }
+                } else if (sec->get_name() == ".tohost") {
                    tohost = sec->get_address();
                    fromhost = tohost + 0x40;
                }
-            }

-            return std::make_pair(reader.get_entry(), true);
+            }
+            return std::make_pair(entry, true);
        }
        throw std::runtime_error("memory load file is not a valid elf file");
    }
@@ -859,8 +894,8 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned ad
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_mtvec(unsigned addr, reg_t &val) {
-    val = csr[mtvec] & ~2;
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_tvec(unsigned addr, reg_t &val) {
+    val = csr[addr] & ~2;
    return iss::Ok;
 }

@@ -878,6 +913,11 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_status(unsig
    return iss::Ok;
 }

+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_cause(unsigned addr, reg_t val) {
+    csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1))|0xf); //TODO: make exception code size configurable
+    return iss::Ok;
+}
+
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ie(unsigned addr, reg_t &val) {
    val = csr[mie];
    if (addr < mie) val &= csr[mideleg];
@@ -914,9 +954,8 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_ip(unsigned
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_mepc(unsigned addr, reg_t val) {
-    auto mask = get_pc_mask();
-    csr[addr] = val;//(csr[addr] & ~mask) | (val & mask);
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_epc(unsigned addr, reg_t val) {
+     csr[addr] = val & get_pc_mask();
    return iss::Ok;
 }

@@ -1279,9 +1318,6 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
    // bits in mtvec
    this->reg.NEXT_PC = ivec & ~0x3UL;
    if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
-    // reset trap state
-    this->reg.PRIV = new_priv;
-    this->reg.trap_state = 0;
    std::array<char, 32> buffer;
    sprintf(buffer.data(), "0x%016lx", addr);
    if((flags&0xffffffff) != 0xffffffff)
@@ -1289,6 +1325,9 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
                       << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
                       << " at address " << buffer.data() << " occurred, changing privilege level from "
                       << lvl[cur_priv] << " to " << lvl[new_priv];
+    // reset trap state
+    this->reg.PRIV = new_priv;
+    this->reg.trap_state = 0;
    update_vm_info();
    return this->reg.NEXT_PC;
 }
--- a/incl/iss/arch/riscv_hart_mu_p.h
+++ b/incl/iss/arch/riscv_hart_mu_p.h
@@ -66,7 +66,7 @@
 namespace iss {
 namespace arch {

-enum features_e{FEAT_NONE, FEAT_PMP, FEAT_EXT_N};
+enum features_e{FEAT_NONE, FEAT_PMP, FEAT_EXT_N, FEAT_CLIC};

 template <typename BASE, features_e FEAT=FEAT_NONE> class riscv_hart_mu_p : public BASE {
 protected:
@@ -183,10 +183,10 @@ public:
    };
    using hart_state_type = hart_state<reg_t>;

-    constexpr reg_t get_irq_mask(size_t mode) {
+    constexpr reg_t get_irq_wrmask(size_t mode) {
        std::array<const reg_t, 4> m = {{
            0b000100010001, // U mode
-            0,              // S mode
+            0b001100110011, // S mode
            0,
            0b100110011001  // M mode
        }};
@@ -263,6 +263,9 @@ protected:
    virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
    virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);

+    iss::status read_clic(uint64_t addr, unsigned length, uint8_t *const data);
+    iss::status write_clic(uint64_t addr, unsigned length, const uint8_t *const data);
+
    virtual iss::status read_csr(unsigned addr, reg_t &val);
    virtual iss::status write_csr(unsigned addr, reg_t val);

@@ -287,26 +290,44 @@ protected:
    std::unordered_map<uint64_t, uint8_t> atomic_reservation;
    std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
    std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
+    uint8_t clic_cfg_reg{0};
+    uint32_t clic_info_reg{0};
+    std::array<uint32_t, 32> clic_inttrig_reg;
+    union clic_int_reg_t {
+        struct{
+            uint8_t ip;
+            uint8_t ie;
+            uint8_t attr;
+            uint8_t ctl;
+        };
+        uint32_t raw;
+    };
+    std::vector<clic_int_reg_t> clic_int_reg;

 private:
-    iss::status read_reg(unsigned addr, reg_t &val);
-    iss::status write_reg(unsigned addr, reg_t val);
+    iss::status read_csr_reg(unsigned addr, reg_t &val);
+    iss::status write_csr_reg(unsigned addr, reg_t val);
    iss::status read_null(unsigned addr, reg_t &val);
    iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;}
    iss::status read_cycle(unsigned addr, reg_t &val);
    iss::status write_cycle(unsigned addr, reg_t val);
    iss::status read_instret(unsigned addr, reg_t &val);
    iss::status write_instret(unsigned addr, reg_t val);
-    iss::status read_mtvec(unsigned addr, reg_t &val);
+    iss::status read_tvec(unsigned addr, reg_t &val);
    iss::status read_time(unsigned addr, reg_t &val);
    iss::status read_status(unsigned addr, reg_t &val);
    iss::status write_status(unsigned addr, reg_t val);
+    iss::status write_cause(unsigned addr, reg_t val);
    iss::status read_ie(unsigned addr, reg_t &val);
    iss::status write_ie(unsigned addr, reg_t val);
    iss::status read_ip(unsigned addr, reg_t &val);
    iss::status write_ip(unsigned addr, reg_t val);
+    iss::status write_ideleg(unsigned addr, reg_t val);
+    iss::status write_edeleg(unsigned addr, reg_t val);
    iss::status read_hartid(unsigned addr, reg_t &val);
-    iss::status write_mepc(unsigned addr, reg_t val);
+    iss::status write_epc(unsigned addr, reg_t val);
+    iss::status write_intstatus(unsigned addr, reg_t val);
+    iss::status write_intthresh(unsigned addr, reg_t val);

    reg_t mhartid_reg{0x0};
    std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
@@ -314,6 +335,11 @@ private:

 protected:
    void check_interrupt();
+    bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
+    uint64_t clic_base_addr{0};
+    unsigned clic_num_irq{0};
+    unsigned clic_num_trigger{0};
+    unsigned mcause_max_irq{16};
 };

 template <typename BASE, features_e FEAT>
@@ -323,34 +349,39 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
    // reset values
    csr[misa] = traits<BASE>::MISA_VAL;
    csr[mvendorid] = 0x669;
-    csr[marchid] = 0x80000003;
+    csr[marchid] = 0x80000004;
    csr[mimpid] = 1;
+    csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file

    uart_buf.str("");
    for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
+        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
+        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
+        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
    }
    for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
-        //csr_wr_cb[addr] = &this_class::write_reg;
+        //csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    // common regs
-    const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}};
+    const std::array<unsigned, 14> addrs{{
+        misa, mvendorid, marchid, mimpid,
+        mepc, mtvec, mscratch, mcause, mtval,
+        uepc, utvec, uscratch, ucause, utval,
+    }};
    for(auto addr: addrs) {
-        csr_rd_cb[addr] = &this_class::read_reg;
-        csr_wr_cb[addr] = &this_class::write_reg;
+        csr_rd_cb[addr] = &this_class::read_csr_reg;
+        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    // special handling & overrides
    csr_rd_cb[time] = &this_class::read_time;
@@ -370,21 +401,16 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
    csr_wr_cb[minstreth] = &this_class::write_instret;
    csr_rd_cb[mstatus] = &this_class::read_status;
    csr_wr_cb[mstatus] = &this_class::write_status;
-    csr_rd_cb[ustatus] = &this_class::read_status;
-    csr_wr_cb[ustatus] = &this_class::write_status;
+    csr_wr_cb[mcause] = &this_class::write_cause;
+    csr_rd_cb[mtvec] = &this_class::read_tvec;
+    csr_wr_cb[mepc] = &this_class::write_epc;
    csr_rd_cb[mip] = &this_class::read_ip;
    csr_wr_cb[mip] = &this_class::write_ip;
-    csr_rd_cb[uip] = &this_class::read_ip;
-    csr_wr_cb[uip] = &this_class::write_ip;
    csr_rd_cb[mie] = &this_class::read_ie;
    csr_wr_cb[mie] = &this_class::write_ie;
-    csr_rd_cb[uie] = &this_class::read_ie;
-    csr_wr_cb[uie] = &this_class::write_ie;
    csr_rd_cb[mhartid] = &this_class::read_hartid;
    csr_rd_cb[mcounteren] = &this_class::read_null;
    csr_wr_cb[mcounteren] = &this_class::write_null;
-    csr_rd_cb[mtvec] = &this_class::read_mtvec;
-    csr_wr_cb[mepc] = &this_class::write_mepc;
    csr_wr_cb[misa] = &this_class::write_null;
    csr_wr_cb[mvendorid] = &this_class::write_null;
    csr_wr_cb[marchid] = &this_class::write_null;
@@ -392,19 +418,51 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()

    if(FEAT & FEAT_PMP){
        for(size_t i=pmpaddr0; i<=pmpaddr15; ++i){
-            csr_rd_cb[i] = &this_class::read_reg;
-            csr_wr_cb[i] = &this_class::write_reg;
+            csr_rd_cb[i] = &this_class::read_csr_reg;
+            csr_wr_cb[i] = &this_class::write_csr_reg;
        }
        for(size_t i=pmpcfg0; i<=pmpcfg3; ++i){
-            csr_rd_cb[i] = &this_class::read_reg;
-            csr_wr_cb[i] = &this_class::write_reg;
+            csr_rd_cb[i] = &this_class::read_csr_reg;
+            csr_wr_cb[i] = &this_class::write_csr_reg;
        }
    }
    if(FEAT & FEAT_EXT_N){
-        csr_rd_cb[mideleg] = &this_class::read_reg;
-        csr_wr_cb[mideleg] = &this_class::write_reg;
-        csr_rd_cb[medeleg] = &this_class::read_reg;
-        csr_wr_cb[medeleg] = &this_class::write_reg;
+        csr_rd_cb[mideleg] = &this_class::read_csr_reg;
+        csr_wr_cb[mideleg] = &this_class::write_ideleg;
+        csr_rd_cb[medeleg] = &this_class::read_csr_reg;
+        csr_wr_cb[medeleg] = &this_class::write_edeleg;
+        csr_rd_cb[uie] = &this_class::read_ie;
+        csr_wr_cb[uie] = &this_class::write_ie;
+        csr_rd_cb[uip] = &this_class::read_ip;
+        csr_wr_cb[uip] = &this_class::write_ip;
+        csr_wr_cb[uepc] = &this_class::write_epc;
+        csr_rd_cb[ustatus] = &this_class::read_status;
+        csr_wr_cb[ustatus] = &this_class::write_status;
+        csr_wr_cb[ucause] = &this_class::write_cause;
+        csr_rd_cb[utvec] = &this_class::read_tvec;
+    }
+    if(FEAT & FEAT_CLIC) {
+        csr_rd_cb[mtvt] = &this_class::read_csr_reg;
+        csr_wr_cb[mtvt] = &this_class::write_csr_reg;
+        csr_rd_cb[mxnti] = &this_class::read_csr_reg;
+        csr_wr_cb[mxnti] = &this_class::write_csr_reg;
+        csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
+        csr_wr_cb[mintstatus] = &this_class::write_null;
+        csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
+        csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
+        csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg;
+        csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg;
+        csr_rd_cb[mintthresh] = &this_class::read_csr_reg;
+        csr_wr_cb[mintthresh] = &this_class::write_intthresh;
+        csr_rd_cb[mclicbase] = &this_class::read_csr_reg;
+        csr_wr_cb[mclicbase] = &this_class::write_null;
+
+        clic_base_addr=0xC0000000;
+        clic_num_irq=16;
+        clic_int_reg.resize(clic_num_irq);
+        clic_cfg_reg=0x20;
+        clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + clic_num_irq;
+        mcause_max_irq=clic_num_irq+16;
    }
 }

@@ -426,6 +484,7 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
                if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
            if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
            if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
+            auto entry = reader.get_entry();
            for (const auto pseg : reader.segments) {
                const auto fsize = pseg->get_file_size(); // 0x42c/0x0
                const auto seg_data = pseg->get_data();
@@ -438,20 +497,90 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
                                   << pseg->get_physical_address();
                }
            }
-            for (const auto sec : reader.sections) {
-                if (sec->get_name() == ".tohost") {
+            for(const auto sec : reader.sections) {
+                if(sec->get_name() == ".symtab") {
+                    if ( SHT_SYMTAB == sec->get_type() ||
+                            SHT_DYNSYM == sec->get_type() ) {
+                        ELFIO::symbol_section_accessor symbols( reader, sec );
+                        auto sym_no = symbols.get_symbols_num();
+                        std::string   name;
+                        ELFIO::Elf64_Addr    value   = 0;
+                        ELFIO::Elf_Xword     size    = 0;
+                        unsigned char bind    = 0;
+                        unsigned char type    = 0;
+                        ELFIO::Elf_Half      section = 0;
+                        unsigned char other   = 0;
+                        for ( auto i = 0U; i < sym_no; ++i ) {
+                            symbols.get_symbol( i, name, value, size, bind, type, section, other );
+                            if(name=="tohost") {
+                                tohost = value;
+                            } else if(name=="fromhost") {
+                                fromhost = value;
+                            }
+                        }
+                    }
+                } else if (sec->get_name() == ".tohost") {
                    tohost = sec->get_address();
                    fromhost = tohost + 0x40;
                }
-            }

-            return std::make_pair(reader.get_entry(), true);
+            }
+            return std::make_pair(entry, true);
        }
        throw std::runtime_error("memory load file is not a valid elf file");
    }
    throw std::runtime_error("memory load file not found");
 }

+template <typename BASE, features_e FEAT> bool riscv_hart_mu_p<BASE, FEAT>::pmp_check(const access_type type, const uint64_t addr, const unsigned len) {
+    constexpr auto PMP_SHIFT=2U;
+    constexpr auto PMP_R = 0x1U;
+    constexpr auto PMP_W = 0x2U;
+    constexpr auto PMP_X = 0x4U;
+    constexpr auto PMP_A = 0x18U;
+    constexpr auto PMP_L = 0x80U;
+    constexpr auto PMP_TOR =0x1U;
+    constexpr auto PMP_NA4 =0x2U;
+    constexpr auto PMP_NAPOT =0x3U;
+    reg_t base = 0;
+    for (size_t i = 0; i < 16; i++) {
+        reg_t tor = csr[pmpaddr0+i] << PMP_SHIFT;
+        uint8_t cfg = csr[pmpcfg0+(i/4)]>>(i%4);
+        if (cfg & PMP_A) {
+            auto pmp_a = (cfg & PMP_A) >> 3;
+            bool is_tor = pmp_a == PMP_TOR;
+            bool is_na4 = pmp_a == PMP_NA4;
+
+            reg_t mask = (csr[pmpaddr0+i] << 1) | (!is_na4);
+            mask = ~(mask & ~(mask + 1)) << PMP_SHIFT;
+
+            // Check each 4-byte sector of the access
+            bool any_match = false;
+            bool all_match = true;
+            for (reg_t offset = 0; offset < len; offset += 1 << PMP_SHIFT) {
+                reg_t cur_addr = addr + offset;
+                bool napot_match = ((cur_addr ^ tor) & mask) == 0;
+                bool tor_match = base <= cur_addr && cur_addr < tor;
+                bool match = is_tor ? tor_match : napot_match;
+                any_match |= match;
+                all_match &= match;
+            }
+            if (any_match) {
+                // If the PMP matches only a strict subset of the access, fail it
+                if (!all_match)
+                    return false;
+                return  (this->reg.PRIV == PRIV_M && !(cfg & PMP_L)) ||
+                        (type == access_type::READ && (cfg & PMP_R)) ||
+                        (type == access_type::WRITE && (cfg & PMP_W)) ||
+                        (type == access_type::FETCH && (cfg & PMP_X));
+            }
+        }
+        base = tor;
+    }
+    return this->reg.PRIV == PRIV_M;
+}
+
+
 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space,
        const uint64_t addr, const unsigned length, uint8_t *const data) {
@@ -467,6 +596,14 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
    try {
        switch (space) {
        case traits<BASE>::MEM: {
+            if(FEAT & FEAT_PMP){
+                if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) {
+                    fault_data = addr;
+                    if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
+                    this->reg.trap_state = (1 << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1
+                    return iss::Err;
+                }
+            }
            if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
                fault_data = addr;
                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
@@ -480,9 +617,13 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                    fault_data=addr;
                    return iss::Err;
                }
-                auto res = type==iss::address_type::PHYSICAL?
-                        read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
-                        read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
+                auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
+                auto res = iss::Err;
+                if((FEAT & FEAT_CLIC) && access != access_type::FETCH && phys_addr.val>=clic_base_addr && (phys_addr.val+length)<=(clic_base_addr+0x5000)){ //TODO: should be a constant
+                    res = read_clic(phys_addr.val, length, data);
+                } else {
+                    res = read_mem( phys_addr, length, data);
+                }
                if (unlikely(res != iss::Ok)){
                    this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
                    fault_data=addr;
@@ -550,6 +691,14 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
    try {
        switch (space) {
        case traits<BASE>::MEM: {
+            if(FEAT & FEAT_PMP){
+                if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) {
+                    fault_data = addr;
+                    if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
+                    this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 1
+                    return iss::Err;
+                }
+            }
            if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                fault_data = addr;
                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
@@ -557,14 +706,14 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                return iss::Err;
            }
            try {
-                if(length>1 && (addr&(length-1))){
+                if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){
                    this->reg.trap_state = 1<<31 | 6<<16;
                    fault_data=addr;
                    return iss::Err;
                }
-                auto res = type==iss::address_type::PHYSICAL?
-                        write_mem(phys_addr_t{access, space, addr}, length, data):
-                        write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
+                auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
+                auto res = ((FEAT & FEAT_CLIC) && phys_addr.val>=clic_base_addr && (phys_addr.val+length)<=(clic_base_addr+0x5000))? //TODO: should be a constant
+                        write_clic(phys_addr.val, length, data) : write_mem( phys_addr, length, data);
                if (unlikely(res != iss::Ok)) {
                    this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
                    fault_data=addr;
@@ -661,7 +810,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
    return (this->*(it->second))(addr, val);
 }

-template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_reg(unsigned addr, reg_t &val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_csr_reg(unsigned addr, reg_t &val) {
    val = csr[addr];
    return iss::Ok;
 }
@@ -671,7 +820,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
    return iss::Ok;
 }

-template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_reg(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_csr_reg(unsigned addr, reg_t val) {
    csr[addr] = val;
    return iss::Ok;
 }
@@ -740,8 +889,8 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
    return iss::Ok;
 }

-template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_mtvec(unsigned addr, reg_t &val) {
-    val = csr[mtvec] & ~2;
+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_tvec(unsigned addr, reg_t &val) {
+    val = csr[addr] & ~2;
    return iss::Ok;
 }
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_status(unsigned addr, reg_t &val) {
@@ -757,9 +906,8 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
    return iss::Ok;
 }

-template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ie(unsigned addr, reg_t &val) {
-    val = csr[mie];
-    val &= csr[mideleg];
+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
+    csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1))|(mcause_max_irq-1)); //TODO: make exception code size configurable
    return iss::Ok;
 }

@@ -768,32 +916,61 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
    return iss::Ok;
 }

+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ie(unsigned addr, reg_t &val) {
+    auto mask = get_irq_wrmask((addr >> 8) & 0x3);
+    val = csr[mie] & mask;
+    if(this->reg.PRIV!=3)
+        val &= csr[mideleg];
+    return iss::Ok;
+}
+
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
-    auto req_priv_lvl = (addr >> 8) & 0x3;
-    auto mask = get_irq_mask(req_priv_lvl);
+    auto mask = get_irq_wrmask((addr >> 8) & 0x3);
+    if(this->reg.PRIV==0)
+        mask&= ~(0xff<<4); // STIE and UTIE are read only in user and supervisor mode
    csr[mie] = (csr[mie] & ~mask) | (val & mask);
    check_interrupt();
    return iss::Ok;
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ip(unsigned addr, reg_t &val) {
-    val = csr[mip];
+    auto mask = get_irq_wrmask((addr >> 8) & 0x3);
+    val = csr[mip] & mask;
+    if(this->reg.PRIV!=3)
        val &= csr[mideleg];
    return iss::Ok;
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ip(unsigned addr, reg_t val) {
-    auto req_priv_lvl = (addr >> 8) & 0x3;
-    auto mask = get_irq_mask(req_priv_lvl);
-    mask &= ~(1 << 7); // MTIP is read only
+    auto mask = get_irq_wrmask((addr >> 8) & 0x3);
+    mask &= ~(8 << 4); // MTIP is read only
+    if(this->reg.PRIV!=3)
+        mask &= ~(3 << 4); // STIP and UTIP are read only in user and supervisor mode
    csr[mip] = (csr[mip] & ~mask) | (val & mask);
    check_interrupt();
    return iss::Ok;
 }

-template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_mepc(unsigned addr, reg_t val) {
-    auto mask = get_pc_mask();
-    csr[addr] = val;//(csr[addr] & ~mask) | (val & mask);
+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ideleg(unsigned addr, reg_t val) {
+    auto mask = 0b000100010001; // only U mode supported
+    csr[mideleg] = (csr[mideleg] & ~mask) | (val & mask);
+    return iss::Ok;
+}
+
+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_edeleg(unsigned addr, reg_t val) {
+    auto mask = 0b1011001111110111; // bit 14/10 (reserved), bit 11 (Env call), and 3 (break) are hardwired to 0
+    csr[medeleg] = (csr[medeleg] & ~mask) | (val & mask);
+    return iss::Ok;
+}
+
+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_epc(unsigned addr, reg_t val) {
+    csr[addr] = val & get_pc_mask();
+    return iss::Ok;
+}
+
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
+    csr[addr]= val &0xff;
    return iss::Ok;
 }

@@ -900,6 +1077,84 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned l
    return iss::Ok;
 }

+void read_uint32(uint64_t offs, uint32_t& reg, uint8_t *const data, unsigned length) {
+    auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
+    switch (offs & 0x3) {
+    case 0:
+        for (auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + i);
+    break;
+    case 1:
+        for (auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + 1 + i);
+    break;
+    case 2:
+        for (auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + 2 + i);
+    break;
+    case 3:
+        *data = *(reg_ptr + 3);
+    break;
+    }
+}
+
+void write_uint32(uint64_t offs, uint32_t& reg, const uint8_t *const data, unsigned length) {
+    auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
+    switch (offs & 0x3) {
+    case 0:
+        for (auto i = 0U; i < length; ++i)
+            *(reg_ptr + i) = *(data + i);
+    break;
+    case 1:
+        for (auto i = 0U; i < length; ++i)
+            *(reg_ptr + 1 + i) = *(data + i);
+    break;
+    case 2:
+        for (auto i = 0U; i < length; ++i)
+            *(reg_ptr + 2 + i) = *(data + i);
+    break;
+    case 3:
+        *(reg_ptr + 3) = *data ;
+    break;
+    }
+}
+
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_mu_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length, uint8_t *const data) {
+    if(addr==clic_base_addr) { // cliccfg
+        *data=clic_cfg_reg;
+        for(auto i=1; i<length; ++i) *(data+i)=0;
+    } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+8)){ // clicinfo
+        read_uint32(addr, clic_info_reg, data, length);
+    } else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0x40+clic_num_trigger*4)){ // clicinttrig
+        auto offset = ((addr&0x7fff)-0x40)/4;
+        read_uint32(addr, clic_inttrig_reg[offset], data, length);
+    } else if(addr>=(clic_base_addr+0x1000) && (addr+length)<=(clic_base_addr+clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
+        auto offset = ((addr&0x7fff)-0x1000)/4;
+        read_uint32(addr, clic_int_reg[offset].raw, data, length);
+    } else {
+        for(auto i = 0U; i<length; ++i) *(data+i)=0;
+    }
+    return iss::Ok;
+}
+
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
+    if(addr==clic_base_addr) { // cliccfg
+        clic_cfg_reg = *data;
+        clic_cfg_reg&= 0x7f;
+//    } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+4)){ // clicinfo
+//        write_uint32(addr, clic_info_reg, data, length);
+    } else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0xC0)){ // clicinttrig
+        auto offset = ((addr&0x7fff)-0x40)/4;
+        write_uint32(addr, clic_inttrig_reg[offset], data, length);
+    } else if(addr>=(clic_base_addr+0x1000) && (addr+length)<=(clic_base_addr+clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
+        auto offset = ((addr&0x7fff)-0x1000)/4;
+        write_uint32(addr, clic_int_reg[offset].raw, data, length);
+    }
+    return iss::Ok;
+}
+
 template <typename BASE, features_e FEAT> inline void riscv_hart_mu_p<BASE, FEAT>::reset(uint64_t address) {
    BASE::reset(address);
    state.mstatus = hart_state_type::mstatus_reset_val;
@@ -914,7 +1169,7 @@ template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::chec
    auto ena_irq = csr[mip] & csr[mie];

    bool mie = state.mstatus.MIE;
-    auto m_enabled = this->reg.PRIV < PRIV_M || (this->reg.PRIV == PRIV_M && mie);
+    auto m_enabled = this->reg.PRIV < PRIV_M ||  mie;
    auto enabled_interrupts = m_enabled ? ena_irq & ~ideleg : 0;

    if (enabled_interrupts != 0) {
@@ -930,6 +1185,7 @@ template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::chec
 template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
    // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
    // calculate and write mcause val
+    if(flags==std::numeric_limits<uint64_t>::max()) flags=this->reg.trap_state;
    auto trap_id = bit_sub<0, 16>(flags);
    auto cause = bit_sub<16, 15>(flags);
    if (trap_id == 0 && cause == 11) cause = 0x8 + this->reg.PRIV; // adjust environment call cause
@@ -982,11 +1238,8 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
    auto ivec = csr[utvec | (new_priv << 8)];
    // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
    // bits in mtvec
-    this->reg.NEXT_PC = ivec & ~0x1UL;
+    this->reg.NEXT_PC = ivec & ~0x3UL;
    if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
-    // reset trap state
-    this->reg.PRIV = new_priv;
-    this->reg.trap_state = 0;
    std::array<char, 32> buffer;
    sprintf(buffer.data(), "0x%016lx", addr);
    if((flags&0xffffffff) != 0xffffffff)
@@ -994,6 +1247,9 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
                       << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
                       << " at address " << buffer.data() << " occurred, changing privilege level from "
                       << lvl[this->reg.PRIV] << " to " << lvl[new_priv];
+    // reset trap state
+    this->reg.PRIV = new_priv;
+    this->reg.trap_state = 0;
    return this->reg.NEXT_PC;
 }

--- a/incl/sysc/core_complex.h
+++ b/incl/sysc/core_complex.h
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017-2021 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -30,23 +30,23 @@
 *
 *******************************************************************************/

-#ifndef _SYSC_SIFIVE_FE310_H_
-#define _SYSC_SIFIVE_FE310_H_
+#ifndef _SYSC_CORE_COMPLEX_H_
+#define _SYSC_CORE_COMPLEX_H_

-#include "tlm/scc/initiator_mixin.h"
-#include "scc/traceable.h"
-#include "scc/utilities.h"
-#include "tlm/scc/scv/tlm_rec_initiator_socket.h"
+#include <tlm/scc/initiator_mixin.h>
+#include <scc/traceable.h>
+#include <scc/tick2time.h>
+#include <scc/utilities.h>
+#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
+#ifdef CWR_SYSTEMC
+#include <scmlinc/scml_property.h>
+#else
 #include <cci_configuration>
+#endif
 #include <tlm>
-#include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
 #include <tlm_utils/tlm_quantumkeeper.h>
 #include <util/range_lut.h>
-
-class scv_tr_db;
-class scv_tr_stream;
-struct _scv_tr_generator_default_data;
-template <class T_begin, class T_end> class scv_tr_generator;
+#include <memory>

 namespace sysc {

@@ -62,13 +62,12 @@ public:

 namespace tgfs {
 class core_wrapper;
+struct core_trace;

 class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
    tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};

-    sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
-
    sc_core::sc_in<bool> rst_i{"rst_i"};

    sc_core::sc_in<bool> global_irq_i{"global_irq_i"};
@@ -79,6 +78,9 @@ public:

    sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i{"local_irq_i", 16};

+#ifndef CWR_SYSTEMC
+	sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
+
    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;

    cci::cci_param<std::string> elf_file{"elf_file", ""};
@@ -97,7 +99,47 @@ public:

    cci::cci_param<uint32_t> mhartid{"mhartid", 0};

-    core_complex(sc_core::sc_module_name name);
+    core_complex(sc_core::sc_module_name const& name);
+
+#else
+	sc_core::sc_in<bool> clk_i{"clk_i"};
+
+	sc_core::sc_in<uint64_t> mtime_i{"mtime_i"};
+
+	scml_property<std::string> elf_file{"elf_file", ""};
+
+    scml_property<bool> enable_disass{"enable_disass", false};
+
+    scml_property<unsigned long long> reset_address{"reset_address", 0ULL};
+
+    scml_property<std::string> core_type{"core_type", "tgc_c"};
+
+    scml_property<std::string> backend{"backend", "interp"};
+
+    scml_property<unsigned> gdb_server_port{"gdb_server_port", 0};
+
+    scml_property<bool> dump_ir{"dump_ir", false};
+
+    scml_property<uint32_t> mhartid{"mhartid", 0};
+
+    core_complex(sc_core::sc_module_name const& name)
+    : sc_module(name)
+    , local_irq_i{"local_irq_i", 16}
+    , elf_file{"elf_file", ""}
+    , enable_disass{"enable_disass", false}
+    , reset_address{"reset_address", 0ULL}
+    , core_type{"core_type", "tgc_c"}
+    , backend{"backend", "interp"}
+    , gdb_server_port{"gdb_server_port", 0}
+    , dump_ir{"dump_ir", false}
+    , mhartid{"mhartid", 0}
+    , read_lut(tlm_dmi_ext())
+    , write_lut(tlm_dmi_ext())
+    {
+    	init();
+    }
+
+#endif

    ~core_complex();

@@ -121,13 +163,14 @@ public:

    void trace(sc_core::sc_trace_file *trf) const override;

-    void disass_output(uint64_t pc, const std::string instr);
+    bool disass_output(uint64_t pc, const std::string instr);

+    void set_clock_period(sc_core::sc_time period);
 protected:
    void before_end_of_elaboration() override;
    void start_of_simulation() override;
+	void forward();
    void run();
-    void clk_cb();
    void rst_cb();
    void sw_irq_cb();
    void timer_irq_cb();
@@ -136,21 +179,14 @@ protected:
    util::range_lut<tlm_dmi_ext> read_lut, write_lut;
    tlm_utils::tlm_quantumkeeper quantum_keeper;
    std::vector<uint8_t> write_buf;
-    std::unique_ptr<core_wrapper> cpu;
-    sc_core::sc_time curr_clk;
-#ifdef WITH_SCV
-    //! transaction recording database
-    scv_tr_db *m_db;
-    //! blocking transaction recording stream handle
-    scv_tr_stream *stream_handle;
-    //! transaction generator handle for blocking transactions
-    scv_tr_generator<_scv_tr_generator_default_data, _scv_tr_generator_default_data> *instr_tr_handle;
-    scv_tr_generator<uint64_t, _scv_tr_generator_default_data> *fetch_tr_handle;
-    scv_tr_handle tr_handle;
-#endif
+    core_wrapper* cpu{nullptr};
+    sc_core::sc_signal<sc_core::sc_time> curr_clk;
+    core_trace* trc{nullptr};
+    std::unique_ptr<scc::tick2time> t2t;
+private:
+    void init();
 };
-
 } /* namespace SiFive */
 } /* namespace sysc */

-#endif /* _SYSC_SIFIVE_FE310_H_ */
+#endif /* _SYSC_CORE_COMPLEX_H_ */
--- a/softfloat/build/Linux-x86_64-GCC/platform.h
+++ b/softfloat/build/Linux-x86_64-GCC/platform.h
@@ -49,7 +49,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
+#ifdef __GNUC__
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #define SOFTFLOAT_INTRINSIC_INT128 1
+#endif
 #include "opts-GCC.h"

--- a/src/main.cpp
+++ b/src/main.cpp
@@ -47,7 +47,7 @@ using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
 #ifdef CORE_TGC_D
 #include "iss/arch/riscv_hart_mu_p.h"
 #include "iss/arch/tgc_d.h"
-using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::FEAT_PMP>;
+using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
 #ifdef WITH_LLVM
 #include <iss/llvm/jit_helper.h>
@@ -78,7 +78,7 @@ int main(int argc, char *argv[]) {
        ("mem,m", po::value<std::string>(), "the memory input file")
        ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
        ("backend", po::value<std::string>()->default_value("interp"), "the memory input file")
-        ("isa", po::value<std::string>()->default_value("tgf_c"), "isa to use for simulation");
+        ("isa", po::value<std::string>()->default_value("tgc_c"), "isa to use for simulation");
    // clang-format on
    auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
    try {
@@ -123,24 +123,24 @@ int main(int argc, char *argv[]) {
        iss::vm_ptr vm{nullptr};
        iss::cpu_ptr cpu{nullptr};
        std::string isa_opt(clim["isa"].as<std::string>());
-        if (isa_opt == "tgf_c") {
+        if (isa_opt == "tgc_c") {
            std::tie(cpu, vm) =
                iss::create_cpu<tgc_c_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
        } else
 #ifdef CORE_TGC_B
-        if (isa_opt == "tgf_b") {
+        if (isa_opt == "tgc_b") {
            std::tie(cpu, vm) =
                iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
        } else
 #endif
 #ifdef CORE_TGC_D
-        if (isa_opt == "tgf_d") {
+        if (isa_opt == "tgc_d") {
            std::tie(cpu, vm) =
                iss::create_cpu<tgc_d_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
        } else
 #endif
        {
-            LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
+            LOG(ERR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
            return 127;
        }
        if (clim.count("plugin")) {
@@ -161,7 +161,7 @@ int main(int argc, char *argv[]) {
                    vm->register_plugin(*ce_plugin);
                    plugin_list.push_back(ce_plugin);
                } else {
-                    LOG(ERROR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
+                    LOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
                    return 127;
                }
            }
@@ -196,7 +196,7 @@ int main(int argc, char *argv[]) {
        auto cycles = clim["instructions"].as<uint64_t>();
        res = vm->start(cycles, dump);
    } catch (std::exception &e) {
-        LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
+        LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
                   << std::endl;
        res = 2;
    }
--- a/src/plugin/cycle_estimate.cpp
+++ b/src/plugin/cycle_estimate.cpp
@@ -47,10 +47,10 @@ iss::plugin::cycle_estimate::cycle_estimate(std::string config_file_name)
            try {
                is >> root;
            } catch (Json::RuntimeError &e) {
-                LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
            }
        } else {
-            LOG(ERROR) << "Could not open input file " << config_file_name;
+            LOG(ERR) << "Could not open input file " << config_file_name;
        }
    }
 }
@@ -77,7 +77,7 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
    		}
    	}
    } else {
-        LOG(ERROR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
+        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
    }
 	return true;

@@ -87,6 +87,8 @@ void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info co
    assert(arch_instr && "No instrumentation interface available but callback executed");
 	auto entry = delays[instr_info.instr_id];
 	bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8);
-    uint32_t delay = taken ? entry.taken : entry.not_taken;
-    if(delay>1) arch_instr->set_curr_instr_cycles(delay);
+    if (taken && entry.taken > 1)
+        arch_instr->set_curr_instr_cycles(entry.taken);
+    else if (entry.not_taken > 1)
+        arch_instr->set_curr_instr_cycles(entry.not_taken);
 }
--- a/src/plugin/instruction_count.cpp
+++ b/src/plugin/instruction_count.cpp
@@ -46,10 +46,10 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name)
            try {
                is >> root;
            } catch (Json::RuntimeError &e) {
-                LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
            }
        } else {
-            LOG(ERROR) << "Could not open input file " << config_file_name;
+            LOG(ERR) << "Could not open input file " << config_file_name;
        }
    }
 }
@@ -85,7 +85,7 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
    	}
    	rep_counts.resize(delays.size());
    } else {
-        LOG(ERROR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
+        LOG(ERR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
    }
 	return true;
 }
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -30,6 +30,13 @@
 *
 *******************************************************************************/

+// clang-format off
+#include "iss/debugger/gdb_session.h"
+#include "iss/debugger/encoderdecoder.h"
+#include "iss/debugger/server.h"
+#include "iss/debugger/target_adapter_if.h"
+#include "iss/iss.h"
+#include "iss/vm_types.h"
 #include "sysc/core_complex.h"
 #ifdef CORE_TGC_B
 #include "iss/arch/riscv_hart_m_p.h"
@@ -44,23 +51,33 @@ using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
 #include "iss/arch/tgc_d.h"
 using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::FEAT_PMP>;
 #endif
-#include "iss/debugger/encoderdecoder.h"
-#include "iss/debugger/gdb_session.h"
-#include "iss/debugger/server.h"
-#include "iss/debugger/target_adapter_if.h"
-#include "iss/iss.h"
-#include "iss/vm_types.h"
 #include "scc/report.h"
 #include <iostream>
 #include <sstream>
+#include <array>
+// clang-format on

 #define STR(X) #X
 #define CREATE_CORE(CN) \
 if (type == STR(CN)) { std::tie(cpu, vm) = create_core<CN ## _plat_type>(backend, gdb_port, hart_id); } else

 #ifdef WITH_SCV
-#include <array>
 #include <scv.h>
+#else
+#include <scv-tr.h>
+using namespace scv_tr;
+#endif
+
+#ifndef CWR_SYSTEMC
+#define GET_PROP_VALUE(P) P.get_value()
+#else
+#define GET_PROP_VALUE(P) P.getValue()
+#endif
+
+#ifdef _MSC_VER
+// not #if defined(_WIN32) || defined(_WIN64) because we have strncasecmp in mingw
+#define strncasecmp _strnicmp
+#define strcasecmp _stricmp
 #endif

 namespace sysc {
@@ -100,15 +117,14 @@ public:
    sync_type needed_sync() const override { return PRE_SYNC; }

    void disass_output(uint64_t pc, const std::string instr) override {
-        if (INFO <= Log<Output2FILE<disass>>::reporting_level() && Output2FILE<disass>::stream()) {
+        if (!owner->disass_output(pc, instr)) {
            std::stringstream s;
            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
              << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
-            Log<Output2FILE<disass>>().get(INFO, "disass")
+            SCCDEBUG(owner->name())<<"disass: "
                << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
                << std::setfill(' ') << std::left << instr << s.str();
        }
-        owner->disass_output(pc, instr);
    };

    status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) override {
@@ -135,6 +151,7 @@ public:
    }

    status read_csr(unsigned addr, reg_t &val) override {
+#ifndef CWR_SYSTEMC
        if((addr==arch::time || addr==arch::timeh) && owner->mtime_o.get_interface(0)){
            uint64_t time_val;
            bool ret = owner->mtime_o->nb_peek(time_val);
@@ -145,6 +162,17 @@ public:
                val = static_cast<reg_t>(time_val >> 32);
            }
            return ret?Ok:Err;
+#else
+		if((addr==arch::time || addr==arch::timeh)){
+			uint64_t time_val = owner->mtime_i.read();
+			if (addr == iss::arch::time) {
+				val = static_cast<reg_t>(time_val);
+			} else if (addr == iss::arch::timeh) {
+				if (sizeof(reg_t) != 4) return iss::Err;
+				val = static_cast<reg_t>(time_val >> 32);
+			}
+			return Ok;
+#endif
        } else {
            return PLAT::read_csr(addr, val);
        }
@@ -267,7 +295,7 @@ public:
        CREATE_CORE(tgc_d)
 #endif
        {
-            LOG(ERROR) << "Illegal argument value for core type: " << type << std::endl;
+            LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
        }
        auto *srv = debugger::server<debugger::gdb_session>::get();
        if (srv) tgt_adapter = srv->get_target();
@@ -285,18 +313,29 @@ public:
    iss::debugger::target_adapter_if *tgt_adapter{nullptr};
 };

-core_complex::core_complex(sc_module_name name)
+struct core_trace {
+    //! transaction recording database
+    scv_tr_db *m_db{nullptr};
+    //! blocking transaction recording stream handle
+    scv_tr_stream *stream_handle{nullptr};
+    //! transaction generator handle for blocking transactions
+    scv_tr_generator<_scv_tr_generator_default_data, _scv_tr_generator_default_data> *instr_tr_handle{nullptr};
+    scv_tr_handle tr_handle;
+};
+
+SC_HAS_PROCESS(core_complex);// NOLINT
+#ifndef CWR_SYSTEMC
+core_complex::core_complex(sc_module_name const& name)
 : sc_module(name)
 , read_lut(tlm_dmi_ext())
 , write_lut(tlm_dmi_ext())
-#ifdef WITH_SCV
-, m_db(scv_tr_db::get_default_db())
-, stream_handle(nullptr)
-, instr_tr_handle(nullptr)
-, fetch_tr_handle(nullptr)
-#endif
 {
-    SC_HAS_PROCESS(core_complex);// NOLINT
+	init();
+}
+#endif
+
+void core_complex::init(){
+	trc=new core_trace();
    initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
        auto lut_entry = read_lut.getEntry(start);
        if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
@@ -309,8 +348,6 @@ core_complex::core_complex(sc_module_name name)
    });

    SC_THREAD(run);
-    SC_METHOD(clk_cb);
-    sensitive << clk_i;
    SC_METHOD(rst_cb);
    sensitive << rst_i;
    SC_METHOD(sw_irq_cb);
@@ -319,61 +356,82 @@ core_complex::core_complex(sc_module_name name)
    sensitive << timer_irq_i;
    SC_METHOD(global_irq_cb);
    sensitive << global_irq_i;
+    trc->m_db=scv_tr_db::get_default_db();
+
+	SC_METHOD(forward);
+#ifndef CWR_SYSTEMC
+	sensitive<<clk_i;
+#else
+	sensitive<<curr_clk;
+	t2t.reset(new scc::tick2time{"t2t"});
+	t2t->clk_i(clk_i);
+	t2t->clk_o(curr_clk);
+#endif
 }

-core_complex::~core_complex() = default;
+core_complex::~core_complex(){
+    delete cpu;
+    delete trc;
+}

 void core_complex::trace(sc_trace_file *trf) const {}

 void core_complex::before_end_of_elaboration() {
-    SCCDEBUG(SCMOD)<<"instantiating iss::arch::tgf with "<<backend.get_value()<<" backend";
-    cpu = scc::make_unique<core_wrapper>(this);
-    cpu->create_cpu(core_type.get_value(), backend.get_value(), gdb_server_port.get_value(), mhartid.get_value());
+    SCCDEBUG(SCMOD)<<"instantiating iss::arch::tgf with "<<GET_PROP_VALUE(backend)<<" backend";
+    // cpu = scc::make_unique<core_wrapper>(this);
+    cpu = new core_wrapper(this);
+    cpu->create_cpu(GET_PROP_VALUE(core_type), GET_PROP_VALUE(backend), GET_PROP_VALUE(gdb_server_port), GET_PROP_VALUE(mhartid));
    sc_assert(cpu->vm!=nullptr);
-#ifdef WITH_SCV
-    cpu->vm->setDisassEnabled(enable_disass.get_value() || m_db != nullptr);
-#else
-    cpu->vm->setDisassEnabled(enable_disass.get_value());
-#endif
+    cpu->vm->setDisassEnabled(GET_PROP_VALUE(enable_disass) || trc->m_db != nullptr);
 }

 void core_complex::start_of_simulation() {
    quantum_keeper.reset();
-    if (elf_file.get_value().size() > 0) {
-        istringstream is(elf_file.get_value());
+    if (GET_PROP_VALUE(elf_file).size() > 0) {
+        istringstream is(GET_PROP_VALUE(elf_file));
        string s;
        while (getline(is, s, ',')) {
            std::pair<uint64_t, bool> start_addr = cpu->load_file(s);
+#ifndef CWR_SYSTEMC
            if (reset_address.is_default_value() && start_addr.second == true)
                reset_address.set_value(start_addr.first);
+#else
+            if (start_addr.second == true)
+                reset_address=start_addr.first;
+#endif
        }
    }
-#ifdef WITH_SCV
-    if (m_db != nullptr && stream_handle == nullptr) {
+    if (trc->m_db != nullptr && trc->stream_handle == nullptr) {
        string basename(this->name());
-        stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", m_db);
-        instr_tr_handle = new scv_tr_generator<>("execute", *stream_handle);
-        fetch_tr_handle = new scv_tr_generator<uint64_t>("fetch", *stream_handle);
+        trc->stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", trc->m_db);
+        trc->instr_tr_handle = new scv_tr_generator<>("execute", *trc->stream_handle);
    }
+}
+
+bool core_complex::disass_output(uint64_t pc, const std::string instr_str) {
+    if (trc->m_db == nullptr) return false;
+    if (trc->tr_handle.is_active()) trc->tr_handle.end_transaction();
+    trc->tr_handle = trc->instr_tr_handle->begin_transaction();
+    trc->tr_handle.record_attribute("PC", pc);
+    trc->tr_handle.record_attribute("INSTR", instr_str);
+    trc->tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
+    trc->tr_handle.record_attribute("MSTATUS", cpu->get_state());
+    trc->tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000);
+    return true;
+}
+
+void core_complex::forward() {
+#ifndef CWR_SYSTEMC
+	set_clock_period(clk_i.read());
+#else
+	set_clock_period(curr_clk.read());
+
 #endif
 }

-void core_complex::disass_output(uint64_t pc, const std::string instr_str) {
-#ifdef WITH_SCV
-    if (m_db == nullptr) return;
-    if (tr_handle.is_active()) tr_handle.end_transaction();
-    tr_handle = instr_tr_handle->begin_transaction();
-    tr_handle.record_attribute("PC", pc);
-    tr_handle.record_attribute("INSTR", instr_str);
-    tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
-    tr_handle.record_attribute("MSTATUS", cpu->get_state());
-    tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000);
-#endif
-}
-
-void core_complex::clk_cb() {
-    curr_clk = clk_i.read();
-    if (curr_clk == SC_ZERO_TIME) cpu->set_interrupt_execution(true);
+void core_complex::set_clock_period(sc_core::sc_time period) {
+	curr_clk = period;
+    if (period == SC_ZERO_TIME) cpu->set_interrupt_execution(true);
 }

 void core_complex::rst_cb() {
@@ -390,11 +448,11 @@ void core_complex::run() {
    wait(SC_ZERO_TIME); // separate from elaboration phase
    do {
        if (rst_i.read()) {
-            cpu->reset(reset_address.get_value());
+            cpu->reset(GET_PROP_VALUE(reset_address));
            wait(rst_i.negedge_event());
        }
-        while (clk_i.read() == SC_ZERO_TIME) {
-            wait(clk_i.value_changed_event());
+        while (curr_clk.read() == SC_ZERO_TIME) {
+            wait(curr_clk.value_changed_event());
        }
        cpu->set_interrupt_execution(false);
        cpu->start();
@@ -418,15 +476,13 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
        gp.set_data_length(length);
        gp.set_streaming_width(length);
        sc_time delay=quantum_keeper.get_local_time();
-#ifdef WITH_SCV
-        if (m_db != nullptr && tr_handle.is_valid()) {
-            if (is_fetch && tr_handle.is_active()) {
-                tr_handle.end_transaction();
+        if (trc->m_db != nullptr && trc->tr_handle.is_valid()) {
+            if (is_fetch && trc->tr_handle.is_active()) {
+                trc->tr_handle.end_transaction();
            }
-            auto preExt = new tlm::scc::scv::tlm_recording_extension(tr_handle, this);
+            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
            gp.set_extension(preExt);
        }
-#endif
        initiator->b_transport(gp, delay);
        SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : " << data;
        if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
@@ -467,12 +523,10 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
        gp.set_data_length(length);
        gp.set_streaming_width(length);
        sc_time delay=quantum_keeper.get_local_time();
-#ifdef WITH_SCV
-        if (m_db != nullptr && tr_handle.is_valid()) {
-            auto preExt = new tlm::scc::scv::tlm_recording_extension(tr_handle, this);
+        if (trc->m_db != nullptr && trc->tr_handle.is_valid()) {
+            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
            gp.set_extension(preExt);
        }
-#endif
        initiator->b_transport(gp, delay);
        quantum_keeper.set(delay);
        SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : " << data;
@@ -535,6 +589,5 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *
        return initiator->transport_dbg(gp) == length;
    }
 }
-
 } /* namespace SiFive */
 } /* namespace sysc */
--- a/src/vm/interp/vm_tgc_c.cpp
+++ b/src/vm/interp/vm_tgc_c.cpp
@@ -30,23 +30,21 @@
 *
 *******************************************************************************/

-#include "../fp_functions.h"
-#include <iss/arch/tgc_c.h>
-#include <iss/arch/riscv_hart_m_p.h>
+// clang-format off
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
+#include <iss/arch/tgc_c.h>
+#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/interp/vm_base.h>
+#include "../fp_functions.h"
 #include <util/logging.h>
 #include <sstream>
-
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
 #include <fmt/format.h>

 #include <array>
 #include <iss/debugger/riscv_target_adapter.h>
+// clang-format on

 namespace iss {
 namespace interp {
@@ -843,7 +841,7 @@ private:
        try {
        {
            uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
-            int16_t res = (int16_t)readSpace2(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
+            int16_t res = (int16_t)readSpace2(traits::MEM, load_address);
            if(rd != 0) *(X+rd) = res; 
        }
        } catch(...){}
@@ -888,7 +886,7 @@ private:
        try {
        {
            uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
-            int32_t res = (int32_t)readSpace4(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
+            int32_t res = (int32_t)readSpace4(traits::MEM, load_address);
            if(rd != 0) *(X+rd) = (uint32_t)res; 
        }
        } catch(...){}
@@ -977,7 +975,7 @@ private:
        try {
        {
            uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
-            uint16_t res = (uint16_t)readSpace2(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
+            uint16_t res = (uint16_t)readSpace2(traits::MEM, load_address);
            if(rd != 0) *(X+rd) = res; 
        }
        } catch(...){}
@@ -4113,6 +4111,10 @@ inline bool is_count_limit_enabled(finish_cond_e cond){
    return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
 }

+inline bool is_jump_to_self_enabled(finish_cond_e cond){
+    return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
+}
+
 template <typename ARCH>
 typename vm_impl<ARCH>::compile_func vm_impl<ARCH>::decode_inst(code_word_t instr){
    for(auto& e: qlut[instr&0x3]){
@@ -4124,7 +4126,6 @@ typename vm_impl<ARCH>::compile_func vm_impl<ARCH>::decode_inst(code_word_t inst
 template <typename ARCH>
 typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
    // we fetch at max 4 byte, alignment is 2
-    enum {TRAP_ID=1<<16};
    code_word_t insn = 0;
    auto *const data = (uint8_t *)&insn;
    auto pc=start;
@@ -4132,15 +4133,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
            !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
        auto res = fetch_ins(pc, data);
        if(res!=iss::Ok){
-            auto new_pc = super::core.enter_trap(TRAP_ID, pc.val, 0);
-            res = fetch_ins(virt_addr_t{access_type::FETCH, new_pc}, data);
-            if(res!=iss::Ok) throw simulation_stopped(0);
-        }
-        if ((cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF &&
-                (insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+            this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
+            pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
+        } else {
+            if (is_jump_to_self_enabled(cond) && (insn == 0x0000006f || (insn&0xffff)==0xa001))
+                throw simulation_stopped(0); // 'J 0' or 'C.J 0'
            auto f = decode_inst(insn);
            pc = (this->*f)(pc, insn);
        }
+    }
    return pc;
 }
Author	SHA1	Message	Date
Eyck Jentzsch	c8679fca85	remove MSVC warning	2021-10-10 19:56:33 +02:00
Eyck Jentzsch	f0ada1ba8c	add MSVC 16 compatibility	2021-10-10 19:06:41 +02:00
Eyck Jentzsch	09b01af3fa	fix find_package use and debug access alignment check	2021-08-26 22:10:27 +02:00
Eyck Jentzsch	9c8b72693e	correct trap ids of access faults	2021-08-20 09:02:56 +02:00
Eyck Jentzsch	c409e7b7ca	adapt to fixed handling of SystemCPackage	2021-08-19 13:38:29 +02:00
Eyck Jentzsch	2f05083cf0	fix elf loader and pmp check for debug accesses	2021-08-19 10:50:25 +02:00
Eyck Jentzsch	e934049dd4	fix inconsistency due to PA adaptation	2021-08-16 17:55:14 +02:00
Eyck Jentzsch	94f796ebdb	add install target and PA compatibility	2021-08-16 17:02:31 +02:00
Eyck Jentzsch	836ba269e3	fix clic reset values	2021-08-16 15:05:05 +02:00
Eyck Jentzsch	c8681096be	update vm_tgfs_c to match CoreDSL	2021-08-14 10:57:36 +02:00
Eyck Jentzsch	adeffe47ad	fix behavior of riscv_hart_mu_p to match TGC_D	2021-08-12 20:34:10 +02:00
Eyck Jentzsch	d95846a849	fix trap handling if illegal fetch (PMP) and U-mode CSRs	2021-08-01 17:23:22 +02:00
Eyck Jentzsch	af887c286f	fix for #2	2021-07-28 09:09:08 +02:00
Eyck Jentzsch	4ddf50162c	make library naming consistent	2021-07-27 15:55:08 +02:00
Eyck Jentzsch	da819d8890	fix SystemC lib handling in build system	2021-07-27 12:25:31 +02:00
Eyck Jentzsch	5ef5d57d30	Merge branch 'tmp' into develop	2021-07-27 10:49:35 +02:00
Eyck Jentzsch	d7bddd825c	add clic CSRs	2021-07-27 10:47:48 +02:00
Eyck Jentzsch	15f46a87db	adapt core_complex to use scv-tr (scc commit id a3cde47)	2021-07-27 09:38:05 +02:00
Eyck Jentzsch	fc1ae4d57d	update build system	2021-07-26 12:03:52 +02:00