removes use of exceptions to report bus errors

src/iss/arch/riscv_hart_common.h

@@ -230,11 +230,6 @@ public:
     trap_load_access_fault(uint64_t badaddr)
     : trap_access(5 << 16, badaddr) {}
 };
-class illegal_instruction_fault : public trap_access {
-public:
-    illegal_instruction_fault(uint64_t badaddr)
-    : trap_access(2 << 16, badaddr) {}
-};
 class trap_instruction_page_fault : public trap_access {
 public:
     trap_instruction_page_fault(uint64_t badaddr)
@@ -523,10 +518,10 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
             return iss::Err;
         auto req_priv_lvl = (addr >> 8) & 0x3;
         if(this->reg.PRIV < req_priv_lvl) // not having required privileges
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         auto it = csr_rd_cb.find(addr);
         if(it == csr_rd_cb.end() || !it->second) // non existent register
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         return it->second(addr, val);
     }
 
@@ -535,12 +530,12 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
             return iss::Err;
         auto req_priv_lvl = (addr >> 8) & 0x3;
         if(this->reg.PRIV < req_priv_lvl) // not having required privileges
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         if((addr & 0xc00) == 0xc00) // writing to read-only region
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         auto it = csr_wr_cb.find(addr);
         if(it == csr_wr_cb.end() || !it->second) // non existent register
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         return it->second(addr, val);
     }
 
@@ -637,7 +632,7 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
 
     iss::status write_dcsr(unsigned addr, reg_t val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         //                  +-------------- ebreakm
         //                  |   +---------- stepi
         //                  |   |  +++----- cause
@@ -648,28 +643,28 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
 
     iss::status read_debug(unsigned addr, reg_t& val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         val = csr[addr];
         return iss::Ok;
     }
 
     iss::status write_dscratch(unsigned addr, reg_t val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         csr[addr] = val;
         return iss::Ok;
     }
 
     iss::status read_dpc(unsigned addr, reg_t& val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         val = this->reg.DPC;
         return iss::Ok;
     }
 
     iss::status write_dpc(unsigned addr, reg_t val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         this->reg.DPC = val;
         return iss::Ok;
     }

src/sysc/core_complex.cpp

@@ -45,11 +45,10 @@
 #include <scc/report.h>
 #include <util/ities.h>
 #include <iostream>
-#include <sstream>
 #include <array>
-#include <numeric>
 #include <iss/plugin/cycle_estimate.h>
 #include <iss/plugin/instruction_count.h>
+#include <util/ities.h>
 
 // clang-format on
 
@@ -308,19 +307,22 @@ template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::before_end_of_elab
 template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::start_of_simulation() {
     // quantum_keeper.reset();
     if(GET_PROP_VALUE(elf_file).size() > 0) {
-        istringstream is(GET_PROP_VALUE(elf_file));
-        string s;
-        while(getline(is, s, ',')) {
-            std::pair<uint64_t, bool> start_addr = cpu->load_file(s);
+        auto file_names = util::split(GET_PROP_VALUE(elf_file), ',');
+        for(auto& s : file_names) {
+            std::pair<uint64_t, bool> load_result = cpu->load_file(s);
+            if(!std::get<1>(load_result)) {
+                SCCWARN(SCMOD) << "Could not load FW file " << s;
+            } else {
 #ifndef CWR_SYSTEMC
-            if(reset_address.is_default_value() && start_addr.second == true)
-                reset_address.set_value(start_addr.first);
+                if(reset_address.is_default_value())
+                    reset_address.set_value(load_result.first);
 #else
                 if(start_addr.second == true)
                     reset_address = start_addr.first;
 #endif
             }
         }
+    }
     if(trc->m_db != nullptr && trc->stream_handle == nullptr) {
         string basename(this->name());
         trc->stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", trc->m_db);