sends iss output to logfile if logfile is specified

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -976,6 +976,60 @@ if(vector != null) {%>
                 throw new std::runtime_error("Unsupported sew_val");
         }
     }
+    void vector_vector_crypto(uint8_t* V, uint8_t funct6, uint64_t eg_len, uint64_t eg_start, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t egs){
+        switch(egs){
+            case 4:
+                return softvector::vector_vector_crypto<${vlen}, 4>(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1);
+            case 8:
+                return softvector::vector_vector_crypto<${vlen}, 8>(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1);
+            default: 
+                throw new std::runtime_error("Unsupported egs");
+        } 
+    }
+    void vector_scalar_crypto(uint8_t* V, uint8_t funct6, uint64_t eg_len, uint64_t eg_start, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t egs){
+        switch(egs){
+            case 4:
+                return softvector::vector_scalar_crypto<${vlen}, 4>(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1);
+            case 8:
+                return softvector::vector_scalar_crypto<${vlen}, 8>(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1);
+            default: 
+                throw new std::runtime_error("Unsupported egs");
+        } 
+    }
+    void vector_imm_crypto(uint8_t* V, uint8_t funct6, uint64_t eg_len, uint64_t eg_start, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t imm, uint8_t egs){
+        switch(egs){
+            case 4:
+                return softvector::vector_imm_crypto<${vlen}, 4>(V, funct6, eg_len, eg_start, vtype, vd, vs2, imm);
+            case 8:
+                return softvector::vector_imm_crypto<${vlen}, 8>(V, funct6, eg_len, eg_start, vtype, vd, vs2, imm);
+            default: 
+                throw new std::runtime_error("Unsupported egs");
+        } 
+    }
+    void vector_crypto(uint8_t* V, uint8_t funct6, uint64_t eg_len, uint64_t eg_start, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t egs, uint8_t sew){
+        switch(egs){
+            case 4:
+                switch(sew){
+                    case 32:
+                        return softvector::vector_crypto<${vlen}, 4, uint32_t>(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1);
+                    case 64:
+                        return softvector::vector_crypto<${vlen}, 4, uint64_t>(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1);
+                    default: 
+                        throw new std::runtime_error("Unsupported sew");
+                }
+            case 8:
+                switch(sew){
+                    case 32:
+                        return softvector::vector_crypto<${vlen}, 8, uint32_t>(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1);
+                    case 64:
+                        return softvector::vector_crypto<${vlen}, 8, uint64_t>(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1);
+                    default: 
+                        throw new std::runtime_error("Unsupported sew");
+                }            
+            default: 
+                throw new std::runtime_error("Unsupported egs");
+        } 
+    }
 <%}%>
     uint64_t fetch_count{0};
     uint64_t tval{0};

src/iss/arch/riscv_hart_common.h

@@ -230,11 +230,6 @@ public:
     trap_load_access_fault(uint64_t badaddr)
     : trap_access(5 << 16, badaddr) {}
 };
-class illegal_instruction_fault : public trap_access {
-public:
-    illegal_instruction_fault(uint64_t badaddr)
-    : trap_access(2 << 16, badaddr) {}
-};
 class trap_instruction_page_fault : public trap_access {
 public:
     trap_instruction_page_fault(uint64_t badaddr)
@@ -523,10 +518,10 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
             return iss::Err;
         auto req_priv_lvl = (addr >> 8) & 0x3;
         if(this->reg.PRIV < req_priv_lvl) // not having required privileges
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         auto it = csr_rd_cb.find(addr);
         if(it == csr_rd_cb.end() || !it->second) // non existent register
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         return it->second(addr, val);
     }
 
@@ -535,12 +530,12 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
             return iss::Err;
         auto req_priv_lvl = (addr >> 8) & 0x3;
         if(this->reg.PRIV < req_priv_lvl) // not having required privileges
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         if((addr & 0xc00) == 0xc00) // writing to read-only region
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         auto it = csr_wr_cb.find(addr);
         if(it == csr_wr_cb.end() || !it->second) // non existent register
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         return it->second(addr, val);
     }
 
@@ -637,7 +632,7 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
 
     iss::status write_dcsr(unsigned addr, reg_t val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         //                  +-------------- ebreakm
         //                  |   +---------- stepi
         //                  |   |  +++----- cause
@@ -648,28 +643,28 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
 
     iss::status read_debug(unsigned addr, reg_t& val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         val = csr[addr];
         return iss::Ok;
     }
 
     iss::status write_dscratch(unsigned addr, reg_t val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         csr[addr] = val;
         return iss::Ok;
     }
 
     iss::status read_dpc(unsigned addr, reg_t& val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         val = this->reg.DPC;
         return iss::Ok;
     }
 
     iss::status write_dpc(unsigned addr, reg_t val) {
         if(!debug_mode_active())
-            throw illegal_instruction_fault(this->fault_data);
+            return iss::Err;
         this->reg.DPC = val;
         return iss::Ok;
     }
@@ -889,8 +884,7 @@ protected:
 
     instrumentation_if* get_instrumentation_if() override { return &instr_if; };
 
-    using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
+    using csr_type = std::array<typename traits<BASE>::reg_t, 1ULL << 12>;
-    using csr_page_type = typename csr_type::page_type;
     csr_type csr;
 
     std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;

src/iss/debugger/riscv_target_adapter.h

@@ -39,7 +39,6 @@
 #include <iss/iss.h>
 
 #include <array>
-#include <memory>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
 #endif

src/iss/semihosting/semihosting.cpp

@@ -250,7 +250,7 @@ template <typename T> void semihosting_callback<T>::operator()(iss::arch_if* arc
         T cmd_addr = sh_read_field<T>(arch_if_ptr, *parameter);
         T cmd_len = sh_read_field<T>(arch_if_ptr, (*parameter) + 1);
         std::string cmd = sh_read_string<T>(arch_if_ptr, cmd_addr, cmd_len);
-        system(cmd.c_str());
+        auto val = system(cmd.c_str());
         break;
     }
     case semihosting_syscalls::SYS_TICKFREQ: {

src/main.cpp

@@ -99,14 +99,18 @@ int main(int argc, char* argv[]) {
 
     LOGGER(DEFAULT)::print_time() = false;
     LOGGER(connection)::print_time() = false;
+    LOGGER(dbt_rise_iss)::print_time() = false;
+
     auto l = logging::as_log_level(clim["verbose"].as<int>());
     LOGGER(DEFAULT)::reporting_level() = l;
     LOGGER(connection)::reporting_level() = l;
+    LOGGER(dbt_rise_iss)::reporting_level() = l;
     if(clim.count("logfile")) {
         // configure the connection logger
         auto f = fopen(clim["logfile"].as<std::string>().c_str(), "w");
         LOG_OUTPUT(DEFAULT)::stream() = f;
         LOG_OUTPUT(connection)::stream() = f;
+        LOG_OUTPUT(dbt_rise_iss)::stream() = f;
     }
 
     std::vector<iss::vm_plugin*> plugin_list;

src/sysc/core_complex.cpp

@@ -45,11 +45,10 @@
 #include <scc/report.h>
 #include <util/ities.h>
 #include <iostream>
-#include <sstream>
 #include <array>
-#include <numeric>
 #include <iss/plugin/cycle_estimate.h>
 #include <iss/plugin/instruction_count.h>
+#include <util/ities.h>
 
 // clang-format on
 
@@ -308,19 +307,22 @@ template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::before_end_of_elab
 template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::start_of_simulation() {
     // quantum_keeper.reset();
     if(GET_PROP_VALUE(elf_file).size() > 0) {
-        istringstream is(GET_PROP_VALUE(elf_file));
+        auto file_names = util::split(GET_PROP_VALUE(elf_file), ',');
-        string s;
+        for(auto& s : file_names) {
-        while(getline(is, s, ',')) {
+            std::pair<uint64_t, bool> load_result = cpu->load_file(s);
-            std::pair<uint64_t, bool> start_addr = cpu->load_file(s);
+            if(!std::get<1>(load_result)) {
+                SCCWARN(SCMOD) << "Could not load FW file " << s;
+            } else {
 #ifndef CWR_SYSTEMC
-            if(reset_address.is_default_value() && start_addr.second == true)
+                if(reset_address.is_default_value())
-                reset_address.set_value(start_addr.first);
+                    reset_address.set_value(load_result.first);
 #else
                 if(start_addr.second == true)
                     reset_address = start_addr.first;
 #endif
             }
         }
+    }
     if(trc->m_db != nullptr && trc->stream_handle == nullptr) {
         string basename(this->name());
         trc->stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", trc->m_db);