rework core definitions

CMakeLists.txt

@@ -6,6 +6,8 @@ project(dbt-rise-tgc VERSION 1.0.0)
 
 include(GNUInstallDirs)
 
+find_package(elfio)
+
 if(WITH_LLVM)
     if(DEFINED ENV{LLVM_HOME})
         find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)

gen_input/TGC_B.core_desc

@@ -0,0 +1,16 @@
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
+
+Core TGC_B provides RV32I {
+	architectural_state {
+        unsigned XLEN=32;
+        unsigned PCLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000000000100000000;
+        unsigned PGSIZE = 0x1000; //1 << 12;
+        unsigned PGMASK = 0xfff; //PGSIZE-1
+	}
+}
+

gen_input/TGC_C.core_desc

@@ -0,0 +1,15 @@
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
+
+Core TGC_C provides RV32I, RV32M, RV32IC {
+    architectural_state {
+        unsigned XLEN=32;
+        unsigned PCLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned PGSIZE = 0x1000; //1 << 12;
+        unsigned PGMASK = 0xfff; //PGSIZE-1
+    }
+}

gen_input/TGC_D.core_desc

@@ -0,0 +1,13 @@
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
+
+Core TGC_D provides RV32I, RV32M, RV32IC {
+    architectural_state {
+        unsigned XLEN=32;
+        unsigned PCLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000001000100000100;
+    }
+}

gen_input/TGC_D_XRB_MAC.core_desc

@@ -0,0 +1,73 @@
+import "CoreDSL-Instruction-Set-Description/RISCVBase.core_desc"
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
+
+InstructionSet X_RB_MAC extends RISCVBase {
+  architectural_state {
+    register unsigned<64> ACC;
+  }
+
+  instructions {
+    RESET_ACC { // v-- funct7       v-- funct3
+      encoding: 7'd0 :: 10'b0 :: 3'd0 :: 5'b0 :: 7'b0001011;
+      behavior: ACC = 0;
+    }
+    
+    GET_ACC_LO {
+      encoding: 7'd1 :: 10'b0 :: 3'd0 :: rd[4:0] :: 7'b0001011;
+      behavior: if (rd != 0) X[rd] = ACC[31:0];
+    }
+    
+    GET_ACC_HI {
+      encoding: 7'd2 :: 10'b0 :: 3'd0 :: rd[4:0] :: 7'b0001011;
+      behavior: if (rd != 0) X[rd] = ACC[63:32];
+    }
+    
+    MACU_32 {
+      encoding: 7'd0 :: rs2[4:0] :: rs1[4:0] :: 3'd1 :: 5'b0 :: 7'b0001011;
+      behavior: {
+        unsigned<64> mul = X[rs1]    * X[rs2];
+        unsigned<33> add = mul[31:0] + ACC[31:0];
+        ACC = add[31:0];
+      }
+    }
+    
+    MACS_32 {
+      encoding: 7'd1 :: rs2[4:0] :: rs1[4:0] :: 3'd1 :: 5'b0 :: 7'b0001011;
+      behavior: {
+        signed<64> mul = ((signed) X[rs1])    * ((signed) X[rs2]);
+        signed<33> add = ((signed) mul[31:0]) + ((signed) ACC[31:0]);
+        ACC = add[31:0]; // bit range always yields unsigned type
+      }
+    }
+    
+    MACU_64 {
+      encoding: 7'd0 :: rs2[4:0] :: rs1[4:0] :: 3'd2 :: 5'b0 :: 7'b0001011;
+      behavior: {
+        unsigned<64> mul = X[rs1] * X[rs2];
+        unsigned<65> add = mul    + ACC;
+        ACC = add[63:0];
+      }
+    }
+    
+    MACS_64 {
+      encoding: 7'd1 :: rs2[4:0] :: rs1[4:0] :: 3'd2 :: 5'b0 :: 7'b0001011;
+      behavior: {
+        signed<64> mul = ((signed) X[rs1]) * ((signed) X[rs2]);
+        signed<65> add =           mul     + ((signed) ACC);
+        ACC = add[63:0];
+      }
+    }
+  }
+}
+
+Core TGC_D_XRB_MAC provides RV32I, RV32M, RV32IC, X_RB_MAC {
+    architectural_state {
+        unsigned XLEN=32;
+        unsigned PCLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000001000100000100;
+    }
+}

gen_input/TGFS.core_desc

@@ -1,37 +0,0 @@
-import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
-import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
-import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
-
-Core TGC_B provides RV32I {
-	architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000000000100000000;
-        unsigned PGSIZE = 0x1000; //1 << 12;
-        unsigned PGMASK = 0xfff; //PGSIZE-1
-	}
-}
-
-Core TGC_C provides RV32I, RV32M, RV32IC {
-    architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
-        unsigned PGSIZE = 0x1000; //1 << 12;
-        unsigned PGMASK = 0xfff; //PGSIZE-1
-    }
-}
-
-Core TGC_D provides RV32I, RV32M, RV32IC {
-    architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
-    }
-}

incl/iss/arch/riscv_hart_m_p.h

@@ -541,7 +541,7 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
                 return iss::Err;
             }
             try {
-                if(length>1 && (addr&(length-1))){
+                if(!(access && iss::access_type::DEBUG) &&  length>1 && (addr&(length-1))){
                     this->reg.trap_state = 1<<31 | 6<<16;
                     fault_data=addr;
                     return iss::Err;

src/sysc/core_complex.cpp

@@ -109,11 +109,11 @@ public:
     sync_type needed_sync() const override { return PRE_SYNC; }
 
     void disass_output(uint64_t pc, const std::string instr) override {
-        if (!owner->disass_output(pc, instr) && INFO <= Log<Output2FILE<disass>>::reporting_level() && Output2FILE<disass>::stream()) {
+        if (!owner->disass_output(pc, instr)) {
             std::stringstream s;
             s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
               << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
-            Log<Output2FILE<disass>>().get(INFO, "disass")
+            SCCDEBUG(owner->name())<<"disass: "
                 << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
                 << std::setfill(' ') << std::left << instr << s.str();
         }

src/vm/interp/vm_tgc_c.cpp

@@ -4138,8 +4138,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
             this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
             pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
         } else {
-            if (is_jump_to_self_enabled(cond) &&
+            if (is_jump_to_self_enabled(cond) && (insn == 0x0000006f || (insn&0xffff)==0xa001))
-                    (insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+                throw simulation_stopped(0); // 'J 0' or 'C.J 0'
             auto f = decode_inst(insn);
             pc = (this->*f)(pc, insn);
         }