removes debug code

this relates to https://github.com/Minres/DBT-RISE-RISCV/issues/8 :
Debugger loses control when trap vector fetch fails

and https://github.com/Minres/DBT-RISE-RISCV/issues/7 : Two debugger
single-steps are required at reset vector

CMakeLists.txt

@@ -20,6 +20,7 @@ set(LIB_SOURCES
     src/iss/arch/tgc5c.cpp
     src/vm/interp/vm_tgc5c.cpp
     src/vm/fp_functions.cpp
+    src/iss/debugger/csr_names.cpp
     src/iss/semihosting/semihosting.cpp
 )
 

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -38,7 +38,9 @@
 #include <asmjit/asmjit.h>
 #include <util/logging.h>
 #include <iss/instruction_decoder.h>
-
+<%def fcsr = registers.find {it.name=='FCSR'}
+if(fcsr != null) {%>
+#include <vm/fp_functions.h><%}%>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
 #endif
@@ -88,7 +90,6 @@ protected:
     using super::write_reg_to_mem;
     using super::gen_read_mem;
     using super::gen_write_mem;
-    using super::gen_wait;
     using super::gen_leave;
     using super::gen_sync;
    
@@ -100,7 +101,9 @@ protected:
     void gen_block_prologue(jit_holder& jh) override;
     void gen_block_epilogue(jit_holder& jh) override;
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
-
+<%if(fcsr != null) {%>
+    inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}   
+<%}%>
     void gen_instr_prologue(jit_holder& jh);
     void gen_instr_epilogue(jit_holder& jh);
     inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause);
@@ -113,6 +116,9 @@ protected:
         auto sign_mask = 1ULL<<(W-1);
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     }
+<%functions.each{ it.eachLine { %>
+    ${it}<%}%>
+<%}%>
 private:
     /****************************************************************************
      * start opcode definitions
@@ -195,7 +201,7 @@ private:
         gen_raise(jh, 0, 2);
         gen_sync(jh, POST_SYNC, instr_descr.size());
         gen_instr_epilogue(jh);
-        return BRANCH;
+        return ILLEGAL_INSTR;
     }
 };
 
@@ -224,9 +230,9 @@ continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned
         paddr = this->core.virt2phys(pc);
     auto res = this->core.read(paddr, 4, data);
     if (res != iss::Ok)
-        throw trap_access(TRAP_ID, pc.val);
+        return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
-        throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+        return JUMP_TO_SELF;
     ++inst_cnt;
     uint32_t inst_index = instr_decoder.decode_instr(instr);
     compile_func f = nullptr;

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -257,17 +257,21 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
     while(!this->core.should_stop() &&
             !(is_icount_limit_enabled(cond) && icount >= count_limit) &&
             !(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
-        fetch_count++;
+        if(this->debugging_enabled())
+            this->tgt_adapter->check_continue(*PC);
+        pc.val=*PC;
         if(fetch_ins(pc, data)!=iss::Ok){
-            this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
+            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
-            pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
+            process_spawn_blocks();
+            if(this->sync_exec && POST_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
+            pc.val = super::core.enter_trap(arch::traits<ARCH>::RV_CAUSE_FETCH_ACCESS<<16, pc.val, 0);
         } else {
             if (is_jump_to_self_enabled(cond) &&
                     (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
             uint32_t inst_index = instr_decoder.decode_instr(instr);
             opcode_e inst_id = arch::traits<ARCH>::opcode_e::MAX_OPCODE;;
             if(inst_index <instr_descr.size())
-                inst_id = instr_descr.at(instr_decoder.decode_instr(instr)).op;
+                inst_id = instr_descr[inst_index].op;
 
             // pre execution stuff
             this->core.reg.last_branch = 0;
@@ -279,6 +283,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     <%}%>if(this->disass_enabled){
                         /* generate console output when executing the command */<%instr.disass.eachLine{%>
                         ${it}<%}%>
+                        this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers<%instr.usedVariables.each{ k,v->
                     if(v.isArray) {%>
@@ -310,11 +315,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 icount++;
                 instret++;
             }
-            cycle++;
+            *PC = *NEXT_PC;
-            pc.val=*NEXT_PC;
-            this->core.reg.PC = this->core.reg.NEXT_PC;
             this->core.reg.trap_state =  this->core.reg.pending_trap;
         }
+        fetch_count++;
+        cycle++;
     }
     return pc;
 }

gen_input/templates/llvm/CORENAME.cpp.gtl

@@ -37,7 +37,9 @@
 #include <iss/llvm/vm_base.h>
 #include <util/logging.h>
 #include <iss/instruction_decoder.h>
-
+<%def fcsr = registers.find {it.name=='FCSR'}
+if(fcsr != null) {%>
+#include <vm/fp_functions.h><%}%>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
 #endif
@@ -83,7 +85,9 @@ protected:
     using vm_base<ARCH>::get_reg_ptr;
 
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
-
+<%if(fcsr != null) {%>
+    inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}   
+<%}%>
     template <typename T> inline ConstantInt *size(T type) {
         return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
     }
@@ -131,7 +135,9 @@ protected:
         auto sign_mask = 1ULL<<(W-1);
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     }
-
+<%functions.each{ it.eachLine { %>
+    ${it}<%}%>
+<%}%>
 private:
     /****************************************************************************
      * start opcode definitions
@@ -212,7 +218,7 @@ private:
         bb = this->leave_blk;
         this->gen_instr_epilogue(bb);
         this->builder.CreateBr(bb);
-        return std::make_tuple(BRANCH, nullptr);
+        return std::make_tuple(ILLEGAL_INSTR, nullptr);
     }    
 };
 
@@ -247,19 +253,11 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
     auto *const data = (uint8_t *)&instr;
     if(this->core.has_mmu())
         paddr = this->core.virt2phys(pc);
-    //TODO: re-add page handling
-//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-//        auto res = this->core.read(paddr, 2, data);
-//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-//        if ((instr & 0x3) == 0x3) { // this is a 32bit instruction
-//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
-//        }
-//    } else {
     auto res = this->core.read(paddr, 4, data);
-    if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+    if (res != iss::Ok) 
-//    }
+        return std::make_tuple(ILLEGAL_FETCH, nullptr);
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001)
-    // curr pc on stack
+        return std::make_tuple(JUMP_TO_SELF, nullptr);
     ++inst_cnt;
     uint32_t inst_index = instr_decoder.decode_instr(instr);
     compile_func f = nullptr;

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -38,7 +38,9 @@
 #include <util/logging.h>
 #include <sstream>
 #include <iss/instruction_decoder.h>
-
+<%def fcsr = registers.find {it.name=='FCSR'}
+if(fcsr != null) {%>
+#include <vm/fp_functions.h><%}%>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
 #endif
@@ -85,7 +87,12 @@ protected:
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
 
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+<%
+if(fcsr != null) {%>
+    inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}   
 
+    void add_prologue(tu_builder& tu) override;
+<%}%>
     void setup_module(std::string m) override {
         super::setup_module(m);
     }
@@ -98,8 +105,6 @@ protected:
 
     void gen_leave_trap(tu_builder& tu, unsigned lvl);
 
-    void gen_wait(tu_builder& tu, unsigned type);
-
     inline void gen_set_tval(tu_builder& tu, uint64_t new_tval);
 
     inline void gen_set_tval(tu_builder& tu, value new_tval);
@@ -133,6 +138,9 @@ protected:
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     }
 
+<%functions.each{ it.eachLine { %>
+    ${it}<%}%>
+<%}%>
 private:
     /****************************************************************************
      * start opcode definitions
@@ -163,6 +171,7 @@ private:
         <%}%>if(this->disass_enabled){
             /* generate console output when executing the command */<%instr.disass.eachLine{%>
             ${it}<%}%>
+            tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
         pc=pc+ ${instr.length/8};
@@ -187,11 +196,11 @@ private:
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, std::string("illegal_instruction"));
         }
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        gen_raise_trap(tu, 0, 2);     // illegal instruction trap
+        gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         this->gen_set_tval(tu, instr);
         vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
         vm_impl::gen_trap_check(tu);
-        return BRANCH;
+        return ILLEGAL_INSTR;
     }
 };
 
@@ -224,19 +233,11 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
     phys_addr_t paddr(pc);
     if(this->core.has_mmu())
         paddr = this->core.virt2phys(pc);
-    //TODO: re-add page handling
-//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-//        auto res = this->core.read(paddr, 2, data);
-//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-//        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
-//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
-//        }
-//    } else {
     auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
-    if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+    if (res != iss::Ok)
-//    }
+        return ILLEGAL_FETCH;
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001) 
-    // curr pc on stack
+        return JUMP_TO_SELF;
     ++inst_cnt;
     uint32_t inst_index = instr_decoder.decode_instr(instr);
     compile_func f = nullptr;
@@ -258,9 +259,6 @@ template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsi
     tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP), 32));
 }
 
-template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
-}
-
 template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, uint64_t new_tval) {
     tu(fmt::format("tval = {};", new_tval));
 }
@@ -275,6 +273,39 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP),32));
     tu("return *next_pc;");
 }
+<%
+if(fcsr != null) {%>
+template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
+    std::ostringstream os;
+    os << "uint32_t (*fget_flags)()=" << (uintptr_t)&fget_flags << ";\\n";
+    os << "uint32_t (*fadd_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fadd_s << ";\\n";
+    os << "uint32_t (*fsub_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fsub_s << ";\\n";
+    os << "uint32_t (*fmul_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fmul_s << ";\\n";
+    os << "uint32_t (*fdiv_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_s << ";\\n";
+    os << "uint32_t (*fsqrt_s)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_s << ";\\n";
+    os << "uint32_t (*fcmp_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fcmp_s << ";\\n";
+    os << "uint32_t (*fcvt_s)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_s << ";\\n";
+    os << "uint32_t (*fmadd_s)(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_s << ";\\n";
+    os << "uint32_t (*fsel_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fsel_s << ";\\n";
+    os << "uint32_t (*fclass_s)( uint32_t v1 )=" << (uintptr_t)&fclass_s << ";\\n";
+    os << "uint32_t (*fconv_d2f)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fconv_d2f << ";\\n";
+    os << "uint64_t (*fconv_f2d)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fconv_f2d << ";\\n";
+    os << "uint64_t (*fadd_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fadd_d << ";\\n";
+    os << "uint64_t (*fsub_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fsub_d << ";\\n";
+    os << "uint64_t (*fmul_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fmul_d << ";\\n";
+    os << "uint64_t (*fdiv_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_d << ";\\n";
+    os << "uint64_t (*fsqrt_d)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_d << ";\\n";
+    os << "uint64_t (*fcmp_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fcmp_d << ";\\n";
+    os << "uint64_t (*fcvt_d)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_d << ";\\n";
+    os << "uint64_t (*fmadd_d)(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_d << ";\\n";
+    os << "uint64_t (*fsel_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fsel_d << ";\\n";
+    os << "uint64_t (*fclass_d)(uint64_t v1  )=" << (uintptr_t)&fclass_d << ";\\n";
+    os << "uint64_t (*fcvt_32_64)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_32_64 << ";\\n";
+    os << "uint32_t (*fcvt_64_32)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_64_32 << ";\\n";
+    os << "uint32_t (*unbox_s)(uint64_t v)=" << (uintptr_t)&unbox_s << ";\\n";
+    tu.add_prologue(os.str());
+}
+<%}%>
 
 } // namespace ${coreDef.name.toLowerCase()}
 

src/iss/arch/riscv_hart_m_p.h

@@ -613,7 +613,7 @@ std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT, LOGCAT>::load_file(std::str
                         CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
                 }
             }
-            for(const auto sec : reader.sections) {
+            for(const auto& sec : reader.sections) {
                 if(sec->get_name() == ".tohost") {
                     tohost = sec->get_address();
                     fromhost = tohost + 0x40;
@@ -689,8 +689,10 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
                 }
                 return res;
             } catch(trap_access& ta) {
-                this->reg.trap_state = (1UL << 31) | ta.id;
+                if( (access & access_type::DEBUG) == 0) {
-                fault_data = ta.addr;
+                    this->reg.trap_state = (1UL << 31) | ta.id;
+                    fault_data = ta.addr;
+                }
                 return iss::Err;
             }
         } break;
@@ -717,8 +719,10 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
         }
         return iss::Ok;
     } catch(trap_access& ta) {
-        this->reg.trap_state = (1UL << 31) | ta.id;
+        if((access & access_type::DEBUG) == 0) {
-        fault_data = ta.addr;
+            this->reg.trap_state = (1UL << 31) | ta.id;
+            fault_data = ta.addr;
+        }
         return iss::Err;
     }
 }
@@ -848,8 +852,10 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
         }
         return iss::Ok;
     } catch(trap_access& ta) {
-        this->reg.trap_state = (1UL << 31) | ta.id;
+        if((access & access_type::DEBUG) == 0) {
-        fault_data = ta.addr;
+            this->reg.trap_state = (1UL << 31) | ta.id;
+            fault_data = ta.addr;
+        }
         return iss::Err;
     }
 }

src/iss/debugger/riscv_target_adapter.h

@@ -30,8 +30,8 @@
  *
  *******************************************************************************/
 
-#ifndef _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
+#ifndef _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_
-#define _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
+#define _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_
 
 #include "iss/arch_if.h"
 #include <iss/arch/traits.h>
@@ -39,6 +39,8 @@
 #include <iss/iss.h>
 
 #include <array>
+#include <iostream>
+#include <fstream>
 #include <memory>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -48,6 +50,10 @@
 
 namespace iss {
 namespace debugger {
+
+char const* const get_csr_name(unsigned);
+constexpr auto csr_offset = 100U;
+
 using namespace iss::arch;
 using namespace iss::debugger;
 
@@ -103,7 +109,7 @@ public:
     status process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) override;
 
     status thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, size_t& num,
-                             bool& done) override;
+            bool& done) override;
 
     status current_thread_query(rp_thread_ref& thread) override;
 
@@ -129,11 +135,21 @@ public:
 
 protected:
     static inline constexpr addr_t map_addr(const addr_t& i) { return i; }
-
+    std::string csr_xml;
     iss::arch_if* core;
     rp_thread_ref thread_idx;
 };
 
+template <typename ARCH>
+typename std::enable_if<iss::arch::traits<ARCH>::FLEN!=0, unsigned>::type get_f0_offset() {
+    return iss::arch::traits<ARCH>::F0;
+}
+
+template <typename ARCH>
+typename std::enable_if<iss::arch::traits<ARCH>::FLEN==0, unsigned>::type get_f0_offset() {
+    return 0;
+}
+
 template <typename ARCH> status riscv_target_adapter<ARCH>::set_gen_thread(rp_thread_ref& thread) {
     thread_idx = thread;
     return Ok;
@@ -175,34 +191,37 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
     CPPLOG(TRACE) << "reading target registers";
-    // return idx<0?:;
     data.clear();
     avail.clear();
     const uint8_t* reg_base = core->get_regs_base_ptr();
     auto start_reg = arch::traits<ARCH>::X0;
-    for(size_t reg_no = start_reg; reg_no < start_reg + 33 /*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
+    for(size_t i = 0; i < 33; ++i) {
-        auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
+        if(i < arch::traits<ARCH>::RFS || i == arch::traits<ARCH>::PC) {
-        unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
+            auto reg_no = i<32? start_reg + i: arch::traits<ARCH>::PC;
-        for(size_t j = 0; j < reg_width; ++j) {
+            unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
-            data.push_back(*(reg_base + offset + j));
+            for(size_t j = 0; j < arch::traits<ARCH>::XLEN/8; ++j) {
-            avail.push_back(0xff);
+                data.push_back(*(reg_base + offset + j));
+                avail.push_back(0xff);
+            }
+        } else {
+            for(size_t j = 0; j < arch::traits<ARCH>::XLEN/8; ++j) {
+                data.push_back(0);
+                avail.push_back(0);
+            }
+        }
+    }
+    if(iss::arch::traits<ARCH>::FLEN > 0) {
+        auto fstart_reg = get_f0_offset<ARCH>();
+        for(size_t i = 0; i < 32; ++i) {
+            auto reg_no = fstart_reg + i;
+            auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
+            unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
+            for(size_t j = 0; j < reg_width; ++j) {
+                data.push_back(*(reg_base + offset + j));
+                avail.push_back(0xff);
+            }
         }
     }
-    // work around fill with F type registers
-    //    if (arch::traits<ARCH>::NUM_REGS < 65) {
-    //        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
-    //        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
-    //            for (size_t j = 0; j < reg_width; ++j) {
-    //                data.push_back(0x0);
-    //                avail.push_back(0x00);
-    //            }
-    //            // if(arch::traits<ARCH>::XLEN < 64)
-    //            //     for(unsigned j=0; j<4; ++j){
-    //            //         data.push_back(0x0);
-    //            //         avail.push_back(0x00);
-    //            //     }
-    //        }
-    //    }
     return Ok;
 }
 
@@ -210,25 +229,25 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
     auto start_reg = arch::traits<ARCH>::X0;
     auto* reg_base = core->get_regs_base_ptr();
     auto iter = data.data();
-    bool e_ext = arch::traits<ARCH>::PC < 32;
+    auto iter_end = data.data()+data.size();
-    for(size_t reg_no = 0; reg_no < start_reg + 33 /*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
+    for(size_t i = 0; i < 33 && iter < iter_end; ++i) {
-        if(e_ext && reg_no > 15) {
+        auto reg_width = arch::traits<ARCH>::XLEN / 8;
-            if(reg_no == 32) {
+        if(i < arch::traits<ARCH>::RFS) {
-                auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
+            auto offset = traits<ARCH>::reg_byte_offsets[start_reg + i];
-                auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
+            std::copy(iter, iter + reg_width, reg_base+offset);
-                std::copy(iter, iter + reg_width, reg_base);
+        } else if(i == 32) {
-            } else {
+            auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
-                const uint64_t zero_val = 0;
+            std::copy(iter, iter + reg_width, reg_base+offset);
-                auto reg_width = arch::traits<ARCH>::reg_bit_widths[15] / 8;
+        }
-                auto iter = (uint8_t*)&zero_val;
+        iter += reg_width;
-                std::copy(iter, iter + reg_width, reg_base);
+    }
-            }
+    if(iss::arch::traits<ARCH>::FLEN > 0) {
-        } else {
+        auto fstart_reg = get_f0_offset<ARCH>();
-            auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
+        auto reg_width = arch::traits<ARCH>::FLEN / 8;
-            auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
+        for(size_t i = 0; i < 32 && iter < iter_end; ++i) {
-            std::copy(iter, iter + reg_width, reg_base);
+            unsigned offset = traits<ARCH>::reg_byte_offsets[fstart_reg + i];
-            iter += 4;
+            std::copy(iter, iter + reg_width, reg_base+offset);
-            reg_base += offset;
+            iter += reg_width;
         }
     }
     return Ok;
@@ -236,7 +255,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
 
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
-    if(reg_no < 65) {
+    if(reg_no <csr_offset) {
         // auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
         // arch::traits<ARCH>::reg_e>(reg_no))/8;
         auto* reg_base = core->get_regs_base_ptr();
@@ -247,23 +266,24 @@ status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std
         std::copy(reg_base + offset, reg_base + offset + reg_width, data.begin());
         std::fill(avail.begin(), avail.end(), 0xff);
     } else {
-        typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, reg_no - 65);
+        typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, reg_no - csr_offset);
         data.resize(sizeof(typename traits<ARCH>::reg_t));
         avail.resize(sizeof(typename traits<ARCH>::reg_t));
         std::fill(avail.begin(), avail.end(), 0xff);
         core->read(a, data.size(), data.data());
+        std::fill(avail.begin(), avail.end(), 0xff);
     }
     return data.size() > 0 ? Ok : Err;
 }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t>& data) {
-    if(reg_no < 65) {
+    if(reg_no < csr_offset) {
         auto* reg_base = core->get_regs_base_ptr();
         auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
         auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
         std::copy(data.begin(), data.begin() + reg_width, reg_base + offset);
     } else {
-        typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_WRITE, traits<ARCH>::CSR, reg_no - 65);
+        typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_WRITE, traits<ARCH>::CSR, reg_no - csr_offset);
         core->write(a, data.size(), data.data());
     }
     return Ok;
@@ -276,7 +296,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::read_mem(uint64_t ad
 }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t>& data) {
-    auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
+    auto a = map_addr({iss::access_type::DEBUG_WRITE, iss::address_type::VIRTUAL, 0, addr});
     auto f = [&]() -> status { return core->write(a, data.size(), data.data()); };
     return srv->execute_syncronized(f);
 }
@@ -329,7 +349,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type
         auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
         target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
         CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
-                      << std::dec;
+                << std::dec;
         CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Ok;
     }
@@ -359,7 +379,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_t
 
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
-                                                    std::function<void(unsigned)> stop_callback) {
+        std::function<void(unsigned)> stop_callback) {
     auto* reg_base = core->get_regs_base_ptr();
     auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
     auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
@@ -369,93 +389,52 @@ status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t
 }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string& out_buf) {
-    const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
+    if(!csr_xml.size()) {
-                          "<target><architecture>riscv:rv32</architecture>"
+        std::ostringstream oss;
-                          //"  <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
+        oss << "<?xml version=\"1.0\"?><!DOCTYPE feature SYSTEM \"gdb-target.dtd\"><target version=\"1.0\">\n";
-                          //"    <reg name=\"x0\"  bitsize=\"32\" group=\"general\"/>\n"
+        if(iss::arch::traits<ARCH>::XLEN == 32)
-                          //"    <reg name=\"x1\"  bitsize=\"32\" group=\"general\"/>\n"
+            oss << "<architecture>riscv:rv32</architecture>\n";
-                          //"    <reg name=\"x2\"  bitsize=\"32\" group=\"general\"/>\n"
+        else if(iss::arch::traits<ARCH>::XLEN == 64)
-                          //"    <reg name=\"x3\"  bitsize=\"32\" group=\"general\"/>\n"
+            oss << "  <architectureriscv:rv64</architecture>\n";
-                          //"    <reg name=\"x4\"  bitsize=\"32\" group=\"general\"/>\n"
+        oss << "  <feature name=\"org.gnu.gdb.riscv.cpu\">\n";
-                          //"    <reg name=\"x5\"  bitsize=\"32\" group=\"general\"/>\n"
+        auto reg_base_num = iss::arch::traits<ARCH>::X0;
-                          //"    <reg name=\"x6\"  bitsize=\"32\" group=\"general\"/>\n"
+        for(auto i = 0U; i<iss::arch::traits<ARCH>::RFS; ++i) {
-                          //"    <reg name=\"x7\"  bitsize=\"32\" group=\"general\"/>\n"
+            oss << "    <reg name=\"x" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i] << "\" type=\"int\" regnum=\"" << i << "\"/>\n";
-                          //"    <reg name=\"x8\"  bitsize=\"32\" group=\"general\"/>\n"
+        }
-                          //"    <reg name=\"x9\"  bitsize=\"32\" group=\"general\"/>\n"
+        oss << "    <reg name=\"pc\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[iss::arch::traits<ARCH>::PC] << "\" type=\"code_ptr\" regnum=\"" << 32U << "\"/>\n";
-                          //"    <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
+        oss << "  </feature>\n";
-                          //"    <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
+        if(iss::arch::traits<ARCH>::FLEN > 0) {
-                          //"    <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
+            oss << "  <feature name=\"org.gnu.gdb.riscv.fpu\">\n";
-                          //"    <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
+            auto reg_base_num =  get_f0_offset<ARCH>();
-                          //"    <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
+            auto type = iss::arch::traits<ARCH>::FLEN==32?"ieee_single":"riscv_double";
-                          //"    <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
+            for(auto i = 0U; i<32; ++i) {
-                          //"    <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
+                oss << "    <reg name=\"f" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i] << "\" type=\""<<type<<"\" regnum=\"" << i+33 << "\"/>\n";
-                          //"    <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
+            }
-                          //"    <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
+            oss << "    <reg name=\"fcsr\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"103\" type int/>\n";
-                          //"    <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
+            oss << "    <reg name=\"fflags\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"101\" type int/>\n";
-                          //"    <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
+            oss << "    <reg name=\"frm\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"102\" type int/>\n";
-                          //"    <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
+            oss << "  </feature>\n";
-                          //"    <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
+        }
-                          //"    <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
+        oss << "  <feature name=\"org.gnu.gdb.riscv.csr\">\n";
-                          //"    <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
+        std::vector<uint8_t> data;
-                          //"    <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
+        std::vector<uint8_t> avail;
-                          //"    <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
+        data.resize(sizeof(typename traits<ARCH>::reg_t));
-                          //"    <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
+        avail.resize(sizeof(typename traits<ARCH>::reg_t));
-                          //"    <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
+        for(auto i = 0U; i<4096; ++i) {
-                          //"    <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
+            typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, i);
-                          //"    <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
+            std::fill(avail.begin(), avail.end(), 0xff);
-                          //"    <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
+            auto res = core->read(a, data.size(), data.data());
-                          //"  </feature>\n"
+            if(res == iss::Ok) {
-                          "</target>"};
+                oss << "    <reg name=\"" << get_csr_name(i) << "\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\"  type=\"int\" regnum=\"" << (i + csr_offset) << "\"/>\n";
-    out_buf = res;
+            }
+        }
+        oss << "  </feature>\n";
+        oss << "</target>\n";
+    }
+    out_buf = csr_xml;
     return Ok;
 }
-
-/*
- *
-<?xml version="1.0"?>
-<!DOCTYPE target SYSTEM "gdb-target.dtd">
-<target>
-  <architecture>riscv:rv32</architecture>
-
-  <feature name="org.gnu.gdb.riscv.rv32i">
-    <reg name="x0"  bitsize="32" group="general"/>
-    <reg name="x1"  bitsize="32" group="general"/>
-    <reg name="x2"  bitsize="32" group="general"/>
-    <reg name="x3"  bitsize="32" group="general"/>
-    <reg name="x4"  bitsize="32" group="general"/>
-    <reg name="x5"  bitsize="32" group="general"/>
-    <reg name="x6"  bitsize="32" group="general"/>
-    <reg name="x7"  bitsize="32" group="general"/>
-    <reg name="x8"  bitsize="32" group="general"/>
-    <reg name="x9"  bitsize="32" group="general"/>
-    <reg name="x10" bitsize="32" group="general"/>
-    <reg name="x11" bitsize="32" group="general"/>
-    <reg name="x12" bitsize="32" group="general"/>
-    <reg name="x13" bitsize="32" group="general"/>
-    <reg name="x14" bitsize="32" group="general"/>
-    <reg name="x15" bitsize="32" group="general"/>
-    <reg name="x16" bitsize="32" group="general"/>
-    <reg name="x17" bitsize="32" group="general"/>
-    <reg name="x18" bitsize="32" group="general"/>
-    <reg name="x19" bitsize="32" group="general"/>
-    <reg name="x20" bitsize="32" group="general"/>
-    <reg name="x21" bitsize="32" group="general"/>
-    <reg name="x22" bitsize="32" group="general"/>
-    <reg name="x23" bitsize="32" group="general"/>
-    <reg name="x24" bitsize="32" group="general"/>
-    <reg name="x25" bitsize="32" group="general"/>
-    <reg name="x26" bitsize="32" group="general"/>
-    <reg name="x27" bitsize="32" group="general"/>
-    <reg name="x28" bitsize="32" group="general"/>
-    <reg name="x29" bitsize="32" group="general"/>
-    <reg name="x30" bitsize="32" group="general"/>
-    <reg name="x31" bitsize="32" group="general"/>
-  </feature>
-
-</target>
-
- */
 } // namespace debugger
 } // namespace iss
 
-#endif /* _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */
+#endif /* _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */

src/main.cpp

@@ -69,7 +69,8 @@ int main(int argc, char* argv[]) {
         ("logfile,l", po::value<std::string>(), "Sets default log file.")
         ("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
         ("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
-        ("instructions,i", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of instructions to simulate")
+        ("ilimit,i", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of instructions to simulate")
+        ("flimit", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of fetches to simulate")
         ("reset,r", po::value<std::string>(), "reset address")
         ("dump-ir", "dump the intermediate representation")
         ("elf,f", po::value<std::vector<std::string>>(), "ELF file(s) to load")
@@ -215,8 +216,15 @@ int main(int argc, char* argv[]) {
             start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), nullptr, 16) : std::stoull(str, nullptr, 10);
         }
         vm->reset(start_address);
-        auto cycles = clim["instructions"].as<uint64_t>();
+        auto limit = clim["ilimit"].as<uint64_t>();
-        res = vm->start(cycles, dump);
+        auto cond = iss::finish_cond_e::JUMP_TO_SELF;
+        if(clim.count("flimit")) {
+            cond = cond | iss::finish_cond_e::FCOUNT_LIMIT;
+            limit = clim["flimit"].as<uint64_t>();
+        } else {
+            cond = cond | iss::finish_cond_e::ICOUNT_LIMIT;
+        }
+        res = vm->start(limit, dump, cond);
 
         auto instr_if = vm->get_arch()->get_instrumentation_if();
         // this assumes a single input file

src/sysc/core_complex.cpp

@@ -125,7 +125,7 @@ using vm_ptr = std::unique_ptr<iss::vm_if>;
 
 class core_wrapper {
 public:
-    core_wrapper(core_complex* owner)
+    core_wrapper(core_complex_if* owner)
     : owner(owner) {}
 
     void reset(uint64_t addr) { vm->reset(addr); }
@@ -181,7 +181,7 @@ public:
                                              "SystemC sub-commands: break <time>, print_time"});
     }
 
-    core_complex* const owner;
+    core_complex_if* const owner;
     vm_ptr vm{nullptr};
     sc_cpu_ptr cpu{nullptr};
     iss::debugger::target_adapter_if* tgt_adapter{nullptr};
@@ -197,9 +197,9 @@ struct core_trace {
     scv_tr_handle tr_handle;
 };
 
-SC_HAS_PROCESS(core_complex); // NOLINT
 #ifndef CWR_SYSTEMC
-core_complex::core_complex(sc_module_name const& name)
+template <unsigned int BUSWIDTH>
+core_complex<BUSWIDTH>::core_complex(sc_module_name const& name)
 : sc_module(name)
 , fetch_lut(tlm_dmi_ext())
 , read_lut(tlm_dmi_ext())
@@ -208,7 +208,8 @@ core_complex::core_complex(sc_module_name const& name)
 }
 #endif
 
-void core_complex::init() {
+template <unsigned int BUSWIDTH>
+void core_complex<BUSWIDTH>::init() {
     trc = new core_trace();
     ibus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
         auto lut_entry = fetch_lut.getEntry(start);
@@ -227,6 +228,7 @@ void core_complex::init() {
         }
     });
 
+    SC_HAS_PROCESS(core_complex<BUSWIDTH>); // NOLINT
     SC_THREAD(run);
     SC_METHOD(rst_cb);
     sensitive << rst_i;
@@ -252,16 +254,19 @@ void core_complex::init() {
 #endif
 }
 
-core_complex::~core_complex() {
+template <unsigned int BUSWIDTH>
+core_complex<BUSWIDTH>::~core_complex() {
     delete cpu;
     delete trc;
     for(auto* p : plugin_list)
         delete p;
 }
 
-void core_complex::trace(sc_trace_file* trf) const {}
+template <unsigned int BUSWIDTH>
+void core_complex<BUSWIDTH>::trace(sc_trace_file* trf) const {}
 
-void core_complex::before_end_of_elaboration() {
+template <unsigned int BUSWIDTH>
+void core_complex<BUSWIDTH>::before_end_of_elaboration() {
     SCCDEBUG(SCMOD) << "instantiating iss::arch::tgf with " << GET_PROP_VALUE(backend) << " backend";
     // cpu = scc::make_unique<core_wrapper>(this);
     cpu = new core_wrapper(this);
@@ -302,7 +307,8 @@ void core_complex::before_end_of_elaboration() {
     }
 }
 
-void core_complex::start_of_simulation() {
+template <unsigned int BUSWIDTH>
+void core_complex<BUSWIDTH>::start_of_simulation() {
     // quantum_keeper.reset();
     if(GET_PROP_VALUE(elf_file).size() > 0) {
         istringstream is(GET_PROP_VALUE(elf_file));
@@ -325,7 +331,8 @@ void core_complex::start_of_simulation() {
     }
 }
 
-bool core_complex::disass_output(uint64_t pc, const std::string instr_str) {
+template <unsigned int BUSWIDTH>
+bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_str) {
     if(trc->m_db == nullptr)
         return false;
     if(trc->tr_handle.is_active())
@@ -339,7 +346,8 @@ bool core_complex::disass_output(uint64_t pc, const std::string instr_str) {
     return true;
 }
 
-void core_complex::forward() {
+template <unsigned int BUSWIDTH>
+void core_complex<BUSWIDTH>::forward() {
 #ifndef CWR_SYSTEMC
     set_clock_period(clk_i.read());
 #else
@@ -348,24 +356,30 @@ void core_complex::forward() {
 #endif
 }
 
-void core_complex::set_clock_period(sc_core::sc_time period) {
+template <unsigned int BUSWIDTH>
+void core_complex<BUSWIDTH>::set_clock_period(sc_core::sc_time period) {
     curr_clk = period;
     if(period == SC_ZERO_TIME)
         cpu->set_interrupt_execution(true);
 }
 
-void core_complex::rst_cb() {
+template <unsigned int BUSWIDTH>
+void core_complex<BUSWIDTH>::rst_cb() {
     if(rst_i.read())
         cpu->set_interrupt_execution(true);
 }
 
-void core_complex::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
+template <unsigned int BUSWIDTH>
+void core_complex<BUSWIDTH>::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
 
-void core_complex::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
+template <unsigned int BUSWIDTH>
+void core_complex<BUSWIDTH>::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
 
-void core_complex::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
+template <unsigned int BUSWIDTH>
+void core_complex<BUSWIDTH>::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
 
-void core_complex::local_irq_cb() {
+template <unsigned int BUSWIDTH>
+void core_complex<BUSWIDTH>::local_irq_cb() {
     for(auto i = 0U; i < local_irq_i.size(); ++i) {
         if(local_irq_i[i].event()) {
             cpu->local_irq(16 + i, local_irq_i[i].read());
@@ -373,7 +387,8 @@ void core_complex::local_irq_cb() {
     }
 }
 
-void core_complex::run() {
+template <unsigned int BUSWIDTH>
+void core_complex<BUSWIDTH>::run() {
     wait(SC_ZERO_TIME); // separate from elaboration phase
     do {
         wait(SC_ZERO_TIME);
@@ -391,7 +406,8 @@ void core_complex::run() {
     sc_stop();
 }
 
-bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
+template <unsigned int BUSWIDTH>
+bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
     auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
     auto lut_entry = dmi_lut.getEntry(addr);
     if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
@@ -449,7 +465,8 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t* const data,
     }
 }
 
-bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
+template <unsigned int BUSWIDTH>
+bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
     auto lut_entry = write_lut.getEntry(addr);
     if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
         auto offset = addr - lut_entry.get_start_address();
@@ -497,7 +514,8 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t* cons
     }
 }
 
-bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
+template <unsigned int BUSWIDTH>
+bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
     tlm::tlm_generic_payload gp;
     gp.set_command(tlm::TLM_READ_COMMAND);
     gp.set_address(addr);
@@ -507,7 +525,8 @@ bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const d
     return dbus->transport_dbg(gp) == length;
 }
 
-bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
+template <unsigned int BUSWIDTH>
+bool core_complex<BUSWIDTH>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
     write_buf.resize(length);
     std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
     tlm::tlm_generic_payload gp;
@@ -518,5 +537,10 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t*
     gp.set_streaming_width(length);
     return dbus->transport_dbg(gp) == length;
 }
+
+template class core_complex<scc::LT>;
+template class core_complex<32>;
+template class core_complex<64>;
+
 } /* namespace tgfs */
 } /* namespace sysc */

src/sysc/core_complex.h

@@ -36,14 +36,13 @@
 #include <scc/tick2time.h>
 #include <scc/traceable.h>
 #include <scc/utilities.h>
+#include <scc/signal_opt_ports.h>
 #include <tlm/scc/initiator_mixin.h>
 #include <tlm/scc/scv/tlm_rec_initiator_socket.h>
 #ifdef CWR_SYSTEMC
 #include <scmlinc/scml_property.h>
-#define SOCKET_WIDTH 32
 #else
 #include <cci_configuration>
-#define SOCKET_WIDTH scc::LT
 #endif
 #include <memory>
 #include <tlm>
@@ -68,12 +67,36 @@ public:
 namespace tgfs {
 class core_wrapper;
 struct core_trace;
+struct core_complex_if {
 
-class core_complex : public sc_core::sc_module, public scc::traceable {
+    virtual ~core_complex_if() = default;
+
+    virtual bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) =0;
+
+    virtual bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data)  =0;
+
+    virtual bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data)  =0;
+
+    virtual bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data)  =0;
+
+    virtual bool disass_output(uint64_t pc, const std::string instr)  =0;
+
+    virtual unsigned get_last_bus_cycles() =0;
+
+    //! Allow quantum keeper handling
+    virtual void sync(uint64_t) =0;
+
+    virtual char const* hier_name() = 0;
+
+    scc::sc_in_opt<uint64_t> mtime_i{"mtime_i"};
+};
+
+template <unsigned int BUSWIDTH = scc::LT>
+class core_complex : public sc_core::sc_module, public scc::traceable, public core_complex_if {
 public:
-    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> ibus{"ibus"};
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>> ibus{"ibus"};
 
-    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> dbus{"dbus"};
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>> dbus{"dbus"};
 
     sc_core::sc_in<bool> rst_i{"rst_i"};
 
@@ -88,8 +111,6 @@ public:
 #ifndef CWR_SYSTEMC
     sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
 
-    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o{"mtime_o"};
-
     cci::cci_param<std::string> elf_file{"elf_file", ""};
 
     cci::cci_param<bool> enable_disass{"enable_disass", false};
@@ -115,8 +136,6 @@ public:
 #else
     sc_core::sc_in<bool> clk_i{"clk_i"};
 
-    sc_core::sc_in<uint64_t> mtime_i{"mtime_i"};
-
     scml_property<std::string> elf_file{"elf_file", ""};
 
     scml_property<bool> enable_disass{"enable_disass", false};
@@ -159,13 +178,13 @@ public:
 
     ~core_complex();
 
-    inline unsigned get_last_bus_cycles() {
+    unsigned get_last_bus_cycles() override {
         auto mem_incr = std::max(ibus_inc, dbus_inc);
         ibus_inc = dbus_inc = 0;
         return mem_incr > 1 ? mem_incr : 1;
     }
 
-    inline void sync(uint64_t cycle) {
+    void sync(uint64_t cycle) override {
         auto core_inc = curr_clk * (cycle - last_sync_cycle);
         quantum_keeper.inc(core_inc);
         if(quantum_keeper.need_sync()) {
@@ -175,20 +194,24 @@ public:
         last_sync_cycle = cycle;
     }
 
-    bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch);
+    bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) override;
 
-    bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data);
+    bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data) override;
 
-    bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data);
+    bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) override;
 
-    bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data);
+    bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) override;
 
     void trace(sc_core::sc_trace_file* trf) const override;
 
-    bool disass_output(uint64_t pc, const std::string instr);
+    bool disass_output(uint64_t pc, const std::string instr) override;
 
     void set_clock_period(sc_core::sc_time period);
 
+    char const* hier_name() override {
+        return name();
+    }
+
 protected:
     void before_end_of_elaboration() override;
     void start_of_simulation() override;

src/sysc/register_tgc_c.cpp

@@ -46,12 +46,12 @@ using namespace sysc;
 volatile std::array<bool, 2> tgc_init = {
     iss_factory::instance().register_creator("tgc5c|m_p|interp",
                                              [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
                                                  auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
                                                  return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
                                              }),
     iss_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
         auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
         return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
     })};
@@ -79,12 +79,12 @@ using namespace sysc;
 volatile std::array<bool, 2> tgc_init = {
     iss_factory::instance().register_creator("tgc5c|m_p|tcc",
                                              [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
                                                  auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
                                                  return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
                                              }),
     iss_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
         auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
         return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
     })};
@@ -96,12 +96,12 @@ using namespace sysc;
 volatile std::array<bool, 2> tgc_init = {
     iss_factory::instance().register_creator("tgc5c|m_p|asmjit",
                                              [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
                                                  auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
                                                  return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
                                              }),
     iss_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
         auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
         return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
     })};

src/sysc/sc_core_adapter.h

@@ -21,7 +21,7 @@ public:
     using reg_t = typename iss::arch::traits<typename PLAT::core>::reg_t;
     using phys_addr_t = typename iss::arch::traits<typename PLAT::core>::phys_addr_t;
     using heart_state_t = typename PLAT::hart_state_type;
-    sc_core_adapter(sysc::tgfs::core_complex* owner)
+    sc_core_adapter(sysc::tgfs::core_complex_if* owner)
     : owner(owner) {}
 
     iss::arch_if* get_arch_if() override { return this; }
@@ -54,7 +54,7 @@ public:
             std::stringstream s;
             s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') << std::setw(sizeof(reg_t) * 2)
               << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount + this->cycle_offset << "]";
-            SCCDEBUG(owner->name()) << "disass: "
+            SCCDEBUG(owner->hier_name()) << "disass: "
                                     << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
                                     << std::setfill(' ') << std::left << instr << s.str();
         }
@@ -79,10 +79,10 @@ public:
                     switch(hostvar >> 48) {
                     case 0:
                         if(hostvar != 0x1) {
-                            SCCINFO(owner->name())
+                            SCCINFO(owner->hier_name())
                                 << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation";
                         } else {
-                            SCCINFO(owner->name())
+                            SCCINFO(owner->hier_name())
                                 << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation";
                         }
                         this->reg.trap_state = std::numeric_limits<uint32_t>::max();
@@ -112,21 +112,8 @@ public:
     }
 
     iss::status read_csr(unsigned addr, reg_t& val) override {
-#ifndef CWR_SYSTEMC
-        if((addr == iss::arch::time || addr == iss::arch::timeh) && owner->mtime_o.get_interface(0)) {
-            uint64_t time_val;
-            bool ret = owner->mtime_o->nb_peek(time_val);
-            if(addr == iss::arch::time) {
-                val = static_cast<reg_t>(time_val);
-            } else if(addr == iss::arch::timeh) {
-                if(sizeof(reg_t) != 4)
-                    return iss::Err;
-                val = static_cast<reg_t>(time_val >> 32);
-            }
-            return ret ? iss::Ok : iss::Err;
-#else
         if((addr == iss::arch::time || addr == iss::arch::timeh)) {
-            uint64_t time_val = owner->mtime_i.read();
+            uint64_t time_val = owner->mtime_i.get_interface()? owner->mtime_i.read():0;
             if(addr == iss::arch::time) {
                 val = static_cast<reg_t>(time_val);
             } else if(addr == iss::arch::timeh) {
@@ -135,14 +122,13 @@ public:
                 val = static_cast<reg_t>(time_val >> 32);
             }
             return iss::Ok;
-#endif
         } else {
             return PLAT::read_csr(addr, val);
         }
     }
 
     void wait_until(uint64_t flags) override {
-        SCCDEBUG(owner->name()) << "Sleeping until interrupt";
+        SCCDEBUG(owner->hier_name()) << "Sleeping until interrupt";
         while(this->reg.pending_trap == 0 && (this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
             sc_core::wait(wfi_evt);
         }
@@ -173,11 +159,11 @@ public:
             this->csr[iss::arch::mip] &= ~mask;
         this->check_interrupt();
         if(value)
-            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
+            SCCTRACE(owner->hier_name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
     }
 
 private:
-    sysc::tgfs::core_complex* const owner;
+    sysc::tgfs::core_complex_if* const owner{nullptr};
     sc_core::sc_event wfi_evt;
     uint64_t hostvar{std::numeric_limits<uint64_t>::max()};
     unsigned to_host_wr_cnt = 0;

src/vm/asmjit/vm_tgc5c.cpp

@@ -88,7 +88,6 @@ protected:
     using super::write_reg_to_mem;
     using super::gen_read_mem;
     using super::gen_write_mem;
-    using super::gen_wait;
     using super::gen_leave;
     using super::gen_sync;
    
@@ -113,6 +112,7 @@ protected:
         auto sign_mask = 1ULL<<(W-1);
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     }
+
 private:
     /****************************************************************************
      * start opcode definitions
@@ -500,6 +500,7 @@ private:
                 (gen_operation(cc, band, (gen_operation(cc, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))
                 ), addr_mask)
                 ), 32, true);
+            {
             auto label_merge = cc.newLabel();
             cmp(cc, gen_operation(cc, urem, new_pc, static_cast<uint32_t>(traits::INSTR_ALIGNMENT))
             ,0);
@@ -521,6 +522,7 @@ private:
                     mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(UNKNOWN_JUMP));
                 }
             cc.bind(label_merge);
+            }
         }
         auto returnValue = BRANCH;
         
@@ -566,6 +568,7 @@ private:
             gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
+            {
             auto label_merge = cc.newLabel();
             cmp(cc, gen_operation(cc, eq, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
             ,0);
@@ -583,6 +586,7 @@ private:
                 }
             }
             cc.bind(label_merge);
+            }
         }
         auto returnValue = BRANCH;
         
@@ -628,6 +632,7 @@ private:
             gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
+            {
             auto label_merge = cc.newLabel();
             cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
             ,0);
@@ -645,6 +650,7 @@ private:
                 }
             }
             cc.bind(label_merge);
+            }
         }
         auto returnValue = BRANCH;
         
@@ -690,6 +696,7 @@ private:
             gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
+            {
             auto label_merge = cc.newLabel();
             cmp(cc, gen_operation(cc, lt, gen_ext(cc, 
                 load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(cc, 
@@ -709,6 +716,7 @@ private:
                 }
             }
             cc.bind(label_merge);
+            }
         }
         auto returnValue = BRANCH;
         
@@ -754,6 +762,7 @@ private:
             gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
+            {
             auto label_merge = cc.newLabel();
             cmp(cc, gen_operation(cc, gte, gen_ext(cc, 
                 load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(cc, 
@@ -773,6 +782,7 @@ private:
                 }
             }
             cc.bind(label_merge);
+            }
         }
         auto returnValue = BRANCH;
         
@@ -818,6 +828,7 @@ private:
             gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
+            {
             auto label_merge = cc.newLabel();
             cmp(cc, gen_operation(cc, ltu, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
             ,0);
@@ -835,6 +846,7 @@ private:
                 }
             }
             cc.bind(label_merge);
+            }
         }
         auto returnValue = BRANCH;
         
@@ -880,6 +892,7 @@ private:
             gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
+            {
             auto label_merge = cc.newLabel();
             cmp(cc, gen_operation(cc, gteu, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
             ,0);
@@ -897,6 +910,7 @@ private:
                 }
             }
             cc.bind(label_merge);
+            }
         }
         auto returnValue = BRANCH;
         
@@ -2364,7 +2378,7 @@ private:
         if(this->disass_enabled){
             /* generate disass */
             
-            //This disass is not yet implemented
+            //No disass specified, using instruction name
             std::string mnemonic = "ecall";
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -2401,7 +2415,7 @@ private:
         if(this->disass_enabled){
             /* generate disass */
             
-            //This disass is not yet implemented
+            //No disass specified, using instruction name
             std::string mnemonic = "ebreak";
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -2438,7 +2452,7 @@ private:
         if(this->disass_enabled){
             /* generate disass */
             
-            //This disass is not yet implemented
+            //No disass specified, using instruction name
             std::string mnemonic = "mret";
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -2475,7 +2489,7 @@ private:
         if(this->disass_enabled){
             /* generate disass */
             
-            //This disass is not yet implemented
+            //No disass specified, using instruction name
             std::string mnemonic = "wfi";
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -2497,7 +2511,10 @@ private:
         gen_instr_prologue(jh);
         cc.comment("//behavior:");
         /*generate behavior*/
-        gen_wait(jh, 1);
+        InvokeNode* call_wait;
+        jh.cc.comment("//call_wait");
+        jh.cc.invoke(&call_wait, &wait, FuncSignature::build<void, int32_t>());
+        setArg(call_wait, 0, 1);
         auto returnValue = CONT;
         
         gen_sync(jh, POST_SYNC, 41);
@@ -3116,6 +3133,7 @@ private:
             auto divisor = gen_ext(cc, 
                 load_reg_from_mem(jh, traits::X0 + rs2), 32, true);
             if(rd!=0){
+                {
                 auto label_merge = cc.newLabel();
                 cmp(cc, gen_operation(cc, ne, divisor, 0)
                 ,0);
@@ -3123,6 +3141,7 @@ private:
                 cc.je(label_else);
                 {
                     auto MMIN = ((uint32_t)1)<<(static_cast<uint32_t>(traits::XLEN)-1);
+                    {
                     auto label_merge = cc.newLabel();
                     cmp(cc, gen_operation(cc, land, gen_operation(cc, eq, load_reg_from_mem(jh, traits::X0 + rs1), MMIN)
                     , gen_operation(cc, eq, divisor, - 1)
@@ -3143,6 +3162,7 @@ private:
                                       ), 32, true));
                         }
                     cc.bind(label_merge);
+                    }
                 }
                 cc.jmp(label_merge);
                 cc.bind(label_else);
@@ -3151,6 +3171,7 @@ private:
                               (uint32_t)- 1);
                     }
                 cc.bind(label_merge);
+                }
             }
         }
         auto returnValue = CONT;
@@ -3196,6 +3217,7 @@ private:
             gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
+            {
             auto label_merge = cc.newLabel();
             cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0)
             ,0);
@@ -3217,6 +3239,7 @@ private:
                     }
                 }
             cc.bind(label_merge);
+            }
         }
         auto returnValue = CONT;
         
@@ -3261,6 +3284,7 @@ private:
             gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
+            {
             auto label_merge = cc.newLabel();
             cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0)
             ,0);
@@ -3268,6 +3292,7 @@ private:
             cc.je(label_else);
             {
                 auto MMIN = (uint32_t)1<<(static_cast<uint32_t>(traits::XLEN)-1);
+                {
                 auto label_merge = cc.newLabel();
                 cmp(cc, gen_operation(cc, land, gen_operation(cc, eq, load_reg_from_mem(jh, traits::X0 + rs1), MMIN)
                 , gen_operation(cc, eq, gen_ext(cc, 
@@ -3296,6 +3321,7 @@ private:
                         }
                     }
                 cc.bind(label_merge);
+                }
             }
             cc.jmp(label_merge);
             cc.bind(label_else);
@@ -3306,6 +3332,7 @@ private:
                     }
                 }
             cc.bind(label_merge);
+            }
         }
         auto returnValue = CONT;
         
@@ -3350,6 +3377,7 @@ private:
             gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
+            {
             auto label_merge = cc.newLabel();
             cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0)
             ,0);
@@ -3371,6 +3399,7 @@ private:
                     }
                 }
             cc.bind(label_merge);
+            }
         }
         auto returnValue = CONT;
         
@@ -3388,7 +3417,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"),
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"),
                 fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -3436,7 +3465,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"),
+                "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"),
                 fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -3482,7 +3511,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"),
+                "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"),
                 fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -3525,7 +3554,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"),
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"),
                 fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -3572,8 +3601,8 @@ private:
         if(this->disass_enabled){
             /* generate disass */
             
-            //This disass is not yet implemented
+            //No disass specified, using instruction name
-            std::string mnemonic = "c__nop";
+            std::string mnemonic = "c.nop";
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
             jh.disass_collection.push_back(mnemonic_ptr);
@@ -3609,7 +3638,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"),
+                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.jal"),
                 fmt::arg("imm", imm));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -3653,7 +3682,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"),
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"),
                 fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -3700,7 +3729,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"),
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"),
                 fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -3744,7 +3773,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"),
+                "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c.addi16sp"),
                 fmt::arg("nzimm", nzimm));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -3789,8 +3818,8 @@ private:
         if(this->disass_enabled){
             /* generate disass */
             
-            //This disass is not yet implemented
+            //No disass specified, using instruction name
-            std::string mnemonic = "__reserved_clui";
+            std::string mnemonic = ".reserved_clui";
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
             jh.disass_collection.push_back(mnemonic_ptr);
@@ -3828,7 +3857,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"),
+                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"),
                 fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -3869,7 +3898,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"),
+                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"),
                 fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -3923,7 +3952,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"),
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"),
                 fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -3965,7 +3994,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"),
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"),
                 fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4007,7 +4036,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"),
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"),
                 fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4048,7 +4077,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"),
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"),
                 fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4089,7 +4118,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"),
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"),
                 fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4129,7 +4158,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"),
+                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"),
                 fmt::arg("imm", imm));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4171,7 +4200,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"),
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"),
                 fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4194,6 +4223,7 @@ private:
         cc.comment("//behavior:");
         /*generate behavior*/
         mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
+        {
         auto label_merge = cc.newLabel();
         cmp(cc, gen_operation(cc, eq, load_reg_from_mem(jh, traits::X0 + rs1+8), 0)
         ,0);
@@ -4204,6 +4234,7 @@ private:
             mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(KNOWN_JUMP));
         }
         cc.bind(label_merge);
+        }
         auto returnValue = BRANCH;
         
         gen_sync(jh, POST_SYNC, 75);
@@ -4220,7 +4251,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"),
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"),
                 fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4243,6 +4274,7 @@ private:
         cc.comment("//behavior:");
         /*generate behavior*/
         mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
+        {
         auto label_merge = cc.newLabel();
         cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs1+8), 0)
         ,0);
@@ -4253,6 +4285,7 @@ private:
             mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(KNOWN_JUMP));
         }
         cc.bind(label_merge);
+        }
         auto returnValue = BRANCH;
         
         gen_sync(jh, POST_SYNC, 76);
@@ -4269,7 +4302,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"),
+                "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"),
                 fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4317,7 +4350,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"),
+                "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"),
                 fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4367,7 +4400,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"),
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"),
                 fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4413,7 +4446,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"),
+                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"),
                 fmt::arg("rs1", name(rs1)));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4459,8 +4492,8 @@ private:
         if(this->disass_enabled){
             /* generate disass */
             
-            //This disass is not yet implemented
+            //No disass specified, using instruction name
-            std::string mnemonic = "__reserved_cmv";
+            std::string mnemonic = ".reserved_cmv";
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
             jh.disass_collection.push_back(mnemonic_ptr);
@@ -4498,7 +4531,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"),
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"),
                 fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4546,7 +4579,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"),
+                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"),
                 fmt::arg("rs1", name(rs1)));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4595,8 +4628,8 @@ private:
         if(this->disass_enabled){
             /* generate disass */
             
-            //This disass is not yet implemented
+            //No disass specified, using instruction name
-            std::string mnemonic = "c__ebreak";
+            std::string mnemonic = "c.ebreak";
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
             jh.disass_collection.push_back(mnemonic_ptr);
@@ -4634,7 +4667,7 @@ private:
             /* generate disass */
             
             auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"),
+                "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"),
                 fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4679,7 +4712,7 @@ private:
         if(this->disass_enabled){
             /* generate disass */
             
-            //This disass is not yet implemented
+            //No disass specified, using instruction name
             std::string mnemonic = "dii";
             InvokeNode* call_print_disass;
             char* mnemonic_ptr = strdup(mnemonic.c_str());
@@ -4735,7 +4768,7 @@ private:
         gen_raise(jh, 0, 2);
         gen_sync(jh, POST_SYNC, instr_descr.size());
         gen_instr_epilogue(jh);
-        return BRANCH;
+        return ILLEGAL_INSTR;
     }
 };
 
@@ -4764,9 +4797,9 @@ continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned
         paddr = this->core.virt2phys(pc);
     auto res = this->core.read(paddr, 4, data);
     if (res != iss::Ok)
-        throw trap_access(TRAP_ID, pc.val);
+        return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
-        throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+        return JUMP_TO_SELF;
     ++inst_cnt;
     uint32_t inst_index = instr_decoder.decode_instr(instr);
     compile_func f = nullptr;

src/vm/fp_functions.cpp

@@ -128,7 +128,6 @@ uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op) {
 }
 
 uint32_t fcvt_s(uint32_t v1, uint32_t op, uint8_t mode) {
-
     float32_t v1f{v1};
     softfloat_exceptionFlags = 0;
     float32_t r;

src/vm/interp/vm_tgc5c.cpp

@@ -333,17 +333,21 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
     while(!this->core.should_stop() &&
             !(is_icount_limit_enabled(cond) && icount >= count_limit) &&
             !(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
-        fetch_count++;
+        if(this->debugging_enabled())
+            this->tgt_adapter->check_continue(*PC);
+        pc.val=*PC;
         if(fetch_ins(pc, data)!=iss::Ok){
-            this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
+            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
-            pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
+            process_spawn_blocks();
+            if(this->sync_exec && POST_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
+            pc.val = super::core.enter_trap(arch::traits<ARCH>::RV_CAUSE_FETCH_ACCESS<<16, pc.val, 0);
         } else {
             if (is_jump_to_self_enabled(cond) &&
                     (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
             uint32_t inst_index = instr_decoder.decode_instr(instr);
             opcode_e inst_id = arch::traits<ARCH>::opcode_e::MAX_OPCODE;;
             if(inst_index <instr_descr.size())
-                inst_id = instr_descr.at(instr_decoder.decode_instr(instr)).op;
+                inst_id = instr_descr[inst_index].op;
 
             // pre execution stuff
             this->core.reg.last_branch = 0;
@@ -1458,7 +1462,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 case arch::traits<ARCH>::opcode_e::ECALL: {
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
-                        this->core.disass_output(pc.val, "ecall");
+                        //No disass specified, using instruction name
+                        std::string mnemonic = "ecall";
+                        this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers// calculate next pc value
                     *NEXT_PC = *PC + 4;
@@ -1471,7 +1477,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 case arch::traits<ARCH>::opcode_e::EBREAK: {
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
-                        this->core.disass_output(pc.val, "ebreak");
+                        //No disass specified, using instruction name
+                        std::string mnemonic = "ebreak";
+                        this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers// calculate next pc value
                     *NEXT_PC = *PC + 4;
@@ -1484,7 +1492,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 case arch::traits<ARCH>::opcode_e::MRET: {
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
-                        this->core.disass_output(pc.val, "mret");
+                        //No disass specified, using instruction name
+                        std::string mnemonic = "mret";
+                        this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers// calculate next pc value
                     *NEXT_PC = *PC + 4;
@@ -1497,7 +1507,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 case arch::traits<ARCH>::opcode_e::WFI: {
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
-                        this->core.disass_output(pc.val, "wfi");
+                        //No disass specified, using instruction name
+                        std::string mnemonic = "wfi";
+                        this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers// calculate next pc value
                     *NEXT_PC = *PC + 4;
@@ -1721,7 +1733,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
                         auto mnemonic = fmt::format(
-                            "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence.i"),
+                            "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
                             fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
                         this->core.disass_output(pc.val, mnemonic);
                     }
@@ -2095,7 +2107,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
-                        this->core.disass_output(pc.val, "c.nop");
+                        //No disass specified, using instruction name
+                        std::string mnemonic = "c.nop";
+                        this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers// calculate next pc value
                     *NEXT_PC = *PC + 2;
@@ -2201,7 +2215,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     uint8_t rd = ((bit_sub<7,5>(instr)));
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
-                        this->core.disass_output(pc.val, ".reserved_clui");
+                        //No disass specified, using instruction name
+                        std::string mnemonic = ".reserved_clui";
+                        this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers// calculate next pc value
                     *NEXT_PC = *PC + 2;
@@ -2520,7 +2536,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 case arch::traits<ARCH>::opcode_e::__reserved_cmv: {
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
-                        this->core.disass_output(pc.val, ".reserved_cmv");
+                        //No disass specified, using instruction name
+                        std::string mnemonic = ".reserved_cmv";
+                        this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers// calculate next pc value
                     *NEXT_PC = *PC + 2;
@@ -2586,7 +2604,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 case arch::traits<ARCH>::opcode_e::C__EBREAK: {
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
-                        this->core.disass_output(pc.val, "c.ebreak");
+                        //No disass specified, using instruction name
+                        std::string mnemonic = "c.ebreak";
+                        this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers// calculate next pc value
                     *NEXT_PC = *PC + 2;
@@ -2625,7 +2645,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 case arch::traits<ARCH>::opcode_e::DII: {
                     if(this->disass_enabled){
                         /* generate console output when executing the command */
-                        this->core.disass_output(pc.val, "dii");
+                        //No disass specified, using instruction name
+                        std::string mnemonic = "dii";
+                        this->core.disass_output(pc.val, mnemonic);
                     }
                     // used registers// calculate next pc value
                     *NEXT_PC = *PC + 2;
@@ -2655,11 +2677,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 icount++;
                 instret++;
             }
-            cycle++;
+            *PC = *NEXT_PC;
-            pc.val=*NEXT_PC;
-            this->core.reg.PC = this->core.reg.NEXT_PC;
             this->core.reg.trap_state =  this->core.reg.pending_trap;
         }
+        fetch_count++;
+        cycle++;
     }
     return pc;
 }