replaces unordered_map with flat_hash_map

vm_base.h needs to be included before gdb_session.h as termios.h (via
boost and gdb_server) has a define which clashes with a variable name in
ConstantRange.h (via iss/llvm/vm_base.h)

CMakeLists.txt

@@ -12,6 +12,7 @@ include(flink)
 find_package(elfio QUIET)
 find_package(jsoncpp)
 find_package(Boost COMPONENTS coroutine REQUIRED)
+find_package(absl REQUIRED)
 
 add_subdirectory(softfloat)
 
@@ -104,7 +105,7 @@ if(NOT(DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND))
     target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
 endif()
 
-target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine)
+target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine abseil::abseil)
 
 if(TARGET yaml-cpp::yaml-cpp)
     target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS)

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -40,7 +40,11 @@
 #include <iss/instruction_decoder.h>
 <%def fcsr = registers.find {it.name=='FCSR'}
 if(fcsr != null) {%>
-#include <vm/fp_functions.h><%}%>
+#include <vm/fp_functions.h><%}
+def aes = functions.find { it.contains('aes') }
+if(aes != null) {%>
+#include <vm/aes_sbox.h>
+<%}%>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
 #endif
@@ -49,6 +53,22 @@ if(fcsr != null) {%>
 #include <array>
 #include <iss/debugger/riscv_target_adapter.h>
 
+#ifndef _MSC_VER
+using int128_t = __int128;
+using uint128_t = unsigned __int128;
+namespace std {
+template <> struct make_unsigned<__int128> { typedef unsigned __int128 type; };
+template <> class __make_unsigned_selector<__int128 unsigned, false, false> {
+public:
+    typedef unsigned __int128 __type;
+};
+template <> struct is_signed<int128_t> { static constexpr bool value = true; };
+template <> struct is_signed<uint128_t> { static constexpr bool value = false; };
+template <> struct is_unsigned<int128_t> { static constexpr bool value = false; };
+template <> struct is_unsigned<uint128_t> { static constexpr bool value = true; };
+} // namespace std
+#endif
+
 namespace iss {
 namespace asmjit {
 
@@ -116,9 +136,14 @@ protected:
         auto sign_mask = 1ULL<<(W-1);
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     }
+    inline void raise(uint16_t trap_id, uint16_t cause){
+        auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
+        this->core.reg.trap_state = trap_val;
+    }
+
 <%functions.each{ it.eachLine { %>
-    ${it}<%}%>
+    ${it}<%}
-<%}%>
+}%>
 private:
     /****************************************************************************
      * start opcode definitions
@@ -166,7 +191,6 @@ private:
         mov(cc, jh.next_pc, pc.val);
 
         gen_instr_prologue(jh);
-        cc.comment("//behavior:");
         /*generate behavior*/
         <%instr.behavior.eachLine{%>${it}
         <%}%>
@@ -197,7 +221,6 @@ private:
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
         mov(cc, jh.next_pc, pc.val);
         gen_instr_prologue(jh);
-        cc.comment("//behavior:");
         gen_raise(jh, 0, 2);
         gen_sync(jh, POST_SYNC, instr_descr.size());
         gen_instr_epilogue(jh);
@@ -226,8 +249,6 @@ continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_hold
     code_word_t instr = 0;
     phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&instr;
-    if(this->core.has_mmu())
-        paddr = this->core.virt2phys(pc);
     auto res = this->core.read(paddr, 4, data);
     if (res != iss::Ok)
         return ILLEGAL_FETCH;
@@ -245,24 +266,25 @@ template <typename ARCH>
 void vm_impl<ARCH>::gen_instr_prologue(jit_holder& jh) {
     auto& cc = jh.cc;
 
-    cc.comment("//gen_instr_prologue");
-
     x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
     mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
     mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state);
+    cc.comment("//Instruction prologue end");
 
 }
 template <typename ARCH>
 void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
     auto& cc = jh.cc;
 
-    cc.comment("//gen_instr_epilogue");
+    cc.comment("//Instruction epilogue begin");
     x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
     mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
     cmp(cc, current_trap_state, 0);
     cc.jne(jh.trap_entry);
     cc.inc(get_ptr_for(jh, traits::ICOUNT));
     cc.inc(get_ptr_for(jh, traits::CYCLE));
+    cc.comment("//Instruction epilogue end");
+
 }
 template <typename ARCH>
 void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
@@ -274,7 +296,7 @@ void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
 template <typename ARCH>
 void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
     x86::Compiler& cc = jh.cc;
-    cc.comment("//gen_block_epilogue");
+    cc.comment("//block epilogue begin");
     cc.ret(jh.next_pc);
 
     cc.bind(jh.trap_entry);
@@ -286,7 +308,6 @@ void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
     x86::Gp current_pc = get_reg_for_Gp(cc, traits::PC);
     mov(cc, current_pc, get_ptr_for(jh, traits::PC));
 
-    cc.comment("//enter trap call;");
     InvokeNode* call_enter_trap;
     cc.invoke(&call_enter_trap, &enter_trap, FuncSignature::build<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
     call_enter_trap->setArg(0, jh.arch_if_ptr);
@@ -304,7 +325,6 @@ void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
 template <typename ARCH>
 inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
     auto& cc = jh.cc;
-    cc.comment("//gen_raise");
     auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
     mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
     mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);

gen_input/templates/llvm/CORENAME.cpp.gtl

@@ -31,12 +31,14 @@
  *******************************************************************************/
 // clang-format off
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
+// vm_base needs to be included before gdb_session as termios.h (via boost and gdb_server) has a define which clashes with a variable
+// name in ConstantRange.h
+#include <iss/llvm/vm_base.h>
+#include <iss/iss.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
-#include <iss/iss.h>
-#include <iss/llvm/vm_base.h>
-#include <util/logging.h>
 #include <iss/instruction_decoder.h>
+#include <util/logging.h>
 <%def fcsr = registers.find {it.name=='FCSR'}
 if(fcsr != null) {%>
 #include <vm/fp_functions.h><%}%>
@@ -136,7 +138,28 @@ protected:
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     }
 <%functions.each{ it.eachLine { %>
-    ${it}<%}%>
+    ${it}<%}
+}
+if(fcsr != null) {%>
+    Value* NaNBox16(BasicBlock* bb, Value* NaNBox16_val){
+        if(static_cast<uint32_t>(traits::FLEN) == 16)
+            return this->gen_ext(NaNBox16_val, traits::FLEN, false);
+        auto box = this->builder.CreateNot((this->gen_ext(0, 32, false)));
+        return this->gen_ext((this->builder.CreateOr(this->builder.CreateShl(this->gen_ext(box, traits::FLEN), 16), this->gen_ext(NaNBox16_val, traits::FLEN))), traits::FLEN, false);
+    }
+    Value* NaNBox32(BasicBlock* bb, Value* NaNBox32_val){
+        if(static_cast<uint32_t>(traits::FLEN) == 32)
+            return this->gen_ext(NaNBox32_val, traits::FLEN, false);
+        auto box = this->builder.CreateNot((this->gen_ext(0, 64, false)));
+        return this->gen_ext((this->builder.CreateOr(this->builder.CreateShl(this->gen_ext(box, traits::FLEN), 32), this->gen_ext(NaNBox32_val, traits::FLEN))), traits::FLEN, false);
+    }
+    Value* NaNBox64(BasicBlock* bb, Value* NaNBox64_val){
+        if(static_cast<uint32_t>(traits::FLEN) == 64)
+            return this->gen_ext(NaNBox64_val, traits::FLEN, false);
+        auto box = this->builder.CreateNot((this->gen_ext(0, 128, false)));
+        return this->gen_ext((this->builder.CreateOr(this->builder.CreateShl(this->gen_ext(box, traits::FLEN), 64), this->gen_ext(NaNBox64_val, traits::FLEN))), traits::FLEN, false);
+    }
+
 <%}%>
 private:
     /****************************************************************************
@@ -251,8 +274,6 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, BasicBlock *this_block)
     // const typename traits::addr_t upper_bits = ~traits::PGMASK;
     phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&instr;
-    if(this->core.has_mmu())
-        paddr = this->core.virt2phys(pc);
     auto res = this->core.read(paddr, 4, data);
     if (res != iss::Ok) 
         return std::make_tuple(ILLEGAL_FETCH, nullptr);

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -139,7 +139,34 @@ if(fcsr != null) {%>
     }
 
 <%functions.each{ it.eachLine { %>
-    ${it}<%}%>
+    ${it}<%}
+}
+if(fcsr != null) {%>
+    value NaNBox16(tu_builder& tu, value NaNBox16_val){
+        if(static_cast<uint32_t>(traits::FLEN) == 16)
+            return tu.ext(NaNBox16_val, traits::FLEN, false);
+        else {         
+            auto box = tu.assignment(tu.logical_neg((tu.ext(0, 32, false))), traits::FLEN) ;
+            return tu.ext((tu.bitwise_or(tu.shl(box, 16), NaNBox16_val)), traits::FLEN, false);
+        } 
+    }
+    value NaNBox32(tu_builder& tu, value NaNBox32_val){
+        if(static_cast<uint32_t>(traits::FLEN) == 32)
+            return tu.ext(NaNBox32_val, traits::FLEN, false);
+        else {         
+            auto box = tu.assignment(tu.logical_neg((tu.ext(0, 64, false))), traits::FLEN) ;
+            return tu.ext((tu.bitwise_or(tu.shl(box, 32), NaNBox32_val)), traits::FLEN, false);
+        } 
+    }
+    value NaNBox64(tu_builder& tu, value NaNBox64_val){
+        if(static_cast<uint32_t>(traits::FLEN) == 64)
+            return tu.ext(NaNBox64_val, traits::FLEN, false);
+        else {
+            throw new std::runtime_error("tcc does not support Registers wider than 64 bits");     
+            auto box = tu.assignment(tu.logical_neg((tu.ext(0, 128, false))), traits::FLEN) ;
+            return tu.ext((tu.bitwise_or(tu.shl(box, 64), NaNBox64_val)), traits::FLEN, false);
+        }
+    }
 <%}%>
 private:
     /****************************************************************************
@@ -181,6 +208,8 @@ private:
         this->gen_set_tval(tu, instr);
         <%instr.behavior.eachLine{%>${it}
         <%}%>
+        tu("(*icount)++;");
+        tu("(*instret)++;");
         tu.close_scope();
         vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
         gen_trap_check(tu);        
@@ -232,8 +261,6 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, tu_builder& tu) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
     phys_addr_t paddr(pc);
-    if(this->core.has_mmu())
-        paddr = this->core.virt2phys(pc);
     auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
     if (res != iss::Ok)
         return ILLEGAL_FETCH;
@@ -278,34 +305,75 @@ template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
     os << tu.add_reg_ptr("trap_state", arch::traits<ARCH>::TRAP_STATE, this->regs_base_ptr);
     os << tu.add_reg_ptr("pending_trap", arch::traits<ARCH>::PENDING_TRAP, this->regs_base_ptr);
     os << tu.add_reg_ptr("cycle", arch::traits<ARCH>::CYCLE, this->regs_base_ptr);
-<%if(fcsr != null) {%>
+<%if(fcsr != null) {
+    def flen = constants.find { it.name == 'FLEN' }?.value ?: 0
+    %>
     os << "uint32_t (*fget_flags)()=" << (uintptr_t)&fget_flags << ";\\n";
+
+    os << "uint16_t (*fadd_h)(uint16_t v1, uint16_t v2, uint8_t mode)=" << (uintptr_t)&fadd_h << ";\\n";
+    os << "uint16_t (*fsub_h)(uint16_t v1, uint16_t v2, uint8_t mode)=" << (uintptr_t)&fsub_h << ";\\n";
+    os << "uint16_t (*fmul_h)(uint16_t v1, uint16_t v2, uint8_t mode)=" << (uintptr_t)&fmul_h << ";\\n";
+    os << "uint16_t (*fdiv_h)(uint16_t v1, uint16_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_h << ";\\n";
+    os << "uint16_t (*fsqrt_h)(uint16_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_h << ";\\n";
+    os << "uint16_t (*fcmp_h)(uint16_t v1, uint16_t v2, uint16_t op)=" << (uintptr_t)&fcmp_h << ";\\n";
+    os << "uint16_t (*fmadd_h)(uint16_t v1, uint16_t v2, uint16_t v3, uint16_t op, uint8_t mode)=" << (uintptr_t)&fmadd_h << ";\\n";
+    os << "uint16_t (*fsel_h)(uint16_t v1, uint16_t v2, uint16_t op)=" << (uintptr_t)&fsel_h << ";\\n";
+    os << "uint16_t (*fclass_h)(uint16_t v1)=" << (uintptr_t)&fclass_h << ";\\n";
+    os << "uint16_t (*unbox_h)(uint8_t FLEN, uint64_t v)=" << (uintptr_t)&unbox_h << ";\\n";
+
+    os << "uint32_t (*f16toi32)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&f16toi32 << ";\\n";
+    os << "uint32_t (*f16toui32)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&f16toui32 << ";\\n";
+    os << "uint16_t (*i32tof16)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&i32tof16 << ";\\n";
+    os << "uint16_t (*ui32tof16)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&ui32tof16 << ";\\n";
+    os << "uint64_t (*f16toi64)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&f16toi64 <<";\\n";
+    os << "uint64_t (*f16toui64)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&f16toui64 <<";\\n";
+    os << "uint16_t (*i64tof16)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&i64tof16 <<";\\n";
+    os << "uint16_t (*ui64tof16)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&ui64tof16 <<";\\n";
+
     os << "uint32_t (*fadd_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fadd_s << ";\\n";
     os << "uint32_t (*fsub_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fsub_s << ";\\n";
     os << "uint32_t (*fmul_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fmul_s << ";\\n";
     os << "uint32_t (*fdiv_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_s << ";\\n";
     os << "uint32_t (*fsqrt_s)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_s << ";\\n";
     os << "uint32_t (*fcmp_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fcmp_s << ";\\n";
-    os << "uint32_t (*fcvt_s)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_s << ";\\n";
     os << "uint32_t (*fmadd_s)(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_s << ";\\n";
     os << "uint32_t (*fsel_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fsel_s << ";\\n";
     os << "uint32_t (*fclass_s)( uint32_t v1 )=" << (uintptr_t)&fclass_s << ";\\n";
-    os << "uint32_t (*fconv_d2f)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fconv_d2f << ";\\n";
+    os << "uint32_t (*unbox_s)(uint8_t FLEN, uint64_t v)=" << (uintptr_t)&unbox_s << ";\\n";
-    os << "uint64_t (*fconv_f2d)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fconv_f2d << ";\\n";
+
+    os << "uint32_t (*f32toi32)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&f32toi32 << ";\\n";
+    os << "uint32_t (*f32toui32)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&f32toui32 << ";\\n";
+    os << "uint32_t (*i32tof32)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&i32tof32 << ";\\n";
+    os << "uint32_t (*ui32tof32)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&ui32tof32 << ";\\n";
+    os << "uint64_t (*f32toi64)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&f32toi64 <<";\\n";
+    os << "uint64_t (*f32toui64)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&f32toui64 <<";\\n";
+    os << "uint32_t (*i64tof32)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&i64tof32 <<";\\n";
+    os << "uint32_t (*ui64tof32)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&ui64tof32 <<";\\n";
+    <%if(flen > 32) {%>
+
     os << "uint64_t (*fadd_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fadd_d << ";\\n";
     os << "uint64_t (*fsub_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fsub_d << ";\\n";
     os << "uint64_t (*fmul_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fmul_d << ";\\n";
     os << "uint64_t (*fdiv_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_d << ";\\n";
     os << "uint64_t (*fsqrt_d)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_d << ";\\n";
     os << "uint64_t (*fcmp_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fcmp_d << ";\\n";
-    os << "uint64_t (*fcvt_d)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_d << ";\\n";
     os << "uint64_t (*fmadd_d)(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_d << ";\\n";
     os << "uint64_t (*fsel_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fsel_d << ";\\n";
     os << "uint64_t (*fclass_d)(uint64_t v1  )=" << (uintptr_t)&fclass_d << ";\\n";
-    os << "uint64_t (*fcvt_32_64)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_32_64 << ";\\n";
+    os << "uint64_t (*unbox_d)(uint8_t FLEN, uint64_t v)=" << (uintptr_t)&unbox_d << ";\\n";
-    os << "uint32_t (*fcvt_64_32)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_64_32 << ";\\n";
+
-    os << "uint32_t (*unbox_s)(uint64_t v)=" << (uintptr_t)&unbox_s << ";\\n";
+    os << "uint32_t (*f64tof32)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&f64tof32 << ";\\n";
-    <%}%>
+    os << "uint64_t (*f32tof64)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&f32tof64 << ";\\n";
+    os << "uint64_t (*f64toi64)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&f64toi64 <<";\\n";
+    os << "uint64_t (*f64toui64)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&f64toui64 <<";\\n";
+    os << "uint64_t (*i64tof64)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&i64tof64 <<";\\n";
+    os << "uint64_t (*ui64tof64)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&ui64tof64 <<";\\n";
+    os << "uint64_t (*i32tof64)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&i32tof64 <<";\\n";
+    os << "uint64_t (*ui32tof64)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&ui32tof64 <<";\\n";
+    os << "uint32_t (*f64toi32)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&f64toi32 <<";\\n";
+    os << "uint32_t (*f64toui32)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&f64toui32 <<";\\n";
+    <%}
+    }%>
     tu.add_prologue(os.str());
 }
 

src/iss/arch/riscv_hart_common.h

@@ -37,6 +37,7 @@
 
 #include "mstatus.h"
 #include "util/delegate.h"
+#include <absl/container/flat_hash_map.h>
 #include <array>
 #include <cstdint>
 #include <elfio/elfio.hpp>
@@ -259,8 +260,8 @@ template <typename WORD_TYPE> struct priv_if {
     std::function<iss::status(unsigned, WORD_TYPE)> write_csr;
     std::function<iss::status(uint8_t const*)> exec_htif;
     std::function<void(uint16_t, uint16_t, WORD_TYPE)> raise_trap; // trap_id, cause, fault_data
-    std::unordered_map<unsigned, rd_csr_f>& csr_rd_cb;
+    absl::flat_hash_map<unsigned, rd_csr_f>& csr_rd_cb;
-    std::unordered_map<unsigned, wr_csr_f>& csr_wr_cb;
+    absl::flat_hash_map<unsigned, wr_csr_f>& csr_wr_cb;
     hart_state<WORD_TYPE>& state;
     uint8_t& PRIV;
     WORD_TYPE& PC;
@@ -775,7 +776,7 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
                                       this->fault_data = fault_data;
                                   },
                               .csr_rd_cb{this->csr_rd_cb},
-                              .csr_wr_cb{csr_wr_cb},
+                              .csr_wr_cb{this->csr_wr_cb},
                               .state{this->state},
                               .PRIV{this->reg.PRIV},
                               .PC{this->reg.PC},
@@ -893,8 +894,8 @@ protected:
     using csr_page_type = typename csr_type::page_type;
     csr_type csr;
 
-    std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
+    absl::flat_hash_map<unsigned, rd_csr_f> csr_rd_cb;
-    std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
+    absl::flat_hash_map<unsigned, wr_csr_f> csr_wr_cb;
 
     reg_t mhartid_reg{0x0};
     uint64_t mcycle_csr{0};

src/iss/arch/riscv_hart_m_p.h

@@ -134,7 +134,7 @@ protected:
 
     hart_state<reg_t> state;
 
-    std::unordered_map<uint64_t, uint8_t> atomic_reservation;
+    absl::flat_hash_map<uint64_t, uint8_t> atomic_reservation;
 
     iss::status read_status(unsigned addr, reg_t& val);
     iss::status write_status(unsigned addr, reg_t val);

src/iss/arch/riscv_hart_msu_vp.h

@@ -48,9 +48,9 @@
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
 #endif
+#include <fmt/format.h>
 #include <iss/mem/memory_with_htif.h>
 #include <iss/mem/mmu.h>
-#include <fmt/format.h>
 #include <type_traits>
 #include <unordered_map>
 
@@ -150,7 +150,7 @@ protected:
 
     hart_state<reg_t> state;
 
-    std::unordered_map<uint64_t, uint8_t> atomic_reservation;
+    absl::flat_hash_map<uint64_t, uint8_t> atomic_reservation;
 
     iss::status read_status(unsigned addr, reg_t& val);
     iss::status write_status(unsigned addr, reg_t val);

src/iss/arch/riscv_hart_mu_p.h

@@ -160,7 +160,7 @@ protected:
 
     hart_state<reg_t> state;
 
-    std::unordered_map<uint64_t, uint8_t> atomic_reservation;
+    absl::flat_hash_map<uint64_t, uint8_t> atomic_reservation;
 
     iss::status read_status(unsigned addr, reg_t& val);
     iss::status write_status(unsigned addr, reg_t val);

src/iss/mem/mmu.h

@@ -32,9 +32,9 @@
  *       eyck@minres.com - initial implementation
  ******************************************************************************/
 
-#include "memory_if.h"
 #include "iss/arch/riscv_hart_common.h"
 #include "iss/vm_types.h"
+#include "memory_if.h"
 #include <util/logging.h>
 
 namespace iss {
@@ -238,7 +238,7 @@ private:
 
 protected:
     reg_t satp;
-    std::unordered_map<reg_t, uint64_t> ptw;
+    absl::flat_hash_map<reg_t, uint64_t> ptw;
     std::array<vm_info, 2> vmt;
     std::array<address_type, 4> addr_mode;
 

src/vm/aes_sbox.h

@@ -35,7 +35,7 @@
 #ifndef _VM_AES_SBOX_H_
 #define _VM_AES_SBOX_H_
 #include <cstdint>
-
+extern "C" {
 const uint8_t AES_ENC_SBOX[] = {
     0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76, 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59,
     0x47, 0xF0, 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0, 0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1,
@@ -65,5 +65,6 @@ const uint8_t AES_DEC_SBOX[] = {
     0x93, 0xC9, 0x9C, 0xEF, 0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0, 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61, 0x17, 0x2B,
     0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D};
 uint8_t inline aes_sbox_inv(uint8_t index) { return AES_DEC_SBOX[index]; }
+}
 
 #endif /* _VM_AES_SBOX_H_ */

src/vm/fp_functions.h

@@ -49,7 +49,6 @@ uint16_t fsqrt_h(uint16_t v1, uint8_t mode);
 uint16_t fcmp_h(uint16_t v1, uint16_t v2, uint16_t op);
 uint16_t fmadd_h(uint16_t v1, uint16_t v2, uint16_t v3, uint16_t op, uint8_t mode);
 uint16_t fsel_h(uint16_t v1, uint16_t v2, uint16_t op);
-uint16_t fsqrt_h(uint16_t v1, uint8_t mode);
 uint16_t fclass_h(uint16_t v1);
 uint16_t frsqrt7_h(uint16_t v);
 uint16_t frec7_h(uint16_t v, uint8_t mode);

src/vm/interp/vm_tgc5c.cpp

@@ -38,14 +38,17 @@
 #include <iss/iss.h>
 #include <iss/interp/vm_base.h>
 
+#include <stdexcept>
+#include <unordered_map>
 #include <util/logging.h>
 #include <boost/coroutine2/all.hpp>
 #include <functional>
 #include <exception>
+#include <utility>
 #include <vector>
 #include <sstream>
 #include <iss/instruction_decoder.h>
-
+#include <absl/container/flat_hash_map.h>
 
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -255,6 +258,11 @@ private:
             return iss::Err;
         return iss::Ok;
     }
+
+    struct translation_buffer {
+        std::vector<std::tuple<opcode_e, uint64_t, uint32_t>> entries;
+    } tb;
+    absl::flat_hash_map<uint64_t, translation_buffer> tb_lut;
 };
 
 template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
@@ -312,27 +320,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
     auto& instr =  this->core.reg.instruction;
     // we fetch at max 4 byte, alignment is 2
     auto *const data = reinterpret_cast<uint8_t*>(&instr);
-
+    auto exec = [this, PC, NEXT_PC](opcode_e inst_id, uint64_t pc, uint32_t instr) {
-    while(!this->core.should_stop() &&
+                // pre execution stuff
-            !(is_icount_limit_enabled(cond) && icount >= count_limit) &&
-            !(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
-        if(this->debugging_enabled())
-            this->tgt_adapter->check_continue(*PC);
-        pc.val=*PC;
-        if(fetch_ins(pc, data)!=iss::Ok){
-            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
-            process_spawn_blocks();
-            if(this->sync_exec && POST_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
-            pc.val = super::core.enter_trap(arch::traits<ARCH>::RV_CAUSE_FETCH_ACCESS<<16, pc.val, 0);
-        } else {
-            if (is_jump_to_self_enabled(cond) &&
-                    (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-            uint32_t inst_index = instr_decoder.decode_instr(instr);
-            opcode_e inst_id = arch::traits<ARCH>::opcode_e::MAX_OPCODE;;
-            if(inst_index <instr_descr.size())
-                inst_id = instr_descr[inst_index].op;
-
-            // pre execution stuff
             this->core.reg.last_branch = 0;
             if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
             try{
@@ -345,7 +334,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"),
                             fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -372,7 +361,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"),
                             fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -399,7 +388,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"),
                             fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -436,7 +425,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -474,7 +463,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"),
                             fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -510,7 +499,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"),
                             fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -546,7 +535,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"),
                             fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -582,7 +571,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"),
                             fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -618,7 +607,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"),
                             fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -654,7 +643,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"),
                             fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -690,7 +679,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"),
                             fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -722,7 +711,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"),
                             fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -754,7 +743,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"),
                             fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -786,7 +775,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"),
                             fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -818,7 +807,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"),
                             fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -850,7 +839,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"),
                             fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -878,7 +867,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"),
                             fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -906,7 +895,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"),
                             fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -934,7 +923,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -962,7 +951,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -990,7 +979,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1018,7 +1007,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1046,7 +1035,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1074,7 +1063,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1102,7 +1091,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1130,7 +1119,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1158,7 +1147,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1186,7 +1175,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1214,7 +1203,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1242,7 +1231,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1270,7 +1259,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1298,7 +1287,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1326,7 +1315,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1354,7 +1343,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1382,7 +1371,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1410,7 +1399,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1438,7 +1427,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1468,7 +1457,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"),
                             fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     // calculate next pc value
@@ -1485,7 +1474,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         /* generate console output when executing the command */
                         //No disass specified, using instruction name
                         std::string mnemonic = "ecall";
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     // calculate next pc value
@@ -1501,7 +1490,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         /* generate console output when executing the command */
                         //No disass specified, using instruction name
                         std::string mnemonic = "ebreak";
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     // calculate next pc value
@@ -1517,7 +1506,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         /* generate console output when executing the command */
                         //No disass specified, using instruction name
                         std::string mnemonic = "mret";
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     // calculate next pc value
@@ -1533,7 +1522,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         /* generate console output when executing the command */
                         //No disass specified, using instruction name
                         std::string mnemonic = "wfi";
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     // calculate next pc value
@@ -1553,7 +1542,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"),
                             fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1591,7 +1580,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"),
                             fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1627,7 +1616,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"),
                             fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1663,7 +1652,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"),
                             fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1696,7 +1685,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"),
                             fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1731,7 +1720,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"),
                             fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1766,7 +1755,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
                             fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     // calculate next pc value
@@ -1787,7 +1776,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1816,7 +1805,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1845,7 +1834,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1874,7 +1863,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1903,7 +1892,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1944,7 +1933,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -1979,7 +1968,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2022,7 +2011,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2056,7 +2045,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"),
                             fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2082,7 +2071,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"),
                             fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2106,7 +2095,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"),
                             fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2128,7 +2117,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"),
                             fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2153,7 +2142,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         /* generate console output when executing the command */
                         //No disass specified, using instruction name
                         std::string mnemonic = "c.nop";
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     // calculate next pc value
@@ -2170,7 +2159,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.jal"),
                             fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2192,7 +2181,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"),
                             fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2219,7 +2208,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"),
                             fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2243,7 +2232,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c.addi16sp"),
                             fmt::arg("nzimm", nzimm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2266,7 +2255,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         /* generate console output when executing the command */
                         //No disass specified, using instruction name
                         std::string mnemonic = ".reserved_clui";
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     // calculate next pc value
@@ -2285,7 +2274,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"),
                             fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2305,7 +2294,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"),
                             fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2332,7 +2321,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"),
                             fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2352,7 +2341,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"),
                             fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2372,7 +2361,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"),
                             fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2392,7 +2381,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"),
                             fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2412,7 +2401,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"),
                             fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2431,7 +2420,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"),
                             fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     // calculate next pc value
@@ -2451,7 +2440,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"),
                             fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2474,7 +2463,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"),
                             fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2497,7 +2486,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"),
                             fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2524,7 +2513,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"),
                             fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2552,7 +2541,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2578,7 +2567,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"),
                             fmt::arg("rs1", name(rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2602,7 +2591,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         /* generate console output when executing the command */
                         //No disass specified, using instruction name
                         std::string mnemonic = ".reserved_cmv";
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     // calculate next pc value
@@ -2621,7 +2610,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"),
                             fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2647,7 +2636,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"),
                             fmt::arg("rs1", name(rs1)));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2673,7 +2662,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         /* generate console output when executing the command */
                         //No disass specified, using instruction name
                         std::string mnemonic = "c.ebreak";
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     // calculate next pc value
@@ -2692,7 +2681,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         auto mnemonic = fmt::format(
                             "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"),
                             fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
@@ -2716,7 +2705,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         /* generate console output when executing the command */
                         //No disass specified, using instruction name
                         std::string mnemonic = "dii";
-                        this->core.disass_output(pc.val, mnemonic);
+                        this->core.disass_output(pc, mnemonic);
                     }
                     // used registers
                     // calculate next pc value
@@ -2739,16 +2728,54 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
             // if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt
             //    this->core.reg.trap_state =  this->core.reg.pending_trap;
             // trap check
-            if(trap_state!=0){
+            if(this->core.reg.trap_state!=0){
                 //In case of Instruction address misaligned (cause = 0 and trapid = 0) need the targeted addr (in tval)
-                auto mcause = (trap_state>>16) & 0xff; 
+                auto mcause = (this->core.reg.trap_state>>16) & 0xff; 
-                super::core.enter_trap(trap_state, pc.val, mcause ? instr:tval);
+                super::core.enter_trap(this->core.reg.trap_state, pc, mcause ? instr:tval);
             } else {
-                icount++;
+                this->core.reg.icount++;
-                instret++;
+                this->core.reg.instret++;
             }
             *PC = *NEXT_PC;
             this->core.reg.trap_state =  this->core.reg.pending_trap;
+
+    };
+    while(!this->core.should_stop() &&
+            !(is_icount_limit_enabled(cond) && icount >= count_limit) &&
+            !(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
+        if(this->debugging_enabled())
+            this->tgt_adapter->check_continue(*PC);
+        pc.val=*PC;
+        auto current_tb = tb_lut.find(pc.val);
+        if(current_tb==tb_lut.end()) {
+            auto res = tb_lut.insert(std::make_pair(pc.val,translation_buffer{}));
+            if(!res.second)
+                throw std::runtime_error("");
+            current_tb=res.first;
+            do {
+                if(fetch_ins(pc, data)!=iss::Ok){
+                    if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
+                    process_spawn_blocks();
+                    if(this->sync_exec && POST_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
+                    pc.val = super::core.enter_trap(arch::traits<ARCH>::RV_CAUSE_FETCH_ACCESS<<16, pc.val, 0);
+                    break;
+                } else {
+                    if (is_jump_to_self_enabled(cond) &&
+                            (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+                    uint32_t inst_index = instr_decoder.decode_instr(instr);
+                    opcode_e inst_id = arch::traits<ARCH>::opcode_e::MAX_OPCODE;;
+                    if(inst_index <instr_descr.size())
+                        inst_id = instr_descr[inst_index].op;
+                    if(is_jump_to_self_enabled(cond) &&
+                        inst_id==arch::traits<ARCH>::opcode_e::JAL && !bit_sub<7, 25>(instr) ||
+                        inst_id == arch::traits<ARCH>::opcode_e::C__J && !bit_sub<2, 11>(instr))
+                        throw simulation_stopped(0);
+                    exec(inst_id, pc.val, instr);
+                }
+            } while(this->core.reg.last_branch==0);
+        } else {
+            for(auto& e:current_tb->second.entries)
+                exec(std::get<0>(e), std::get<1>(e), std::get<2>(e));
         }
         fetch_count++;
         cycle++;

src/vm/llvm/fp_impl.cpp

@@ -72,32 +72,70 @@ using namespace ::llvm;
 void add_fp_functions_2_module(Module* mod, uint32_t flen, uint32_t xlen) {
     if(flen) {
         FDECL(fget_flags, INT_TYPE(32));
+
+        FDECL(fadd_h, INT_TYPE(16), INT_TYPE(16), INT_TYPE(16), INT_TYPE(8));
+        FDECL(fsub_h, INT_TYPE(16), INT_TYPE(16), INT_TYPE(16), INT_TYPE(8));
+        FDECL(fmul_h, INT_TYPE(16), INT_TYPE(16), INT_TYPE(16), INT_TYPE(8));
+        FDECL(fdiv_h, INT_TYPE(16), INT_TYPE(16), INT_TYPE(16), INT_TYPE(8));
+        FDECL(fsqrt_h, INT_TYPE(16), INT_TYPE(16), INT_TYPE(8));
+        FDECL(fcmp_h, INT_TYPE(16), INT_TYPE(16), INT_TYPE(16), INT_TYPE(16));
+        FDECL(fmadd_h, INT_TYPE(16), INT_TYPE(16), INT_TYPE(16), INT_TYPE(16), INT_TYPE(16), INT_TYPE(8));
+        FDECL(fsel_h, INT_TYPE(16), INT_TYPE(16), INT_TYPE(16), INT_TYPE(16));
+        FDECL(fclass_h, INT_TYPE(16), INT_TYPE(16));
+        FDECL(unbox_h, INT_TYPE(16), INT_TYPE(32), INT_TYPE(64)); // technically the first arg is only 8 bits
+
+        FDECL(f16toi32, INT_TYPE(32), INT_TYPE(32), INT_TYPE(8))
+        FDECL(f16toui32, INT_TYPE(32), INT_TYPE(32), INT_TYPE(8))
+        FDECL(i32tof16, INT_TYPE(16), INT_TYPE(32), INT_TYPE(8))
+        FDECL(ui32tof16, INT_TYPE(16), INT_TYPE(32), INT_TYPE(8))
+        FDECL(f16toi64, INT_TYPE(64), INT_TYPE(32), INT_TYPE(8))
+        FDECL(f16toui64, INT_TYPE(64), INT_TYPE(32), INT_TYPE(8))
+        FDECL(i64tof16, INT_TYPE(16), INT_TYPE(64), INT_TYPE(8))
+        FDECL(ui64tof16, INT_TYPE(16), INT_TYPE(64), INT_TYPE(8))
+
         FDECL(fadd_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
         FDECL(fsub_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
         FDECL(fmul_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
         FDECL(fdiv_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
         FDECL(fsqrt_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
         FDECL(fcmp_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32));
-        FDECL(fcvt_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
         FDECL(fmadd_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
         FDECL(fsel_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32));
         FDECL(fclass_s, INT_TYPE(32), INT_TYPE(32));
-        FDECL(fcvt_32_64, INT_TYPE(64), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
+        FDECL(unbox_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(64)); // technically the first arg is only 8 bits
-        FDECL(fcvt_64_32, INT_TYPE(32), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
+
+        FDECL(f32toi32, INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
+        FDECL(f32toui32, INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
+        FDECL(i32tof32, INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
+        FDECL(ui32tof32, INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
+        FDECL(f32toi64, INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
+        FDECL(f32toui64, INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
+        FDECL(i64tof32, INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
+        FDECL(ui64tof32, INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
         if(flen > 32) {
-            FDECL(fconv_d2f, INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
+
-            FDECL(fconv_f2d, INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
             FDECL(fadd_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
             FDECL(fsub_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
             FDECL(fmul_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
             FDECL(fdiv_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
             FDECL(fsqrt_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
             FDECL(fcmp_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32));
-            FDECL(fcvt_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
             FDECL(fmadd_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
             FDECL(fsel_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32));
             FDECL(fclass_d, INT_TYPE(64), INT_TYPE(64));
-            FDECL(unbox_s, INT_TYPE(32), INT_TYPE(64));
+
+            FDECL(f64tof32, INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
+            FDECL(f32tof64, INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
+            FDECL(f64toi64, INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
+            FDECL(f64toui64, INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
+            FDECL(i64tof64, INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
+            FDECL(ui64tof64, INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
+            FDECL(i32tof64, INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
+            FDECL(ui32tof64, INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
+            FDECL(f64toi32, INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
+            FDECL(f64toui32, INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
+
+            FDECL(unbox_d, INT_TYPE(64), INT_TYPE(32), INT_TYPE(64)); // technically the first arg is only 8 bits
         }
     }
 }

src/vm/llvm/vm_tgc5c.cpp

@@ -31,10 +31,12 @@
  *******************************************************************************/
 // clang-format off
 #include <iss/arch/tgc5c.h>
+// vm_base needs to be included before gdb_session as termios.h (via boost and gdb_server) has a define which clashes with a variable
+// name in ConstantRange.h
+#include <iss/llvm/vm_base.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
-#include <iss/llvm/vm_base.h>
 #include <util/logging.h>
 #include <iss/instruction_decoder.h>
 
@@ -353,7 +355,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -399,7 +401,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -446,7 +448,7 @@ private:
         /*generate behavior*/
         this->builder.CreateStore(this->gen_const(32U, static_cast<int>(NO_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
         if(rd>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto new_pc =(uint32_t)(PC+(int32_t)sext<21>(imm));
@@ -503,7 +505,7 @@ private:
         /*generate behavior*/
         this->builder.CreateStore(this->gen_const(32U, static_cast<int>(NO_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto addr_mask =(uint32_t)- 2;
@@ -584,7 +586,7 @@ private:
         /*generate behavior*/
         this->builder.CreateStore(this->gen_const(32U, static_cast<int>(NO_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             {
@@ -649,7 +651,7 @@ private:
         /*generate behavior*/
         this->builder.CreateStore(this->gen_const(32U, static_cast<int>(NO_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             {
@@ -714,7 +716,7 @@ private:
         /*generate behavior*/
         this->builder.CreateStore(this->gen_const(32U, static_cast<int>(NO_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             {
@@ -783,7 +785,7 @@ private:
         /*generate behavior*/
         this->builder.CreateStore(this->gen_const(32U, static_cast<int>(NO_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             {
@@ -852,7 +854,7 @@ private:
         /*generate behavior*/
         this->builder.CreateStore(this->gen_const(32U, static_cast<int>(NO_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             {
@@ -917,7 +919,7 @@ private:
         /*generate behavior*/
         this->builder.CreateStore(this->gen_const(32U, static_cast<int>(NO_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             {
@@ -981,7 +983,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto load_address =this->gen_ext(
@@ -1039,7 +1041,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto load_address =this->gen_ext(
@@ -1097,7 +1099,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto load_address =this->gen_ext(
@@ -1155,7 +1157,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto load_address =this->gen_ext(
@@ -1211,7 +1213,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto load_address =this->gen_ext(
@@ -1267,7 +1269,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto store_address =this->gen_ext(
@@ -1320,7 +1322,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto store_address =this->gen_ext(
@@ -1373,7 +1375,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto store_address =this->gen_ext(
@@ -1426,7 +1428,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -1478,7 +1480,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -1532,7 +1534,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -1585,7 +1587,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -1635,7 +1637,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -1685,7 +1687,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -1735,7 +1737,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -1785,7 +1787,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -1835,7 +1837,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -1887,7 +1889,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -1939,7 +1941,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -1991,7 +1993,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -2044,7 +2046,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -2099,7 +2101,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -2152,7 +2154,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -2202,7 +2204,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -2255,7 +2257,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -2311,7 +2313,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -2361,7 +2363,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -2553,10 +2555,10 @@ private:
         
         this->gen_instr_prologue();
         /*generate behavior*/
-        std::vector<Value*> wait_231_args{
+        std::vector<Value*> wait_57_args{
             this->gen_ext(this->gen_const(8,1), 32)
         };
-        this->builder.CreateCall(this->mod->getFunction("wait"), wait_231_args);
+        this->builder.CreateCall(this->mod->getFunction("wait"), wait_57_args);
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
         auto returnValue = std::make_tuple(CONT,bb);
         
@@ -2595,7 +2597,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto xrs1 =this->gen_reg_load(traits::X0+ rs1);
@@ -2651,7 +2653,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto xrd =this->gen_read_mem(traits::CSR, csr, 4);
@@ -2708,7 +2710,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto xrd =this->gen_read_mem(traits::CSR, csr, 4);
@@ -2765,7 +2767,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto xrd =this->gen_read_mem(traits::CSR, csr, 4);
@@ -2816,7 +2818,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto xrd =this->gen_read_mem(traits::CSR, csr, 4);
@@ -2872,7 +2874,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto xrd =this->gen_read_mem(traits::CSR, csr, 4);
@@ -2968,7 +2970,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto res =this->builder.CreateMul(
@@ -3023,7 +3025,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto res =this->builder.CreateMul(
@@ -3081,7 +3083,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto res =this->builder.CreateMul(
@@ -3138,7 +3140,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto res =this->builder.CreateMul(
@@ -3194,7 +3196,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto dividend =this->gen_ext(
@@ -3298,7 +3300,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             {
@@ -3371,7 +3373,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             {
@@ -3479,7 +3481,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             {
@@ -3561,7 +3563,7 @@ private:
             get_reg_ptr(rd+8 + traits::X0), false);
         }
         else{
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
         auto returnValue = std::make_tuple(CONT,bb);
@@ -3698,7 +3700,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rs1!=0) {
@@ -3825,7 +3827,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -3871,7 +3873,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(imm==0||rd>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         if(rd!=0) {
             this->builder.CreateStore(
@@ -3924,7 +3926,7 @@ private:
             get_reg_ptr(2 + traits::X0), false);
         }
         else{
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
         auto returnValue = std::make_tuple(CONT,bb);
@@ -3960,7 +3962,7 @@ private:
         
         this->gen_instr_prologue();
         /*generate behavior*/
-        this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+        this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
         auto returnValue = std::make_tuple(CONT,bb);
         
@@ -4459,7 +4461,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rs1!=0) {
@@ -4508,7 +4510,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rd==0) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto offs =this->gen_ext(
@@ -4562,7 +4564,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -4689,7 +4691,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             if(rd!=0) {
@@ -4740,7 +4742,7 @@ private:
         /*generate behavior*/
         this->builder.CreateStore(this->gen_const(32U, static_cast<int>(NO_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
         if(rs1>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto addr_mask =(uint32_t)- 2;
@@ -4826,7 +4828,7 @@ private:
         this->gen_instr_prologue();
         /*generate behavior*/
         if(rs2>=static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
             auto offs =this->gen_ext(
@@ -4874,7 +4876,7 @@ private:
         
         this->gen_instr_prologue();
         /*generate behavior*/
-        this->gen_raise_trap(0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
+        this->gen_raise_trap(0, static_cast<uint32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
         auto returnValue = std::make_tuple(CONT,bb);
         

src/vm/tcc/vm_tgc5c.cpp

@@ -348,7 +348,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -384,7 +384,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -421,7 +421,7 @@ private:
         this->gen_set_tval(tu, instr);
         tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(NO_JUMP),32));
         if(rd>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto new_pc = (uint32_t)(PC+(int32_t)sext<21>(imm));
@@ -468,7 +468,7 @@ private:
         this->gen_set_tval(tu, instr);
         tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(NO_JUMP),32));
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto addr_mask = (uint32_t)- 2;
@@ -526,7 +526,7 @@ private:
         this->gen_set_tval(tu, instr);
         tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(NO_JUMP),32));
         if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	tu.open_if(tu.icmp(ICmpInst::ICMP_EQ,
@@ -576,7 +576,7 @@ private:
         this->gen_set_tval(tu, instr);
         tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(NO_JUMP),32));
         if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
@@ -626,7 +626,7 @@ private:
         this->gen_set_tval(tu, instr);
         tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(NO_JUMP),32));
         if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	tu.open_if(tu.icmp(ICmpInst::ICMP_SLT,
@@ -676,7 +676,7 @@ private:
         this->gen_set_tval(tu, instr);
         tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(NO_JUMP),32));
         if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	tu.open_if(tu.icmp(ICmpInst::ICMP_SGE,
@@ -726,7 +726,7 @@ private:
         this->gen_set_tval(tu, instr);
         tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(NO_JUMP),32));
         if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	tu.open_if(tu.icmp(ICmpInst::ICMP_ULT,
@@ -776,7 +776,7 @@ private:
         this->gen_set_tval(tu, instr);
         tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(NO_JUMP),32));
         if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	tu.open_if(tu.icmp(ICmpInst::ICMP_UGE,
@@ -825,7 +825,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto load_address = tu.assignment(tu.ext((tu.add(
@@ -866,7 +866,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto load_address = tu.assignment(tu.ext((tu.add(
@@ -907,7 +907,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto load_address = tu.assignment(tu.ext((tu.add(
@@ -948,7 +948,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto load_address = tu.assignment(tu.ext((tu.add(
@@ -989,7 +989,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto load_address = tu.assignment(tu.ext((tu.add(
@@ -1030,7 +1030,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto store_address = tu.assignment(tu.ext((tu.add(
@@ -1068,7 +1068,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto store_address = tu.assignment(tu.ext((tu.add(
@@ -1106,7 +1106,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto store_address = tu.assignment(tu.ext((tu.add(
@@ -1144,7 +1144,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1183,7 +1183,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1222,7 +1222,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1261,7 +1261,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1300,7 +1300,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1339,7 +1339,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1378,7 +1378,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1417,7 +1417,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1456,7 +1456,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1495,7 +1495,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1534,7 +1534,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1573,7 +1573,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1614,7 +1614,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1653,7 +1653,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1692,7 +1692,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1731,7 +1731,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1772,7 +1772,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1813,7 +1813,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -1852,7 +1852,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -2030,7 +2030,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto xrs1 = tu.assignment(tu.load(rs1 + traits::X0, 0),32);
@@ -2072,7 +2072,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32);
@@ -2116,7 +2116,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32);
@@ -2160,7 +2160,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32);
@@ -2199,7 +2199,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32);
@@ -2242,7 +2242,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32);
@@ -2315,7 +2315,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto res = tu.assignment(tu.mul(
@@ -2355,7 +2355,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto res = tu.assignment(tu.mul(
@@ -2397,7 +2397,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto res = tu.assignment(tu.mul(
@@ -2439,7 +2439,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto res = tu.assignment(tu.mul(
@@ -2481,7 +2481,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto dividend = tu.assignment(tu.ext(tu.load(rs1 + traits::X0, 0),32,true),32);
@@ -2546,7 +2546,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
@@ -2597,7 +2597,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
@@ -2665,7 +2665,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
@@ -2720,7 +2720,7 @@ private:
                tu.constant(imm,16))),32,false));
         }
         else{
-        	this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+        	this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         auto returnValue = CONT;
         
@@ -2817,7 +2817,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rs1!=0) {
@@ -2913,7 +2913,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -2949,7 +2949,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(imm==0||rd>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         if(rd!=0) {
             tu.store(rd + traits::X0, tu.constant((uint32_t)((int32_t)sext<18>(imm)),32));
@@ -2987,7 +2987,7 @@ private:
                tu.constant((int16_t)sext<10>(nzimm),16))),32,false));
         }
         else{
-        	this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+        	this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         auto returnValue = CONT;
         
@@ -3015,7 +3015,7 @@ private:
         tu("(*cycle)++;");
         tu.open_scope();
         this->gen_set_tval(tu, instr);
-        this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+        this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         auto returnValue = CONT;
         
         tu.close_scope();
@@ -3376,7 +3376,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rs1!=0) {
@@ -3414,7 +3414,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)||rd==0) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto offs = tu.assignment(tu.ext((tu.add(
@@ -3451,7 +3451,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -3551,7 +3551,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rd>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	if(rd!=0) {
@@ -3589,7 +3589,7 @@ private:
         this->gen_set_tval(tu, instr);
         tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(NO_JUMP),32));
         if(rs1>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto addr_mask = (uint32_t)- 2;
@@ -3656,7 +3656,7 @@ private:
         tu.open_scope();
         this->gen_set_tval(tu, instr);
         if(rs2>=static_cast<uint32_t>(traits:: RFS)) {
-            this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+            this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         }
         else{
         	auto offs = tu.assignment(tu.ext((tu.add(
@@ -3689,7 +3689,7 @@ private:
         tu("(*cycle)++;");
         tu.open_scope();
         this->gen_set_tval(tu, instr);
-        this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
+        this->gen_raise_trap(tu, 0, static_cast<uint32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
         auto returnValue = CONT;
         
         tu.close_scope();
@@ -3831,4 +3831,4 @@ volatile std::array<bool, 2> dummy = {
 };
 }
 }
-// clang-format on
+// clang-format on