scc update: scv4tlm -> scv

.clang-format

@@ -1,3 +1,4 @@
+---
 Language:        Cpp
 # BasedOnStyle:  LLVM
 # should be in line with IndentWidth
@@ -12,8 +13,8 @@ AllowAllParametersOfDeclarationOnNextLine: true
 AllowShortBlocksOnASingleLine: false
 AllowShortCaseLabelsOnASingleLine: false
 AllowShortFunctionsOnASingleLine: All
-AllowShortIfStatementsOnASingleLine: false
+AllowShortIfStatementsOnASingleLine: true
-AllowShortLoopsOnASingleLine: false
+AllowShortLoopsOnASingleLine: true
 AlwaysBreakAfterDefinitionReturnType: None
 AlwaysBreakAfterReturnType: None
 AlwaysBreakBeforeMultilineStrings: false
@@ -38,8 +39,8 @@ BreakBeforeTernaryOperators: true
 BreakConstructorInitializersBeforeComma: true
 BreakAfterJavaFieldAnnotations: false
 BreakStringLiterals: true
-ColumnLimit:     140
+ColumnLimit:     120
-CommentPragmas:  '^( IWYU pragma:| @suppress)'
+CommentPragmas:  '^ IWYU pragma:'
 ConstructorInitializerAllOnOneLineOrOnePerLine: false
 ConstructorInitializerIndentWidth: 0
 ContinuationIndentWidth: 4
@@ -75,13 +76,13 @@ PenaltyBreakFirstLessLess: 120
 PenaltyBreakString: 1000
 PenaltyExcessCharacter: 1000000
 PenaltyReturnTypeOnItsOwnLine: 60
-PointerAlignment: Left
+PointerAlignment: Right
 ReflowComments:  true
 SortIncludes:    true
 SpaceAfterCStyleCast: false
 SpaceAfterTemplateKeyword: true
 SpaceBeforeAssignmentOperators: true
-SpaceBeforeParens: Never
+SpaceBeforeParens: ControlStatements
 SpaceInEmptyParentheses: false
 SpacesBeforeTrailingComments: 1
 SpacesInAngles:  false

.gitignore

@@ -1,6 +1,5 @@
 .DS_Store
 /*.il
-/.settings
 /avr-instr.html
 /blink.S
 /flash.*
@@ -15,6 +14,7 @@
 /*.ods
 /build*/
 /*.logs
+language.settings.xml
 /*.gtkw
 /Debug wo LLVM/
 /*.txdb
@@ -30,5 +30,4 @@
 /.gdbinit
 /*.out
 /dump.json
-/*.yaml
+/src-gen/
-/*.json

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "gen_input/CoreDSL-Instruction-Set-Description"]
+	path = gen_input/CoreDSL-Instruction-Set-Description
+	url = ../CoreDSL-Instruction-Set-Description.git

.project

@@ -23,5 +23,6 @@
 		<nature>org.eclipse.cdt.core.ccnature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.linuxtools.tmf.project.nature</nature>
 	</natures>
 </projectDescription>

.settings/org.eclipse.cdt.codan.core.prefs

@@ -0,0 +1,73 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.codan.checkers.errnoreturn=Warning
+org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false}
+org.eclipse.cdt.codan.checkers.errreturnvalue=Error
+org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"}
+org.eclipse.cdt.codan.checkers.nocommentinside=-Error
+org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"}
+org.eclipse.cdt.codan.checkers.nolinecomment=-Error
+org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"}
+org.eclipse.cdt.codan.checkers.noreturn=Error
+org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false}
+org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error
+org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"}
+org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error
+org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"}
+org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"}
+org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error
+org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"}
+org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false}
+org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning
+org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error
+org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"}
+org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning
+org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true}
+org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem=Error
+org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"}
+org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error
+org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"}
+org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error
+org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"}
+org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error
+org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"}
+org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error
+org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"}
+org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info
+org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"}
+org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error
+org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"}
+org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error
+org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"}
+org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"}
+org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"}
+org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"}
+org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false}
+org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false}
+org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")}
+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"}

.settings/org.eclipse.cdt.core.prefs

@@ -0,0 +1,13 @@
+eclipse.preferences.version=1
+environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/append=true
+environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/appendContributed=true
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LLVM_HOME/delimiter=\:
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LLVM_HOME/operation=append
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LLVM_HOME/value=/usr/lib/llvm-6.0
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/append=true
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/appendContributed=true
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/delimiter=\:
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/operation=append
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/value=/usr/lib/llvm-6.0
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true

.settings/org.eclipse.cdt.managedbuilder.core.prefs

@@ -0,0 +1,37 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPLUS_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/CPLUS_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/C_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/append=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.debug.1751741082/appendContributed=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPLUS_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/CPLUS_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/C_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/append=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/appendContributed=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPLUS_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/CPLUS_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/C_INCLUDE_PATH/delimiter=\:
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/LIBRARY_PATH/delimiter=\:
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/append=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.debug.1751741082/appendContributed=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LIBRARY_PATH/delimiter=\:
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/append=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171.1259602404/appendContributed=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/LIBRARY_PATH/delimiter=\:
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true

CMakeLists.txt

@@ -1,270 +1,123 @@
-cmake_minimum_required(VERSION 3.18)
+cmake_minimum_required(VERSION 3.12)
-list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake)
 
-# ##############################################################################
+project("riscv" VERSION 1.0.0)
-#
-# ##############################################################################
-project(dbt-rise-tgc VERSION 1.0.0)
 
 include(GNUInstallDirs)
-include(flink)
 
-find_package(elfio QUIET)
+conan_basic_setup()
-find_package(jsoncpp)
+
-find_package(Boost COMPONENTS coroutine REQUIRED)
+find_package(Boost COMPONENTS program_options system thread filesystem REQUIRED)
+if(WITH_LLVM)
+	if(DEFINED ENV{LLVM_HOME})
+		find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
+	endif(DEFINED ENV{LLVM_HOME})
+	find_package(LLVM REQUIRED CONFIG)
+	message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
+	message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
+	llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
+endif()
+
+#Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH)
+#set(CMAKE_MACOSX_RPATH ON)
+#set(CMAKE_SKIP_BUILD_RPATH FALSE)
+#set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE)
+#set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib")
+#set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE)
 
 add_subdirectory(softfloat)
 
-set(LIB_SOURCES
-    src/iss/plugin/instruction_count.cpp
-    src/iss/arch/tgc5c.cpp
-    src/vm/interp/vm_tgc5c.cpp
-    src/vm/fp_functions.cpp
-    src/iss/debugger/csr_names.cpp
-    src/iss/semihosting/semihosting.cpp
-)
-
-if(WITH_TCC)
-    list(APPEND LIB_SOURCES
-        src/vm/tcc/vm_tgc5c.cpp
-    )
-endif()
-
-if(WITH_LLVM)
-    list(APPEND LIB_SOURCES
-        src/vm/llvm/vm_tgc5c.cpp
-        src/vm/llvm/fp_impl.cpp
-    )
-endif()
-
-if(WITH_ASMJIT)
-    list(APPEND LIB_SOURCES
-        src/vm/asmjit/vm_tgc5c.cpp
-    )
-endif()
-
 # library files
-FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
+FILE(GLOB RiscVSCHeaders ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*.h ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*/*.h)
-FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
+set(LIB_HEADERS ${RiscVSCHeaders} )
-FILE(GLOB GEN_YAML_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/contrib/instr/*.yaml)
+set(LIB_SOURCES 
-list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
+	src/iss/tgf_b.cpp
-
+	src/iss/tgf_c.cpp
-foreach(FILEPATH ${GEN_ISS_SOURCES})
+	src/vm/fp_functions.cpp
-    get_filename_component(CORE ${FILEPATH} NAME_WE)
+	src/vm/tcc/vm_tgf_b.cpp
-    string(TOUPPER ${CORE} CORE)
+	src/vm/tcc/vm_tgf_c.cpp
-    list(APPEND LIB_DEFINES CORE_${CORE})
+	src/vm/interp/vm_tgf_b.cpp
-endforeach()
+	src/vm/interp/vm_tgf_c.cpp
-
+    src/plugin/instruction_count.cpp
-message(STATUS "Core defines are ${LIB_DEFINES}")
+    src/plugin/cycle_estimate.cpp
-
+)
 if(WITH_LLVM)
-    FILE(GLOB LLVM_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp)
+set(LIB_SOURCES ${LIB_SOURCES}
-    list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
+	src/vm/llvm/fp_impl.cpp
-endif()
+	src/vm/llvm/vm_tgf_b.cpp
-
+	src/vm/llvm/vm_tgf_c.cpp
-if(WITH_TCC)
+)
-    FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/tcc/vm_*.cpp)
-    list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
-endif()
-
-if(WITH_ASMJIT)
-    FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/asmjit/vm_*.cpp)
-    list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
-endif()
-
-if(TARGET yaml-cpp::yaml-cpp)
-    list(APPEND LIB_SOURCES
-        src/iss/plugin/cycle_estimate.cpp
-        src/iss/plugin/instruction_count.cpp
-    )
 endif()
 
 # Define the library
-add_library(${PROJECT_NAME} SHARED ${LIB_SOURCES})
+add_library(riscv SHARED ${LIB_SOURCES})
+target_compile_options(riscv PRIVATE -Wno-shift-count-overflow)
+target_include_directories(riscv PUBLIC incl ../external/elfio)
+target_link_libraries(riscv PUBLIC softfloat scc-util jsoncpp)
+target_link_libraries(riscv PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
+set_target_properties(riscv PROPERTIES
+  VERSION ${PROJECT_VERSION}
+  FRAMEWORK FALSE
+  PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
+)
 
-if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
+if(SystemC_FOUND)
-    target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
+	add_library(riscv_sc src/sysc/core_complex.cpp)
-elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
+	target_compile_definitions(riscv_sc PUBLIC WITH_SYSTEMC) 
-    target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
+	target_include_directories(riscv_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
-endif()
+	
-
+	if(SCV_FOUND)   
-target_include_directories(${PROJECT_NAME} PUBLIC src)
+	    target_compile_definitions(riscv_sc PUBLIC WITH_SCV)
-target_include_directories(${PROJECT_NAME} PUBLIC src-gen)
+	    target_include_directories(riscv_sc PUBLIC ${SCV_INCLUDE_DIRS})
-
+	endif()
-target_force_link_libraries(${PROJECT_NAME} PRIVATE dbt-rise-core)
+	target_link_libraries(riscv_sc PUBLIC riscv scc )
-
+	if(WITH_LLVM)
-# only re-export the include paths
+		target_link_libraries(riscv_sc PUBLIC ${llvm_libs})
-get_target_property(DBT_CORE_INCL dbt-rise-core INTERFACE_INCLUDE_DIRECTORIES)
+	endif()
-target_include_directories(${PROJECT_NAME} INTERFACE ${DBT_CORE_INCL})
+	target_link_libraries(riscv_sc PUBLIC ${Boost_LIBRARIES} )
-get_target_property(DBT_CORE_DEFS dbt-rise-core INTERFACE_COMPILE_DEFINITIONS)
+	set_target_properties(riscv_sc PROPERTIES
-
+	  VERSION ${PROJECT_VERSION}
-if(NOT(DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND))
+	  FRAMEWORK FALSE
-    target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
+	  PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
-endif()
+	)
-
-target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine)
-
-if(TARGET yaml-cpp::yaml-cpp)
-    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS)
-    target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp)
 endif()
 
+project("riscv-sim")
+add_executable(riscv-sim src/main.cpp)
+# This sets the include directory for the reference project. This is the -I flag in gcc.
+target_include_directories(riscv-sim PRIVATE ../external/libGIS)
 if(WITH_LLVM)
-    find_package(LLVM)
+	target_compile_definitions(riscv-sim PRIVATE WITH_LLVM)
-    target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS})
+	target_link_libraries(riscv-sim PUBLIC ${llvm_libs})
-    target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS})
-
-    if(BUILD_SHARED_LIBS)
-        target_link_libraries(${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES})
-    endif()
 endif()
-
+# Links the target exe against the libraries
-set_target_properties(${PROJECT_NAME} PROPERTIES
+target_link_libraries(riscv-sim riscv)
-    VERSION ${PROJECT_VERSION}
+target_link_libraries(riscv-sim jsoncpp)
-    FRAMEWORK FALSE
+target_link_libraries(riscv-sim external)
-)
+target_link_libraries(riscv-sim ${Boost_LIBRARIES} )
-install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
+if (Tcmalloc_FOUND)
-    EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
+    target_link_libraries(riscv-sim ${Tcmalloc_LIBRARIES})
-    ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib
-    RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries
-    LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib
-    FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
-    PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
-    INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
-)
-install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss COMPONENT ${PROJECT_NAME}
-    DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # target directory
-    FILES_MATCHING # install only matched files
-    PATTERN "*.h" # select header files
-)
-install(FILES ${GEN_YAML_SOURCES} DESTINATION share/tgc-vp)
-
-# ##############################################################################
-#
-# ##############################################################################
-set(CMAKE_INSTALL_RPATH $ORIGIN/../${CMAKE_INSTALL_LIBDIR})
-project(tgc-sim)
-find_package(Boost COMPONENTS program_options thread REQUIRED)
-
-add_executable(${PROJECT_NAME} src/main.cpp)
-
-if(TARGET ${CORE_NAME}_cpp)
-    list(APPEND TGC_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
-else()
-    FILE(GLOB TGC_SOURCES
-        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp
-        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp
-    )
-    list(APPEND TGC_SOURCES ${GEN_SOURCES})
-endif()
-
-foreach(F IN LISTS TGC_SOURCES)
-    if(${F} MATCHES ".*/arch/([^/]*)\.cpp")
-        string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
-        string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-    endif()
-endforeach()
-
-# if(WITH_LLVM)
-# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
-# #target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
-# endif()
-# if(WITH_TCC)
-# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
-# endif()
-target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc fmt::fmt)
-
-if(TARGET Boost::program_options)
-    target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options)
-else()
-    target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY})
-endif()
-
-target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS})
-
-if(Tcmalloc_FOUND)
-    target_link_libraries(${PROJECT_NAME} PUBLIC ${Tcmalloc_LIBRARIES})
 endif(Tcmalloc_FOUND)
 
-install(TARGETS tgc-sim
+install(TARGETS riscv riscv-sim
-    EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
+  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
-    ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # static lib
-    RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries
+  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} COMPONENT libs   # binaries
-    LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib
+  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # shared lib
-    FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac
-    PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
+  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} COMPONENT devel   # headers for mac (note the different component -> different package)
-    INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
+  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
 )
 
-if(BUILD_TESTING)
-    # ... CMake code to create tests ...
-    add_test(NAME tgc-sim-interp
-        COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend interp)
 
-    if(WITH_TCC)
-        add_test(NAME tgc-sim-tcc
-            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend tcc)
-    endif()
 
-    if(WITH_LLVM)
-        add_test(NAME tgc-sim-llvm
-            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend llvm)
-    endif()
-
-    if(WITH_ASMJIT)
-        add_test(NAME tgc-sim-asmjit
-            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend asmjit)
-    endif()
-endif()
-
-# ##############################################################################
 #
-# ##############################################################################
+# SYSTEM PACKAGING (RPM, TGZ, ...)
-if(TARGET scc-sysc)
+# _____________________________________________________________________________
-    project(dbt-rise-tgc_sc VERSION 1.0.0)
-    set(LIB_SOURCES
-        src/sysc/core_complex.cpp
-        src/sysc/register_tgc_c.cpp
-    )
-    FILE(GLOB GEN_SC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/sysc/register_*.cpp)
-    list(APPEND LIB_SOURCES ${GEN_SC_SOURCES})
-    add_library(${PROJECT_NAME} ${LIB_SOURCES})
-    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
-    target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
 
-    foreach(F IN LISTS TGC_SOURCES)
+#include(CPackConfig)
-        if(${F} MATCHES ".*/arch/([^/]*)\.cpp")
-            string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
-            string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
-            target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-        endif()
-    endforeach()
 
-    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
+#
+# CMAKE PACKAGING (for other CMake projects to use this one easily)
+# _____________________________________________________________________________
 
-    # if(WITH_LLVM)
+#include(PackageConfigurator)
-    # target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
-    # endif()
-    set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
-    set_target_properties(${PROJECT_NAME} PROPERTIES
-        VERSION ${PROJECT_VERSION}
-        FRAMEWORK FALSE
-        PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
-    )
-    install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
-        EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
-        ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib
-        RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries
-        LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib
-        FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
-        PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc # headers for mac (note the different component -> different package)
-        INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
-    )
-endif()
-
-project(elfio-test)
-find_package(Boost COMPONENTS program_options thread REQUIRED)
-
-add_executable(${PROJECT_NAME} src/elfio.cpp)
-target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)

cmake/flink.cmake

@@ -1,35 +0,0 @@
-# according to https://github.com/horance-liu/flink.cmake/tree/master
-# SPDX-License-Identifier: Apache-2.0
-
-include(CMakeParseArguments)
-
-function(target_do_force_link_libraries target visibility lib)
-  if(MSVC)
-    target_link_libraries(${target} ${visibility} "/WHOLEARCHIVE:${lib}")
-  elseif(APPLE)
-    target_link_libraries(${target} ${visibility} -Wl,-force_load ${lib})
-  else()
-    target_link_libraries(${target} ${visibility} -Wl,--whole-archive ${lib} -Wl,--no-whole-archive)
-  endif()
-endfunction()
-
-function(target_force_link_libraries target)
-  cmake_parse_arguments(FLINK
-    ""
-    ""
-    "PUBLIC;INTERFACE;PRIVATE"
-    ${ARGN}
-  )
-  
-  foreach(lib IN LISTS FLINK_PUBLIC)
-    target_do_force_link_libraries(${target} PUBLIC ${lib})
-  endforeach()
-
-  foreach(lib IN LISTS FLINK_INTERFACE)
-    target_do_force_link_libraries(${target} INTERFACE ${lib})
-  endforeach()
-  
-  foreach(lib IN LISTS FLINK_PRIVATE)
-    target_do_force_link_libraries(${target} PRIVATE ${lib})
-  endforeach()
-endfunction()

contrib/instr/.gitignore

@@ -1 +0,0 @@
-/*.yaml

contrib/instr/TGC5C_instr.yaml

@@ -1,624 +0,0 @@
-
-RVI: 
-  LUI:
-    index: 0
-    encoding: 0b00000000000000000000000000110111
-    mask: 0b00000000000000000000000001111111
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-    mask: 0b00000000000000000000000001111111
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-    branch:   false
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-    mask: 61567
-    size: 16
-  __reserved_cmv:
-    branch: false
-    delay: 1
-    encoding: 32770
-    index: 81
-    mask: 65535
-    size: 16
-Zicsr:
-  CSRRC:
-    branch: false
-    delay: 1
-    encoding: 12403
-    index: 44
-    mask: 28799
-    size: 32
-  CSRRCI:
-    branch: false
-    delay: 1
-    encoding: 28787
-    index: 47
-    mask: 28799
-    size: 32
-  CSRRS:
-    branch: false
-    delay: 1
-    encoding: 8307
-    index: 43
-    mask: 28799
-    size: 32
-  CSRRSI:
-    branch: false
-    delay: 1
-    encoding: 24691
-    index: 46
-    mask: 28799
-    size: 32
-  CSRRW:
-    branch: false
-    delay: 1
-    encoding: 4211
-    index: 42
-    mask: 28799
-    size: 32
-  CSRRWI:
-    branch: false
-    delay: 1
-    encoding: 20595
-    index: 45
-    mask: 28799
-    size: 32
-Zifencei:
-  FENCE_I:
-    attributes:
-    - - name:flush
-    branch: false
-    delay: 1
-    encoding: 4111
-    index: 48
-    mask: 28799
-    size: 32

contrib/pa/.gitignore

@@ -1,3 +0,0 @@
-/results
-/cwr
-/*.xml

contrib/pa/README.md

@@ -1,43 +0,0 @@
-# Notes
-
-* requires conan version 1.59
-* requires decent cmake version 3.23
-
-Setup for tcsh:
-
-```
-git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
-cd TGC-ISS/
-setenv TGFS_INSTALL_ROOT `pwd`/install
-setenv COWAREHOME <your SNPS PA installation>
-setenv SNPSLMD_LICENSE_FILE <your SNPS PA license file>
-source $COWAREHOME/SLS/linux/setup.csh pae
-setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
-setenv PATH $COWAREHOME/common/bin/:${PATH}
-setenv CC  $COWAREHOME/SLS/linux/common/bin/gcc
-setenv CXX $COWAREHOME/SLS/linux/common/bin/g++
-cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
-    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
-cmake --build build/PA --target install -j16
-cd dbt-rise-tgc/contrib/pa
-# import the TGC core itself
-pct tgc_import_tb.tcl
-```
-
-Setup for bash:
-
-```
-git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
-cd TGC-ISS/
-export TGFS_INSTALL_ROOT `pwd`/install
-module load tools/pa/T-2022.06
-export SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM=1
-export CC=$COWAREHOME/SLS/linux/common/bin/gcc
-export CXX=$COWAREHOME/SLS/linux/common/bin/g++
-cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
-    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
-cmake --build build/PA --target install -j16
-cd dbt-rise-tgc/contrib/pa
-# import the TGC core itself
-pct tgc_import_tb.tcl
-```

contrib/pa/build.tcl

@@ -1,30 +0,0 @@
-namespace eval Specification {
-    proc buildproc { args } {
-        global env
-        variable installDir
-        variable compiler
-        variable compiler [::scsh::get_backend_compiler]
-        #  set target $machine
-        set target [::scsh::machine]
-        set linkerOptions ""
-        set preprocessorOptions ""
-        set libversion $compiler
-        switch -exact -- $target {
-            "linux" {
-            	set install_dir $::env(TGFS_INSTALL_ROOT)
-                set incldir "${install_dir}/include"
-                set libdir "${install_dir}/lib64"
-                set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
-                # Set the Linker paths.
-                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc -lscc-sysc"]
-            }
-            default {
-               puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"
-               return
-            }
-        }
-        ::scsh::cwr_append_ipsimbld_opts preprocessor "$preprocessorOptions"
-        ::scsh::cwr_append_ipsimbld_opts linker       "$linkerOptions"
-    }
-    ::scsh::add_build_callback [namespace current]::buildproc
-}

contrib/pa/tgc_import.cc

@@ -1,4 +0,0 @@
-
-#include "sysc/core_complex.h"
-
-void modules() { sysc::tgfs::core_complex i_core_complex("core_complex"); }

contrib/pa/tgc_import.tcl

@@ -1,50 +0,0 @@
-#############################################################################
-#
-#############################################################################
-proc getScriptDirectory {} {
-    set dispScriptFile [file normalize [info script]]
-    set scriptFolder [file dirname $dispScriptFile]
-    return $scriptFolder
-}
-    set hardware /HARDWARE/HW/HW
-
-set scriptDir [getScriptDirectory]
-set top_design_name core_complex
-set encap_name sysc::tgfs::${top_design_name}
-set clocks clk_i
-set resets rst_i
-set model_prefix "i_"
-set model_postfix ""
-
-::pct::new_project
-::pct::open_library TLM2_PL
-::pct::clear_systemc_defines
-::pct::clear_systemc_include_path
-::pct::add_to_systemc_include_path $::env(TGFS_INSTALL_ROOT)/include
-::pct::set_import_protocol_generation_flag false
-::pct::set_update_existing_encaps_flag true
-::pct::set_dynamic_port_arrays_flag true
-::pct::set_import_scml_properties_flag true
-::pct::set_import_encap_prop_as_extra_prop_flag true
-::pct::load_modules --set-category modules ${scriptDir}/tgc_import.cc
-
-# Set Port Protocols correctly
-set block ${top_design_name}
-foreach clock ${clocks} {
-	::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${clock} SYSTEM_LIBRARY:CLOCK
-}
-foreach reset ${resets} {
-    ::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
-}
-#::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
-
-# Set compile settings and look
-set block SYSTEM_LIBRARY:${top_design_name}
-::pct::set_encap_build_script $block/${encap_name} $scriptDir/build.tcl
-::pct::set_background_color_rgb $block 255 255 255 255
-::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${encap_name} ${encap_name}() 
-::pct::set_bounds i_${top_design_name} 200 300 100 400
-::pct::set_image i_${top_design_name} "$scriptDir/minres.png" center center false true
-
-# export the result as component
-::pct::export_system_library ${top_design_name}  ${top_design_name}.xml

contrib/pa/tgc_import_tb.tcl

@@ -1,71 +0,0 @@
-source tgc_import.tcl
-set hardware /HARDWARE/HW/HW
-set FW_name ${scriptDir}/hello.elf
-
-puts "instantiate testbench elements"
-::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
-::pct::set_param_value i_Memory_Generic/MEM:protocol {Protocol Common Parameters} address_width 30
-::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/LT/clock_period_in_ns 1
-::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/read/cmd_accept_cycles 1
-::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/write/cmd_accept_cycles 1
-::pct::set_bounds i_Memory_Generic 1000 300 100 100
-
-::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
-::BLWizard::generateFramework i_Bus SBLTLM2FT  * {} \
-						{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
-::pct::set_bounds i_Bus 700 300 100 400
-::pct::create_connection C_ibus i_core_complex/ibus i_Bus/i_core_complex_ibus
-::pct::set_location_on_owner i_Bus/i_core_complex_ibus 10
-::pct::create_connection C_dbus i_core_complex/dbus i_Bus/i_core_complex_dbus
-::pct::set_location_on_owner i_Bus/i_core_complex_dbus 10
-::pct::create_connection C_mem i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
-
-puts "instantiating clock manager"
-set clock "Clk"
-::hw::create_hw_instance "" GenericIPlib:ClockGenerator ${clock}_clock
-::pct::set_bounds ${clock}_clock 100 100 100 100
-::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period 1000
-::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period_unit sc_core::SC_PS
-
-puts "instantiating reset manager"
-set reset "Rst"
- ::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset
- ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 0
- ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
- ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
- ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS
- ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
-::pct::set_bounds ${reset}_reset 300 100 100 100
-
-puts "connecting reset/clock"
-::pct::create_connection C_clk . Clk_clock/CLK i_core_complex/clk_i
-::pct::add_ports_to_connection C_clk i_Bus/Clk
-::pct::add_ports_to_connection C_clk i_Memory_Generic/CLK
-::pct::create_connection C_rst . Rst_reset/RST i_core_complex/rst_i
-::pct::add_ports_to_connection C_rst i_Bus/Rst
-
-puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
-::pct::set_param_value $hardware/i_${top_design_name} {Extra properties} elf_file ${FW_name}
-::pct::set_address $hardware/i_${top_design_name}/ibus:i_Memory_Generic/MEM 0x0
-::pct::set_address $hardware/i_${top_design_name}/dbus:i_Memory_Generic/MEM 0x0
-::BLWizard::updateFramework i_Bus {} { common_configuration:BackBone:/advanced/num_resources_per_target:1 }
-
-::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
-::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
-::pct::create_simulation_build_config Debug
-::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
-# add build settings and save design for next steps
-#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
-#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
-
-#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
-#::simulation::run_simulation Simulation
-
-#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
-#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
-#::pct::export_system "export"
-#::cd "export"
-#::scsh::open-project
-#::scsh::build
-#::scsh::elab sim
-::pct::save_system testbench.xml

gen_input/.gitignore

@@ -1,2 +1 @@
 /src-gen/
-/CoreDSL-Instruction-Set-Description

gen_input/TGC5C.core_desc

@@ -1,13 +0,0 @@
-import "ISA/RVI.core_desc"
-import "ISA/RVM.core_desc"
-import "ISA/RVC.core_desc"
-
-Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
-    architectural_state {
-        XLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned int MISA_VAL = 0b01000000000000000001000100000100;
-        unsigned int MARCHID_VAL = 0x80000003;
-    }
-}

gen_input/TGFS.core_desc

@@ -0,0 +1,28 @@
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
+
+Core TGF_B provides RV32I {
+	constants {
+        XLEN:=32;
+        PCLEN:=32;
+        // definitions for the architecture wrapper
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        MISA_VAL:=0b01000000000000000000000100000000;
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
+	}
+}
+
+Core TGF_C provides RV32I, RV32M, RV32IC {
+    constants {
+        XLEN:=32;
+        PCLEN:=32;
+        MUL_LEN:=64;
+        // definitions for the architecture wrapper
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        MISA_VAL:=0b01000000000000000001000100000100;
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
+    }
+}

gen_input/minres_rv.core_desc

@@ -0,0 +1,74 @@
+import "RV32I.core_desc"
+import "RV64I.core_desc"
+import "RVM.core_desc"
+import "RVA.core_desc"
+import "RVC.core_desc"
+import "RVF.core_desc"
+import "RVD.core_desc"
+
+
+Core MNRV32 provides RV32I, RV32IC {
+    constants {
+        XLEN:=32;
+        PCLEN:=32;
+        // definitions for the architecture wrapper
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        MISA_VAL:=0b01000000000101000001000100000101;
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
+    }
+}
+
+Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
+    constants {
+        XLEN:=32;
+        PCLEN:=32;
+        MUL_LEN:=64;
+        // definitions for the architecture wrapper
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        MISA_VAL:=0b01000000000101000001000100000101;
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
+    }
+}
+
+Core RV32GC provides RV32I, RV32M, RV32A, RV32F, RV32D, RV32IC, RV32FC, RV32DC {
+    constants {
+        XLEN:=32;
+        FLEN:=64;
+        PCLEN:=32;
+        MUL_LEN:=64;
+        // definitions for the architecture wrapper
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        MISA_VAL:=0b01000000000101000001000100101101;
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
+    }
+}
+
+Core RV64I provides RV64I {
+    constants {
+        XLEN:=64;
+        PCLEN:=64;
+        // definitions for the architecture wrapper
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        MISA_VAL:=0b10000000000001000000000100000000;
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
+    }
+}
+
+Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV32FC, RV32DC, RV64IC {
+    constants {
+        XLEN:=64;
+        FLEN:=64;
+        PCLEN:=64;
+        MUL_LEN:=128;
+        // definitions for the architecture wrapper
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        MISA_VAL:=0b01000000000101000001000100101101;
+        PGSIZE := 0x1000; //1 << 12;
+        PGMASK := 0xfff; //PGSIZE-1
+    }
+}
+

gen_input/templates/CORENAME.h.gtl

@@ -1,177 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2024 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-<%
-def nativeTypeSize(int size){
-    if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
-}
-def getRegisterSizes(){
-    def regs = registers.collect{nativeTypeSize(it.size)}
-    regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
-    return regs
-}
-def getRegisterOffsets(){
-    def offset = 0
-    def offsets = []
-    getRegisterSizes().each { size ->
-        offsets<<offset
-        offset+=size/8
-    }
-    return offsets
-}
-def byteSize(int size){
-    if(size<=8) return 8;
-    if(size<=16) return 16;
-    if(size<=32) return 32;
-    if(size<=64) return 64;
-    return 128;
-}
-def getCString(def val){
-    return val.toString()+'ULL'
-}
-%>
-#ifndef _${coreDef.name.toUpperCase()}_H_
-#define _${coreDef.name.toUpperCase()}_H_
-// clang-format off
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct ${coreDef.name.toLowerCase()};
-
-template <> struct traits<${coreDef.name.toLowerCase()}> {
-
-    constexpr static char const* const core_type = "${coreDef.name}";
-    
-    static constexpr std::array<const char*, ${registers.size()}> reg_names{
-        {"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
- 
-    static constexpr std::array<const char*, ${registers.size()}> reg_aliases{
-        {"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};
-
-    enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
-
-    constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
-
-    enum reg_e {
-        ${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
-    };
-
-    using reg_t = uint${addrDataWidth}_t;
-
-    using addr_t = uint${addrDataWidth}_t;
-
-    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
-    static constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> reg_bit_widths{
-        {${getRegisterSizes().join(',')}}};
-
-    static constexpr std::array<const uint32_t, ${getRegisterOffsets().size()}> reg_byte_offsets{
-        {${getRegisterOffsets().join(',')}}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { ${spaces.collect{it.name}.join(', ')}, IMEM = MEM };
-    
-    enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
-        ${instr.instruction.name} = ${index},<%}%>
-        MAX_OPCODE
-    };
-};
-
-struct ${coreDef.name.toLowerCase()}: public arch_if {
-
-    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
-    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
-    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
-    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
-
-    ${coreDef.name.toLowerCase()}();
-    ~${coreDef.name.toLowerCase()}();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-
-#pragma pack(push, 1)
-    struct ${coreDef.name}_regs {<%
-        registers.each { reg -> if(reg.size>0) {%> 
-        uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
-        }}%>
-        uint32_t trap_state = 0, pending_trap = 0;
-        uint64_t icount = 0;
-        uint64_t cycle = 0;
-        uint64_t instret = 0;
-        uint32_t instruction = 0;
-        uint32_t last_branch = 0;
-    } reg;
-#pragma pack(pop)
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-<%
-def fcsr = registers.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-    uint${fcsr.size}_t get_fcsr(){return reg.FCSR;}
-    void set_fcsr(uint${fcsr.size}_t val){reg.FCSR = val;}      
-<%} else { %>
-    uint32_t get_fcsr(){return 0;}
-    void set_fcsr(uint32_t val){}
-<%}%>
-};
-
-}
-}            
-#endif /* _${coreDef.name.toUpperCase()}_H_ */
-// clang-format on

gen_input/templates/CORENAME_cyles.txt.gtl

@@ -1,12 +0,0 @@
-{
-	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
-		{
-			"name"  :   "${instr.name}",
-			"size"  :   ${instr.length},
-			"encoding": "${instr.encoding}",
-            "mask":     "${instr.mask}",
-			"branch":   ${instr.modifiesPC},
-			"delay" :   ${instr.isConditional?"[1,1]":"1"}
-		}<%}%>
-	]
-}

gen_input/templates/CORENAME_instr.yaml.gtl

@@ -1,21 +0,0 @@
-<% def getInstructionGroups() {
-    def instrGroups = [:]
-    instructions.each {
-        def groupName = it['instruction'].eContainer().name
-        if(!instrGroups.containsKey(groupName)) {
-            instrGroups[groupName]=[]
-        }
-        instrGroups[groupName]+=it;
-    }
-    instrGroups
-}%><%int index = 0; getInstructionGroups().each{name, instrList -> %>
-${name}: <% instrList.each { %>
-  ${it.instruction.name}:
-    index: ${index++}
-    encoding: ${it.encoding}
-    mask: ${it.mask}<%if(it.attributes.size) {%>
-    attributes: ${it.attributes}<%}%>
-    size:   ${it.length}
-    branch:   ${it.modifiesPC}
-    delay:   ${it.isConditional?"[1,1]":"1"}<%}}%>
-

gen_input/templates/CORENAME_sysc.cpp.gtl

@@ -1,131 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2024 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-// clang-format off
-#include <sysc/iss_factory.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-#include <sysc/sc_core_adapter.h>
-#include <sysc/core_complex.h>
-#include <array>
-<%
-def array_count = coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e"? 3 : 2;
-%>
-namespace iss {
-namespace interp {
-using namespace sysc;
-volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        }),
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%}%>
-};
-}
-#if defined(WITH_LLVM)
-namespace llvm {
-using namespace sysc;
-volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        }),
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%}%>
-};
-}
-#endif
-#if defined(WITH_TCC)
-namespace tcc {
-using namespace sysc;
-volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        }),
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%}%>
-};
-}
-#endif
-#if defined(WITH_ASMJIT)
-namespace asmjit {
-using namespace sysc;
-volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        }),
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
-        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
-        })<%}%>
-};
-}
-#endif
-}
-// clang-format on

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -1,369 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017-2024 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-// clang-format off
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/server.h>
-#include <iss/iss.h>
-#include <iss/asmjit/vm_base.h>
-#include <asmjit/asmjit.h>
-#include <util/logging.h>
-#include <iss/instruction_decoder.h>
-<%def fcsr = registers.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-#include <vm/fp_functions.h><%}%>
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <fmt/format.h>
-
-#include <array>
-#include <iss/debugger/riscv_target_adapter.h>
-
-namespace iss {
-namespace asmjit {
-
-
-namespace ${coreDef.name.toLowerCase()} {
-using namespace ::asmjit;
-using namespace iss::arch;
-using namespace iss::debugger;
-
-template <typename ARCH> class vm_impl : public iss::asmjit::vm_base<ARCH> {
-public:
-    using traits = arch::traits<ARCH>;
-    using super = typename iss::asmjit::vm_base<ARCH>;
-    using virt_addr_t = typename super::virt_addr_t;
-    using phys_addr_t = typename super::phys_addr_t;
-    using code_word_t = typename super::code_word_t;
-    using mem_type_e = typename super::mem_type_e;
-    using addr_t = typename super::addr_t;
-
-    vm_impl();
-
-    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
-
-    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
-
-    target_adapter_if *accquire_target_adapter(server_if *srv) override {
-        debugger_if::dbg_enabled = true;
-        if (vm_base<ARCH>::tgt_adapter == nullptr)
-            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
-        return vm_base<ARCH>::tgt_adapter;
-    }
-
-protected:
-    using super::get_ptr_for;
-    using super::get_reg_for;
-    using super::get_reg_for_Gp;
-    using super::load_reg_from_mem;
-    using super::load_reg_from_mem_Gp;
-    using super::write_reg_to_mem;
-    using super::gen_read_mem;
-    using super::gen_write_mem;
-    using super::gen_leave;
-    using super::gen_sync;
-   
-    using this_class = vm_impl<ARCH>;
-    using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
-
-    continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
-    enum globals_e {TVAL = 0, GLOBALS_SIZE};
-    void gen_block_prologue(jit_holder& jh) override;
-    void gen_block_epilogue(jit_holder& jh) override;
-    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
-<%if(fcsr != null) {%>
-    inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}   
-<%}%>
-    void gen_instr_prologue(jit_holder& jh);
-    void gen_instr_epilogue(jit_holder& jh);
-    inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause);
-    template <typename T, typename = typename std::enable_if<std::is_integral<T>::value>::type> void gen_set_tval(jit_holder& jh, T new_tval) ;
-    void gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) ;
-
-    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
-    inline S sext(U from) {
-        auto mask = (1ULL<<W) - 1;
-        auto sign_mask = 1ULL<<(W-1);
-        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
-    }
-<%functions.each{ it.eachLine { %>
-    ${it}<%}%>
-<%}%>
-private:
-    /****************************************************************************
-     * start opcode definitions
-     ****************************************************************************/
-    struct instruction_descriptor {
-        uint32_t length;
-        uint32_t value;
-        uint32_t mask;
-        compile_func op;
-    };
-
-    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
-         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
-    }};
-
-    //needs to be declared after instr_descr
-    decoder instr_decoder;
-
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    continuation_e __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, jit_holder& jh){
-        uint64_t PC = pc.val;
-        <%instr.fields.eachLine{%>${it}
-        <%}%>if(this->disass_enabled){
-            /* generate disass */
-            <%instr.disass.eachLine{%>
-            ${it}<%}%>
-            InvokeNode* call_print_disass;
-            char* mnemonic_ptr = strdup(mnemonic.c_str());
-            jh.disass_collection.push_back(mnemonic_ptr);
-            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build<void, void *, uint64_t, char *>());
-            call_print_disass->setArg(0, jh.arch_if_ptr);
-            call_print_disass->setArg(1, pc.val);
-            call_print_disass->setArg(2, mnemonic_ptr);
-
-        }
-        x86::Compiler& cc = jh.cc;
-        cc.comment(fmt::format("${instr.name}_{:#x}:",pc.val).c_str());
-        gen_sync(jh, PRE_SYNC, ${idx});
-        mov(cc, jh.pc, pc.val);
-        gen_set_tval(jh, instr);
-        pc = pc+${instr.length/8};
-        mov(cc, jh.next_pc, pc.val);
-
-        gen_instr_prologue(jh);
-        cc.comment("//behavior:");
-        /*generate behavior*/
-        <%instr.behavior.eachLine{%>${it}
-        <%}%>
-        gen_sync(jh, POST_SYNC, ${idx});
-        gen_instr_epilogue(jh);
-    	return returnValue;        
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    continuation_e illegal_instruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
-        x86::Compiler& cc = jh.cc;
-        if(this->disass_enabled){          
-            auto mnemonic = std::string("illegal_instruction");
-            InvokeNode* call_print_disass;
-            char* mnemonic_ptr = strdup(mnemonic.c_str());
-            jh.disass_collection.push_back(mnemonic_ptr);
-            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build<void, void *, uint64_t, char *>());
-            call_print_disass->setArg(0, jh.arch_if_ptr);
-            call_print_disass->setArg(1, pc.val);
-            call_print_disass->setArg(2, mnemonic_ptr);
-        }
-        cc.comment(fmt::format("illegal_instruction{:#x}:",pc.val).c_str());
-        gen_sync(jh, PRE_SYNC, instr_descr.size());
-        mov(cc, jh.pc, pc.val);
-        gen_set_tval(jh, instr);
-        pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        mov(cc, jh.next_pc, pc.val);
-        gen_instr_prologue(jh);
-        cc.comment("//behavior:");
-        gen_raise(jh, 0, 2);
-        gen_sync(jh, POST_SYNC, instr_descr.size());
-        gen_instr_epilogue(jh);
-        return ILLEGAL_INSTR;
-    }
-};
-
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
-
-template <typename ARCH>
-vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id)
-, instr_decoder([this]() {
-        std::vector<generic_instruction_descriptor> g_instr_descr;
-        g_instr_descr.reserve(instr_descr.size());
-        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
-            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
-            g_instr_descr.push_back(new_instr_descr);
-        }
-        return std::move(g_instr_descr);
-    }()) {}
-
-template <typename ARCH>
-continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
-    enum {TRAP_ID=1<<16};
-    code_word_t instr = 0;
-    phys_addr_t paddr(pc);
-    auto *const data = (uint8_t *)&instr;
-    if(this->core.has_mmu())
-        paddr = this->core.virt2phys(pc);
-    auto res = this->core.read(paddr, 4, data);
-    if (res != iss::Ok)
-        return ILLEGAL_FETCH;
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001)
-        return JUMP_TO_SELF;
-    ++inst_cnt;
-    uint32_t inst_index = instr_decoder.decode_instr(instr);
-    compile_func f = nullptr;
-    if(inst_index < instr_descr.size())
-        f = instr_descr[inst_index].op;
-    if (f == nullptr) 
-        f = &this_class::illegal_instruction;
-    return (this->*f)(pc, instr, jh);
-}
-template <typename ARCH>
-void vm_impl<ARCH>::gen_instr_prologue(jit_holder& jh) {
-    auto& cc = jh.cc;
-
-    cc.comment("//gen_instr_prologue");
-
-    x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
-    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
-    mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state);
-
-}
-template <typename ARCH>
-void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
-    auto& cc = jh.cc;
-
-    cc.comment("//gen_instr_epilogue");
-    x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
-    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
-    cmp(cc, current_trap_state, 0);
-    cc.jne(jh.trap_entry);
-    cc.inc(get_ptr_for(jh, traits::ICOUNT));
-}
-template <typename ARCH>
-void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
-    jh.pc = load_reg_from_mem_Gp(jh, traits::PC);
-    jh.next_pc = load_reg_from_mem_Gp(jh, traits::NEXT_PC);
-    jh.globals.resize(GLOBALS_SIZE);
-    jh.globals[TVAL] = get_reg_Gp(jh.cc, 64, false);
-}
-template <typename ARCH>
-void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
-    x86::Compiler& cc = jh.cc;
-    cc.comment("//gen_block_epilogue");
-    cc.ret(jh.next_pc);
-
-    cc.bind(jh.trap_entry);
-    this->write_back(jh);
-
-    x86::Gp current_trap_state = get_reg_for_Gp(cc, traits::TRAP_STATE);
-    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
-
-    x86::Gp current_pc = get_reg_for_Gp(cc, traits::PC);
-    mov(cc, current_pc, get_ptr_for(jh, traits::PC));
-
-    cc.comment("//enter trap call;");
-    InvokeNode* call_enter_trap;
-    cc.invoke(&call_enter_trap, &enter_trap, FuncSignature::build<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
-    call_enter_trap->setArg(0, jh.arch_if_ptr);
-    call_enter_trap->setArg(1, current_trap_state);
-    call_enter_trap->setArg(2, current_pc);
-    call_enter_trap->setArg(3, jh.globals[TVAL]);
-
-    x86_reg_t current_next_pc = get_reg_for(cc, traits::NEXT_PC);
-    mov(cc, current_next_pc, get_ptr_for(jh, traits::NEXT_PC));
-    mov(cc, jh.next_pc, current_next_pc);
-
-    mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(UNKNOWN_JUMP));
-    cc.ret(jh.next_pc);
-}
-template <typename ARCH>
-inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
-    auto& cc = jh.cc;
-    cc.comment("//gen_raise");
-    auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
-    mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
-    mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);
-}
-template <typename ARCH>
-template <typename T, typename>
-void vm_impl<ARCH>::gen_set_tval(jit_holder& jh, T new_tval) {
-        mov(jh.cc, jh.globals[TVAL], new_tval);
-    }
-template <typename ARCH>
-void vm_impl<ARCH>::gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) {
-    if(nonstd::holds_alternative<x86::Gp>(_new_tval)) {
-        x86::Gp new_tval = nonstd::get<x86::Gp>(_new_tval);
-        if(new_tval.size() < 8)
-            new_tval = gen_ext_Gp(jh.cc, new_tval, 64, false);
-        mov(jh.cc, jh.globals[TVAL], new_tval);
-    } else {
-        throw std::runtime_error("Variant not supported in gen_set_tval");
-    }
-}
-
-} // namespace tgc5c
-
-template <>
-std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
-    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
-    return std::unique_ptr<vm_if>(ret);
-}
-} // namespace asmjit
-} // namespace iss
-
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-#include <iss/factory.h>
-namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        })
-};
-}
-}
-// clang-format on

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -1,367 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017-2024 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-<%
-def nativeTypeSize(int size){
-    if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
-}
-%>
-// clang-format off
-#include <cstdint>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/server.h>
-#include <iss/iss.h>
-#include <iss/interp/vm_base.h>
-#include <vm/fp_functions.h>
-#include <util/logging.h>
-#include <boost/coroutine2/all.hpp>
-#include <functional>
-#include <exception>
-#include <vector>
-#include <sstream>
-#include <iss/instruction_decoder.h>
-
-
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <fmt/format.h>
-
-#include <array>
-#include <iss/debugger/riscv_target_adapter.h>
-
-namespace iss {
-namespace interp {
-namespace ${coreDef.name.toLowerCase()} {
-using namespace iss::arch;
-using namespace iss::debugger;
-using namespace std::placeholders;
-
-struct memory_access_exception : public std::exception{
-    memory_access_exception(){}
-};
-
-template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
-public:
-    using traits = arch::traits<ARCH>;
-    using super       = typename iss::interp::vm_base<ARCH>;
-    using virt_addr_t = typename super::virt_addr_t;
-    using phys_addr_t = typename super::phys_addr_t;
-    using code_word_t = typename super::code_word_t;
-    using addr_t      = typename super::addr_t;
-    using reg_t       = typename traits::reg_t;
-    using mem_type_e  = typename traits::mem_type_e;
-    using opcode_e    = typename traits::opcode_e;
-    
-    vm_impl();
-
-    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
-
-    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
-
-    target_adapter_if *accquire_target_adapter(server_if *srv) override {
-        debugger_if::dbg_enabled = true;
-        if (super::tgt_adapter == nullptr)
-            super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
-        return super::tgt_adapter;
-    }
-
-protected:
-    using this_class = vm_impl<ARCH>;
-    using compile_ret_t = virt_addr_t;
-    using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
-
-    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
-<%
-def fcsr = registers.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-    inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}     
-<%}%>
-
-    virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
-
-    // some compile time constants
-
-    inline void raise(uint16_t trap_id, uint16_t cause){
-        auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
-        this->core.reg.trap_state = trap_val;
-    }
-
-    inline void leave(unsigned lvl){
-        this->core.leave_trap(lvl);
-    }
-
-    inline void wait(unsigned type){
-        this->core.wait_until(type);
-    }
-
-    inline void set_tval(uint64_t new_tval){
-        tval = new_tval;
-    }
-
-    uint64_t fetch_count{0};
-    uint64_t tval{0};
-
-    using yield_t = boost::coroutines2::coroutine<void>::push_type;
-    using coro_t = boost::coroutines2::coroutine<void>::pull_type;
-    std::vector<coro_t> spawn_blocks;
-
-    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
-    inline S sext(U from) {
-        auto mask = (1ULL<<W) - 1;
-        auto sign_mask = 1ULL<<(W-1);
-        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
-    }
-    
-    inline void process_spawn_blocks() {
-        if(spawn_blocks.size()==0) return;
-        for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
-             if(*it){
-                 (*it)();
-                 ++it;
-             } else
-                 spawn_blocks.erase(it);
-    }
-<%functions.each{ it.eachLine { %>
-    ${it}<%}%>
-<%}%>
-
-private:
-    /****************************************************************************
-     * start opcode definitions
-     ****************************************************************************/
-    struct instruction_descriptor {
-        uint32_t length;
-        uint32_t value;
-        uint32_t mask;
-        typename arch::traits<ARCH>::opcode_e op;
-    };
-
-    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
-         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
-    }};
-
-    //needs to be declared after instr_descr
-    decoder instr_decoder;
-
-    iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        if(this->core.has_mmu()) {
-            auto phys_pc = this->core.virt2phys(pc);
-//            if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-//                if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
-//                if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
-//                    if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok)
-//                        return iss::Err;
-//            } else {
-                if (this->core.read(phys_pc, 4, data) != iss::Ok)
-                    return iss::Err;
-//            }
-        } else {
-            if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok)
-                return iss::Err;
-
-        }
-        return iss::Ok;
-    }
-};
-
-template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
-    volatile CODE_WORD x = insn;
-    insn = 2 * x;
-}
-
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
-
-// according to
-// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
-#ifdef __GCC__
-constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
-#elif __cplusplus < 201402L
-constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
-constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
-#else
-constexpr size_t bit_count(uint32_t u) {
-    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
-    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
-}
-#endif
-
-template <typename ARCH>
-vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id)
-, instr_decoder([this]() {
-        std::vector<generic_instruction_descriptor> g_instr_descr;
-        g_instr_descr.reserve(instr_descr.size());
-        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
-            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
-            g_instr_descr.push_back(new_instr_descr);
-        }
-        return std::move(g_instr_descr);
-    }()) {}
-
-inline bool is_icount_limit_enabled(finish_cond_e cond){
-    return (cond & finish_cond_e::ICOUNT_LIMIT) == finish_cond_e::ICOUNT_LIMIT;
-}
-
-inline bool is_fcount_limit_enabled(finish_cond_e cond){
-    return (cond & finish_cond_e::FCOUNT_LIMIT) == finish_cond_e::FCOUNT_LIMIT;
-}
-
-inline bool is_jump_to_self_enabled(finish_cond_e cond){
-    return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
-}
-
-template <typename ARCH>
-typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t count_limit){
-    auto pc=start;
-    auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-    auto* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-    auto& trap_state = this->core.reg.trap_state;
-    auto& icount =  this->core.reg.icount;
-    auto& cycle =  this->core.reg.cycle;
-    auto& instret =  this->core.reg.instret;
-    auto& instr =  this->core.reg.instruction;
-    // we fetch at max 4 byte, alignment is 2
-    auto *const data = reinterpret_cast<uint8_t*>(&instr);
-
-    while(!this->core.should_stop() &&
-            !(is_icount_limit_enabled(cond) && icount >= count_limit) &&
-            !(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
-        if(this->debugging_enabled())
-            this->tgt_adapter->check_continue(*PC);
-        pc.val=*PC;
-        if(fetch_ins(pc, data)!=iss::Ok){
-            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
-            process_spawn_blocks();
-            if(this->sync_exec && POST_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
-            pc.val = super::core.enter_trap(arch::traits<ARCH>::RV_CAUSE_FETCH_ACCESS<<16, pc.val, 0);
-        } else {
-            if (is_jump_to_self_enabled(cond) &&
-                    (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-            uint32_t inst_index = instr_decoder.decode_instr(instr);
-            opcode_e inst_id = arch::traits<ARCH>::opcode_e::MAX_OPCODE;;
-            if(inst_index <instr_descr.size())
-                inst_id = instr_descr[inst_index].op;
-
-            // pre execution stuff
-            this->core.reg.last_branch = 0;
-            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
-            try{
-                switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
-                case arch::traits<ARCH>::opcode_e::${instr.name}: {
-                    <%instr.fields.eachLine{%>${it}
-                    <%}%>if(this->disass_enabled){
-                        /* generate console output when executing the command */<%instr.disass.eachLine{%>
-                        ${it}<%}%>
-                        this->core.disass_output(pc.val, mnemonic);
-                    }
-                    // used registers<%instr.usedVariables.each{ k,v->
-                    if(v.isArray) {%>
-                    auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
-                    auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
-                    <%}}%>// calculate next pc value
-                    *NEXT_PC = *PC + ${instr.length/8};
-                    // execute instruction<%instr.behavior.eachLine{%>
-                    ${it}<%}%>
-                    break;
-                }// @suppress("No break at end of case")<%}%>
-                default: {
-                    *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
-                    raise(0,  2);
-                }
-                }
-            }catch(memory_access_exception& e){}
-            // post execution stuff
-            process_spawn_blocks();
-            if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
-            // if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt
-            //    this->core.reg.trap_state =  this->core.reg.pending_trap;
-            // trap check
-            if(trap_state!=0){
-                //In case of Instruction address misaligned (cause = 0 and trapid = 0) need the targeted addr (in tval)
-                auto mcause = (trap_state>>16) & 0xff; 
-                super::core.enter_trap(trap_state, pc.val, mcause ? instr:tval);
-            } else {
-                icount++;
-                instret++;
-            }
-            *PC = *NEXT_PC;
-            this->core.reg.trap_state =  this->core.reg.pending_trap;
-        }
-        fetch_count++;
-        cycle++;
-    }
-    return pc;
-}
-
-} // namespace ${coreDef.name.toLowerCase()}
-
-template <>
-std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
-    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
-    return std::unique_ptr<vm_if>(ret);
-}
-} // namespace interp
-} // namespace iss
-
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-#include <iss/factory.h>
-namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        })
-};
-}
-}
-// clang-format on

gen_input/templates/interp/CORENAME_cyles.txt.gtl

@@ -0,0 +1,9 @@
+{ 
+	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
+		{
+			"name"  : "${instr.name}",
+			"size"  : ${instr.length},
+			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
+		}<%}%>
+	]
+}

gen_input/templates/interp/incl-CORENAME.h.gtl

@@ -0,0 +1,223 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+<% 
+import com.minres.coredsl.coreDsl.Register
+import com.minres.coredsl.coreDsl.RegisterFile
+import com.minres.coredsl.coreDsl.RegisterAlias
+def getTypeSize(size){
+	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
+}
+def getOriginalName(reg){
+    if( reg.original instanceof RegisterFile) {
+    	if( reg.index != null ) {
+        	return reg.original.name+generator.generateHostCode(reg.index)
+        } else {
+        	return reg.original.name
+        }
+    } else if(reg.original instanceof Register){
+        return reg.original.name
+    }
+}
+def getRegisterNames(){
+	def regNames = []
+ 	allRegs.each { reg -> 
+		if( reg instanceof RegisterFile) {
+			(reg.range.right..reg.range.left).each{
+    			regNames+=reg.name.toLowerCase()+it
+            }
+        } else if(reg instanceof Register){
+    		regNames+=reg.name.toLowerCase()
+        }
+    }
+    return regNames
+}
+def getRegisterAliasNames(){
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
+		if( reg instanceof RegisterFile) {
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
+        } else if(reg instanceof Register){
+    		regMap[reg.name]?:reg.name.toLowerCase()
+        }
+ 	}.flatten()
+}
+%>
+#ifndef _${coreDef.name.toUpperCase()}_H_
+#define _${coreDef.name.toUpperCase()}_H_
+
+#include <array>
+#include <iss/arch/traits.h>
+#include <iss/arch_if.h>
+#include <iss/vm_if.h>
+
+namespace iss {
+namespace arch {
+
+struct ${coreDef.name.toLowerCase()};
+
+template <> struct traits<${coreDef.name.toLowerCase()}> {
+
+	constexpr static char const* const core_type = "${coreDef.name}";
+    
+  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
+ 		{"${getRegisterNames().join("\", \"")}"}};
+ 
+  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
+ 		{"${getRegisterAliasNames().join("\", \"")}"}};
+
+    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
+
+    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
+
+    enum reg_e {<%
+     	allRegs.each { reg -> 
+    		if( reg instanceof RegisterFile) {
+    			(reg.range.right..reg.range.left).each{%>
+        ${reg.name}${it},<%
+                }
+            } else if(reg instanceof Register){ %>
+        ${reg.name},<%  
+            }
+        }%>
+        NUM_REGS,
+        NEXT_${pc.name}=NUM_REGS,
+        TRAP_STATE,
+        PENDING_TRAP,
+        MACHINE_STATE,
+        LAST_BRANCH,
+        ICOUNT<% 
+     	allRegs.each { reg -> 
+    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
+        ${reg.name} = ${aliasname}<%
+            }
+        }%>
+    };
+
+    using reg_t = uint${regDataWidth}_t;
+
+    using addr_t = uint${addrDataWidth}_t;
+
+    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
+
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
+
+ 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
+ 		{${regSizes.join(",")}}};
+
+    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
+    	{${regOffsets.join(",")}}};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
+};
+
+struct ${coreDef.name.toLowerCase()}: public arch_if {
+
+    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
+    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
+    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
+    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
+
+    ${coreDef.name.toLowerCase()}();
+    ~${coreDef.name.toLowerCase()}();
+
+    void reset(uint64_t address=0) override;
+
+    uint8_t* get_regs_base_ptr() override;
+    /// deprecated
+    void get_reg(short idx, std::vector<uint8_t>& value) override {}
+    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
+    /// deprecated
+    bool get_flag(int flag) override {return false;}
+    void set_flag(int, bool value) override {};
+    /// deprecated
+    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
+
+    inline uint64_t get_icount() { return reg.icount; }
+
+    inline bool should_stop() { return interrupt_sim; }
+
+    inline uint64_t stop_code() { return interrupt_sim; }
+
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
+
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
+
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
+protected:
+    struct ${coreDef.name}_regs {<%
+     	allRegs.each { reg -> 
+    		if( reg instanceof RegisterFile) {
+    			(reg.range.right..reg.range.left).each{%>
+        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
+                }
+            } else if(reg instanceof Register){ %>
+        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
+            }
+        }%>
+        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
+        uint64_t icount = 0;
+    } reg;
+
+    std::array<address_type, 4> addr_mode;
+    
+    uint64_t interrupt_sim=0;
+<%
+def fcsr = allRegs.find {it.name=='FCSR'}
+if(fcsr != null) {%>
+	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
+	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
+<%} else { %>
+	uint32_t get_fcsr(){return 0;}
+	void set_fcsr(uint32_t val){}
+<%}%>
+};
+
+}
+}            
+#endif /* _${coreDef.name.toUpperCase()}_H_ */

gen_input/templates/interp/src-CORENAME.cpp.gtl

@@ -0,0 +1,107 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+ <% 
+import com.minres.coredsl.coreDsl.Register
+import com.minres.coredsl.coreDsl.RegisterFile
+import com.minres.coredsl.coreDsl.RegisterAlias
+def getOriginalName(reg){
+    if( reg.original instanceof RegisterFile) {
+    	if( reg.index != null ) {
+        	return reg.original.name+generator.generateHostCode(reg.index)
+        } else {
+        	return reg.original.name
+        }
+    } else if(reg.original instanceof Register){
+        return reg.original.name
+    }
+}
+def getRegisterNames(){
+	def regNames = []
+ 	allRegs.each { reg -> 
+		if( reg instanceof RegisterFile) {
+			(reg.range.right..reg.range.left).each{
+    			regNames+=reg.name.toLowerCase()+it
+            }
+        } else if(reg instanceof Register){
+    		regNames+=reg.name.toLowerCase()
+        }
+    }
+    return regNames
+}
+def getRegisterAliasNames(){
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
+		if( reg instanceof RegisterFile) {
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
+        } else if(reg instanceof Register){
+    		regMap[reg.name]?:reg.name.toLowerCase()
+        }
+ 	}.flatten()
+}
+%>
+#include "util/ities.h"
+#include <util/logging.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <cstdio>
+#include <cstring>
+#include <fstream>
+
+using namespace iss::arch;
+
+constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
+
+${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
+    reg.icount = 0;
+}
+
+${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
+
+void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
+    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
+    reg.PC=address;
+    reg.NEXT_PC=reg.PC;
+    reg.trap_state=0;
+    reg.machine_state=0x3;
+    reg.icount=0;
+}
+
+uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
+	return reinterpret_cast<uint8_t*>(&reg);
+}
+
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
+    return phys_addr_t(pc); // change logical address to physical address
+}
+

gen_input/templates/interp/vm-vm_CORENAME.cpp.gtl

@@ -0,0 +1,247 @@
+/*******************************************************************************
+ * Copyright (C) 2020 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#include "../fp_functions.h"
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/server.h>
+#include <iss/iss.h>
+#include <iss/interp/vm_base.h>
+#include <util/logging.h>
+#include <sstream>
+
+#ifndef FMT_HEADER_ONLY
+#define FMT_HEADER_ONLY
+#endif
+#include <fmt/format.h>
+
+#include <array>
+#include <iss/debugger/riscv_target_adapter.h>
+
+namespace iss {
+namespace interp {
+namespace ${coreDef.name.toLowerCase()} {
+using namespace iss::arch;
+using namespace iss::debugger;
+
+template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
+public:
+    using super = typename iss::interp::vm_base<ARCH>;
+    using virt_addr_t = typename super::virt_addr_t;
+    using phys_addr_t = typename super::phys_addr_t;
+    using code_word_t = typename super::code_word_t;
+    using addr_t = typename super::addr_t;
+    using reg_t = typename traits<ARCH>::reg_t;
+    using iss::interp::vm_base<ARCH>::get_reg;
+
+    vm_impl();
+
+    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
+
+    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
+
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
+        debugger_if::dbg_enabled = true;
+        if (super::tgt_adapter == nullptr)
+            super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
+        return super::tgt_adapter;
+    }
+
+protected:
+    using this_class = vm_impl<ARCH>;
+    using compile_ret_t = virt_addr_t;
+    using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
+
+    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
+
+    virt_addr_t execute_inst(virt_addr_t start, std::function<bool(void)> pred) override;
+
+    // some compile time constants
+    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
+    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
+    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
+    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
+
+    std::array<compile_func, LUT_SIZE> lut;
+
+    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
+    std::array<compile_func, LUT_SIZE> lut_11;
+
+    std::array<compile_func *, 4> qlut;
+
+    std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
+
+    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
+                         compile_func f) {
+        if (pos < 0) {
+            lut[idx] = f;
+        } else {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
+            } else {
+                if ((valid & bitmask) == 0) {
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
+                } else {
+                    auto new_val = idx << 1;
+                    if ((value & bitmask) != 0) new_val++;
+                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
+                }
+            }
+        }
+    }
+
+    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
+
+    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
+        if (pos >= 0) {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                lut_val = extract_fields(pos - 1, val, mask, lut_val);
+            } else {
+                auto new_val = lut_val << 1;
+                if ((val & bitmask) != 0) new_val++;
+                lut_val = extract_fields(pos - 1, val, mask, new_val);
+            }
+        }
+        return lut_val;
+    }
+
+    void raise_trap(uint16_t trap_id, uint16_t cause){
+        auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
+        this->template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE) = trap_val;
+        this->template get_reg<uint32_t>(arch::traits<ARCH>::NEXT_PC) = std::numeric_limits<uint32_t>::max();
+    }
+
+    void leave_trap(unsigned lvl){
+        this->core.leave_trap(lvl);
+        auto pc_val = super::template read_mem<reg_t>(traits<ARCH>::CSR, (lvl << 8) + 0x41);
+        this->template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc_val;
+        this->template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
+    }
+
+    void wait(unsigned type){
+        this->core.wait_until(type);
+    }
+
+
+private:
+    /****************************************************************************
+     * start opcode definitions
+     ****************************************************************************/
+    struct InstructionDesriptor {
+        size_t length;
+        uint32_t value;
+        uint32_t mask;
+        compile_func op;
+    };
+
+    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
+         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+        /* instruction ${instr.instruction.name} */
+        {${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+    }};
+ 
+    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
+    /* instruction ${idx}: ${instr.name} */
+    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){<%instr.code.eachLine{%>
+        ${it}<%}%>
+    }
+    <%}%>
+    /****************************************************************************
+     * end opcode definitions
+     ****************************************************************************/
+    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
+        pc = pc + ((instr & 3) == 3 ? 4 : 2);
+        return pc;
+    }
+};
+
+template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
+    volatile CODE_WORD x = insn;
+    insn = 2 * x;
+}
+
+template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
+
+template <typename ARCH>
+vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
+: vm_base<ARCH>(core, core_id, cluster_id) {
+    qlut[0] = lut_00.data();
+    qlut[1] = lut_01.data();
+    qlut[2] = lut_10.data();
+    qlut[3] = lut_11.data();
+    for (auto instr : instr_descr) {
+        auto quantrant = instr.value & 0x3;
+        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
+    }
+}
+
+template <typename ARCH>
+typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t start, std::function<bool(void)> pred) {
+    // we fetch at max 4 byte, alignment is 2
+    enum {TRAP_ID=1<<16};
+    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
+    code_word_t insn = 0;
+    auto *const data = (uint8_t *)&insn;
+    auto pc=start;
+    while(pred){
+        auto paddr = this->core.v2p(pc);
+        if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+            if (this->core.read(paddr, 2, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+            if ((insn & 0x3) == 0x3) // this is a 32bit instruction
+                if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+        } else {
+            if (this->core.read(paddr, 4, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+        }
+        if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+        auto lut_val = extract_fields(insn);
+        auto f = qlut[insn & 0x3][lut_val];
+        if (!f)
+            f = &this_class::illegal_intruction;
+        pc = (this->*f)(pc, insn);
+    }
+    return pc;
+}
+
+} // namespace mnrv32
+
+template <>
+std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
+    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
+    return std::unique_ptr<vm_if>(ret);
+}
+} // namespace interp
+} // namespace iss

gen_input/templates/llvm/CORENAME.cpp.gtl

@@ -1,384 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017-2024 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-// clang-format off
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/server.h>
-#include <iss/iss.h>
-#include <iss/llvm/vm_base.h>
-#include <util/logging.h>
-#include <iss/instruction_decoder.h>
-<%def fcsr = registers.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-#include <vm/fp_functions.h><%}%>
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <fmt/format.h>
-
-#include <array>
-#include <iss/debugger/riscv_target_adapter.h>
-
-namespace iss {
-namespace llvm {
-namespace fp_impl {
-void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
-}
-
-namespace ${coreDef.name.toLowerCase()} {
-using namespace ::llvm;
-using namespace iss::arch;
-using namespace iss::debugger;
-
-template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
-public:
-    using traits = arch::traits<ARCH>;
-    using super = typename iss::llvm::vm_base<ARCH>;
-    using virt_addr_t = typename super::virt_addr_t;
-    using phys_addr_t = typename super::phys_addr_t;
-    using code_word_t = typename super::code_word_t;
-    using addr_t = typename super::addr_t;
-
-    vm_impl();
-
-    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
-
-    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
-
-    target_adapter_if *accquire_target_adapter(server_if *srv) override {
-        debugger_if::dbg_enabled = true;
-        if (vm_base<ARCH>::tgt_adapter == nullptr)
-            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
-        return vm_base<ARCH>::tgt_adapter;
-    }
-
-protected:
-    using vm_base<ARCH>::get_reg_ptr;
-
-    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
-<%if(fcsr != null) {%>
-    inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}   
-<%}%>
-    template <typename T> inline ConstantInt *size(T type) {
-        return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
-    }
-
-    void setup_module(Module* m) override {
-        super::setup_module(m);
-        iss::llvm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE, traits::XLEN);
-    }
-
-    inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
-        return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
-    }
-
-    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
-
-    void gen_leave_behavior(BasicBlock *leave_blk) override;
-    void gen_raise_trap(uint16_t trap_id, uint16_t cause);
-    void gen_leave_trap(unsigned lvl);
-    void gen_wait(unsigned type);
-    void set_tval(uint64_t new_tval);
-    void set_tval(Value* new_tval);
-    void gen_trap_behavior(BasicBlock *) override;
-    void gen_instr_prologue();
-    void gen_instr_epilogue(BasicBlock *bb);
-
-    inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
-        return this->builder.CreateLoad(this->get_typeptr(i), get_reg_ptr(i), false);
-    }
-
-    inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
-        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val),
-                                                           this->get_type(traits::XLEN));
-        this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
-    }
-
-    // some compile time constants
-
-    using this_class = vm_impl<ARCH>;
-    using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
-                                                                                  code_word_t instr,
-                                                                                  BasicBlock *bb);
-    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
-    inline S sext(U from) {
-        auto mask = (1ULL<<W) - 1;
-        auto sign_mask = 1ULL<<(W-1);
-        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
-    }
-<%functions.each{ it.eachLine { %>
-    ${it}<%}%>
-<%}%>
-private:
-    /****************************************************************************
-     * start opcode definitions
-     ****************************************************************************/
-    struct instruction_descriptor {
-        uint32_t length;
-        uint32_t value;
-        uint32_t mask;
-        compile_func op;
-    };
-
-    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
-         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
-    }};
-
-    //needs to be declared after instr_descr
-    decoder instr_decoder;
-
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        uint64_t PC = pc.val;
-        <%instr.fields.eachLine{%>${it}
-        <%}%>if(this->disass_enabled){
-            /* generate console output when executing the command */<%instr.disass.eachLine{%>
-            ${it}<%}%>
-            std::vector<Value*> args {
-                this->core_ptr,
-                this->gen_const(64, pc.val),
-                this->builder.CreateGlobalStringPtr(mnemonic),
-            };
-            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
-        }
-        bb->setName(fmt::format("${instr.name}_0x{:X}",pc.val));
-        this->gen_sync(PRE_SYNC,${idx});
-        
-        this->gen_set_pc(pc, traits::PC);
-        this->set_tval(instr);
-        pc=pc+ ${instr.length/8};
-        this->gen_set_pc(pc, traits::NEXT_PC);
-        
-        this->gen_instr_prologue();
-        /*generate behavior*/
-        <%instr.behavior.eachLine{%>${it}
-        <%}%>
-        this->gen_sync(POST_SYNC, ${idx});
-        this->gen_instr_epilogue(bb);
-        this->builder.CreateBr(bb);
-    	return returnValue;        
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    std::tuple<continuation_e, BasicBlock *> illegal_instruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
-        if(this->disass_enabled){
-            auto mnemonic = std::string("illegal_instruction");
-            std::vector<Value*> args {
-                this->core_ptr,
-                this->gen_const(64, pc.val),
-                this->builder.CreateGlobalStringPtr(mnemonic),
-            };
-            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
-        }
-        this->gen_sync(iss::PRE_SYNC, instr_descr.size());
-        this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
-                                   get_reg_ptr(traits::PC), true);
-        this->builder.CreateStore(
-            this->builder.CreateAdd(this->builder.CreateLoad(this->get_typeptr(traits::ICOUNT), get_reg_ptr(traits::ICOUNT), true),
-                                     this->gen_const(64U, 1)),
-            get_reg_ptr(traits::ICOUNT), true);
-        pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        this->set_tval(instr);
-        this->gen_raise_trap(0, 2);     // illegal instruction trap
-		this->gen_sync(iss::POST_SYNC, instr_descr.size());
-        bb = this->leave_blk;
-        this->gen_instr_epilogue(bb);
-        this->builder.CreateBr(bb);
-        return std::make_tuple(ILLEGAL_INSTR, nullptr);
-    }    
-};
-
-template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
-    volatile CODE_WORD x = instr;
-    instr = 2 * x;
-}
-
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
-
-template <typename ARCH>
-vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id)
-, instr_decoder([this]() {
-        std::vector<generic_instruction_descriptor> g_instr_descr;
-        g_instr_descr.reserve(instr_descr.size());
-        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
-            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
-            g_instr_descr.push_back(new_instr_descr);
-        }
-        return std::move(g_instr_descr);
-    }()) {}
-
-template <typename ARCH>
-std::tuple<continuation_e, BasicBlock *>
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
-    // we fetch at max 4 byte, alignment is 2
-    enum {TRAP_ID=1<<16};
-    code_word_t instr = 0;
-    // const typename traits::addr_t upper_bits = ~traits::PGMASK;
-    phys_addr_t paddr(pc);
-    auto *const data = (uint8_t *)&instr;
-    if(this->core.has_mmu())
-        paddr = this->core.virt2phys(pc);
-    auto res = this->core.read(paddr, 4, data);
-    if (res != iss::Ok) 
-        return std::make_tuple(ILLEGAL_FETCH, nullptr);
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001)
-        return std::make_tuple(JUMP_TO_SELF, nullptr);
-    ++inst_cnt;
-    uint32_t inst_index = instr_decoder.decode_instr(instr);
-    compile_func f = nullptr;
-    if(inst_index < instr_descr.size())
-        f = instr_descr[inst_index].op;
-    if (f == nullptr) {
-        f = &this_class::illegal_instruction;
-    }
-    return (this->*f)(pc, instr, this_block);
-}
-
-template <typename ARCH>
-void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
-    this->builder.SetInsertPoint(leave_blk);
-    this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC),get_reg_ptr(traits::NEXT_PC), false));
-}
-
-template <typename ARCH>
-void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
-    auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
-    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true);
-}
-
-template <typename ARCH>
-void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
-    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
-    this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
-    this->builder.CreateStore(this->gen_const(32U, static_cast<int>(UNKNOWN_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
-}
-
-template <typename ARCH>
-void vm_impl<ARCH>::gen_wait(unsigned type) {
-    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
-    this->builder.CreateCall(this->mod->getFunction("wait"), args);
-}
-
-template <typename ARCH>
-inline void vm_impl<ARCH>::set_tval(uint64_t tval) {
-    auto tmp_tval = this->gen_const(64, tval);
-    this->set_tval(tmp_tval);
-}
-template <typename ARCH>
-inline void vm_impl<ARCH>::set_tval(Value* new_tval) {
-    this->builder.CreateStore(this->gen_ext(new_tval, 64, false), this->tval);
-}
-template <typename ARCH> 
-void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
-    this->builder.SetInsertPoint(trap_blk);
-    auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
-    auto *cur_pc_val = this->builder.CreateLoad(this->get_typeptr(traits::PC), get_reg_ptr(traits::PC), true);
-    std::vector<Value *> args{this->core_ptr,
-                                this->adj_to64(trap_state_val),
-                                this->adj_to64(cur_pc_val),
-                              this->adj_to64(this->builder.CreateLoad(this->get_type(64),this->tval))};
-    this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
-    this->builder.CreateStore(this->gen_const(32U, static_cast<int>(UNKNOWN_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
-
-    auto *trap_addr_val = this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false);
-    this->builder.CreateRet(trap_addr_val);
-}
-template <typename ARCH>
-void vm_impl<ARCH>::gen_instr_prologue() {
-    auto* trap_val =
-        this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::PENDING_TRAP), get_reg_ptr(arch::traits<ARCH>::PENDING_TRAP));
-    this->builder.CreateStore(trap_val, get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), false);
-}
-            
-
-template <typename ARCH>
-void vm_impl<ARCH>::gen_instr_epilogue(BasicBlock *bb) {
-    auto* target_bb = BasicBlock::Create(this->mod->getContext(), "", this->func, bb);
-    auto *v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
-    this->gen_cond_branch(this->builder.CreateICmp(
-                              ICmpInst::ICMP_EQ, v,
-                              ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
-                          target_bb, this->trap_blk, 1);
-    this->builder.SetInsertPoint(target_bb);
-    // update icount
-    auto* icount_val = this->builder.CreateAdd(
-        this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::ICOUNT), get_reg_ptr(arch::traits<ARCH>::ICOUNT)), this->gen_const(64U, 1));
-    this->builder.CreateStore(icount_val, get_reg_ptr(arch::traits<ARCH>::ICOUNT), false);
-}
-
-} // namespace ${coreDef.name.toLowerCase()}
-
-template <>
-std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
-    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
-    return std::unique_ptr<vm_if>(ret);
-}
-} // namespace llvm
-} // namespace iss
-
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-#include <iss/factory.h>
-namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        })
-};
-}
-}
-// clang-format on

gen_input/templates/llvm/CORENAME_cyles.txt.gtl

@@ -0,0 +1,9 @@
+{ 
+	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
+		{
+			"name"  : "${instr.name}",
+			"size"  : ${instr.length},
+			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
+		}<%}%>
+	]
+}

gen_input/templates/llvm/incl-CORENAME.h.gtl

@@ -0,0 +1,223 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+<% 
+import com.minres.coredsl.coreDsl.Register
+import com.minres.coredsl.coreDsl.RegisterFile
+import com.minres.coredsl.coreDsl.RegisterAlias
+def getTypeSize(size){
+	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
+}
+def getOriginalName(reg){
+    if( reg.original instanceof RegisterFile) {
+    	if( reg.index != null ) {
+        	return reg.original.name+generator.generateHostCode(reg.index)
+        } else {
+        	return reg.original.name
+        }
+    } else if(reg.original instanceof Register){
+        return reg.original.name
+    }
+}
+def getRegisterNames(){
+	def regNames = []
+ 	allRegs.each { reg -> 
+		if( reg instanceof RegisterFile) {
+			(reg.range.right..reg.range.left).each{
+    			regNames+=reg.name.toLowerCase()+it
+            }
+        } else if(reg instanceof Register){
+    		regNames+=reg.name.toLowerCase()
+        }
+    }
+    return regNames
+}
+def getRegisterAliasNames(){
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
+		if( reg instanceof RegisterFile) {
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
+        } else if(reg instanceof Register){
+    		regMap[reg.name]?:reg.name.toLowerCase()
+        }
+ 	}.flatten()
+}
+%>
+#ifndef _${coreDef.name.toUpperCase()}_H_
+#define _${coreDef.name.toUpperCase()}_H_
+
+#include <array>
+#include <iss/arch/traits.h>
+#include <iss/arch_if.h>
+#include <iss/vm_if.h>
+
+namespace iss {
+namespace arch {
+
+struct ${coreDef.name.toLowerCase()};
+
+template <> struct traits<${coreDef.name.toLowerCase()}> {
+
+	constexpr static char const* const core_type = "${coreDef.name}";
+    
+  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
+ 		{"${getRegisterNames().join("\", \"")}"}};
+ 
+  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
+ 		{"${getRegisterAliasNames().join("\", \"")}"}};
+
+    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
+
+    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
+
+    enum reg_e {<%
+     	allRegs.each { reg -> 
+    		if( reg instanceof RegisterFile) {
+    			(reg.range.right..reg.range.left).each{%>
+        ${reg.name}${it},<%
+                }
+            } else if(reg instanceof Register){ %>
+        ${reg.name},<%  
+            }
+        }%>
+        NUM_REGS,
+        NEXT_${pc.name}=NUM_REGS,
+        TRAP_STATE,
+        PENDING_TRAP,
+        MACHINE_STATE,
+        LAST_BRANCH,
+        ICOUNT<% 
+     	allRegs.each { reg -> 
+    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
+        ${reg.name} = ${aliasname}<%
+            }
+        }%>
+    };
+
+    using reg_t = uint${regDataWidth}_t;
+
+    using addr_t = uint${addrDataWidth}_t;
+
+    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
+
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
+
+ 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
+ 		{${regSizes.join(",")}}};
+
+    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
+    	{${regOffsets.join(",")}}};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
+};
+
+struct ${coreDef.name.toLowerCase()}: public arch_if {
+
+    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
+    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
+    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
+    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
+
+    ${coreDef.name.toLowerCase()}();
+    ~${coreDef.name.toLowerCase()}();
+
+    void reset(uint64_t address=0) override;
+
+    uint8_t* get_regs_base_ptr() override;
+    /// deprecated
+    void get_reg(short idx, std::vector<uint8_t>& value) override {}
+    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
+    /// deprecated
+    bool get_flag(int flag) override {return false;}
+    void set_flag(int, bool value) override {};
+    /// deprecated
+    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
+
+    inline uint64_t get_icount() { return reg.icount; }
+
+    inline bool should_stop() { return interrupt_sim; }
+
+    inline uint64_t stop_code() { return interrupt_sim; }
+
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
+
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
+
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
+protected:
+    struct ${coreDef.name}_regs {<%
+     	allRegs.each { reg -> 
+    		if( reg instanceof RegisterFile) {
+    			(reg.range.right..reg.range.left).each{%>
+        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
+                }
+            } else if(reg instanceof Register){ %>
+        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
+            }
+        }%>
+        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
+        uint64_t icount = 0;
+    } reg;
+
+    std::array<address_type, 4> addr_mode;
+    
+    uint64_t interrupt_sim=0;
+<%
+def fcsr = allRegs.find {it.name=='FCSR'}
+if(fcsr != null) {%>
+	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
+	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
+<%} else { %>
+	uint32_t get_fcsr(){return 0;}
+	void set_fcsr(uint32_t val){}
+<%}%>
+};
+
+}
+}            
+#endif /* _${coreDef.name.toUpperCase()}_H_ */

gen_input/templates/llvm/src-CORENAME.cpp.gtl

@@ -0,0 +1,107 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+ <% 
+import com.minres.coredsl.coreDsl.Register
+import com.minres.coredsl.coreDsl.RegisterFile
+import com.minres.coredsl.coreDsl.RegisterAlias
+def getOriginalName(reg){
+    if( reg.original instanceof RegisterFile) {
+    	if( reg.index != null ) {
+        	return reg.original.name+generator.generateHostCode(reg.index)
+        } else {
+        	return reg.original.name
+        }
+    } else if(reg.original instanceof Register){
+        return reg.original.name
+    }
+}
+def getRegisterNames(){
+	def regNames = []
+ 	allRegs.each { reg -> 
+		if( reg instanceof RegisterFile) {
+			(reg.range.right..reg.range.left).each{
+    			regNames+=reg.name.toLowerCase()+it
+            }
+        } else if(reg instanceof Register){
+    		regNames+=reg.name.toLowerCase()
+        }
+    }
+    return regNames
+}
+def getRegisterAliasNames(){
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
+		if( reg instanceof RegisterFile) {
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
+        } else if(reg instanceof Register){
+    		regMap[reg.name]?:reg.name.toLowerCase()
+        }
+ 	}.flatten()
+}
+%>
+#include "util/ities.h"
+#include <util/logging.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <cstdio>
+#include <cstring>
+#include <fstream>
+
+using namespace iss::arch;
+
+constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
+
+${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
+    reg.icount = 0;
+}
+
+${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
+
+void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
+    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
+    reg.PC=address;
+    reg.NEXT_PC=reg.PC;
+    reg.trap_state=0;
+    reg.machine_state=0x3;
+    reg.icount=0;
+}
+
+uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
+	return reinterpret_cast<uint8_t*>(&reg);
+}
+
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
+    return phys_addr_t(pc); // change logical address to physical address
+}
+

gen_input/templates/llvm/vm-vm_CORENAME.cpp.gtl

@@ -0,0 +1,325 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/server.h>
+#include <iss/iss.h>
+#include <iss/llvm/vm_base.h>
+#include <util/logging.h>
+
+#ifndef FMT_HEADER_ONLY
+#define FMT_HEADER_ONLY
+#endif
+#include <fmt/format.h>
+
+#include <array>
+#include <iss/debugger/riscv_target_adapter.h>
+
+namespace iss {
+namespace llvm {
+namespace fp_impl {
+void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
+}
+
+namespace ${coreDef.name.toLowerCase()} {
+using namespace ::llvm;
+using namespace iss::arch;
+using namespace iss::debugger;
+
+template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
+public:
+    using super = typename iss::llvm::vm_base<ARCH>;
+    using virt_addr_t = typename super::virt_addr_t;
+    using phys_addr_t = typename super::phys_addr_t;
+    using code_word_t = typename super::code_word_t;
+    using addr_t = typename super::addr_t;
+
+    vm_impl();
+
+    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
+
+    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
+
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
+        debugger_if::dbg_enabled = true;
+        if (vm_base<ARCH>::tgt_adapter == nullptr)
+            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
+        return vm_base<ARCH>::tgt_adapter;
+    }
+
+protected:
+    using vm_base<ARCH>::get_reg_ptr;
+
+    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
+
+    template <typename T> inline ConstantInt *size(T type) {
+        return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
+    }
+
+    void setup_module(Module* m) override {
+        super::setup_module(m);
+        iss::llvm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
+    }
+
+    inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
+        return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
+    }
+
+    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
+
+    void gen_leave_behavior(BasicBlock *leave_blk) override;
+
+    void gen_raise_trap(uint16_t trap_id, uint16_t cause);
+
+    void gen_leave_trap(unsigned lvl);
+
+    void gen_wait(unsigned type);
+
+    void gen_trap_behavior(BasicBlock *) override;
+
+    void gen_trap_check(BasicBlock *bb);
+
+    inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
+        return this->builder.CreateLoad(get_reg_ptr(i), false);
+    }
+
+    inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
+        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
+                                                           this->get_type(traits<ARCH>::XLEN));
+        this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
+    }
+
+    // some compile time constants
+    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
+    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
+    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
+    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
+
+    using this_class = vm_impl<ARCH>;
+    using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
+                                                                                  code_word_t instr,
+                                                                                  BasicBlock *bb);
+    std::array<compile_func, LUT_SIZE> lut;
+
+    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
+    std::array<compile_func, LUT_SIZE> lut_11;
+
+	std::array<compile_func *, 4> qlut;
+
+	std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
+
+    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
+                         compile_func f) {
+        if (pos < 0) {
+            lut[idx] = f;
+        } else {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
+            } else {
+                if ((valid & bitmask) == 0) {
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
+                } else {
+                    auto new_val = idx << 1;
+                    if ((value & bitmask) != 0) new_val++;
+                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
+                }
+            }
+        }
+    }
+
+    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
+
+    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
+        if (pos >= 0) {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                lut_val = extract_fields(pos - 1, val, mask, lut_val);
+            } else {
+                auto new_val = lut_val << 1;
+                if ((val & bitmask) != 0) new_val++;
+                lut_val = extract_fields(pos - 1, val, mask, new_val);
+            }
+        }
+        return lut_val;
+    }
+
+private:
+    /****************************************************************************
+     * start opcode definitions
+     ****************************************************************************/
+    struct InstructionDesriptor {
+        size_t length;
+        uint32_t value;
+        uint32_t mask;
+        compile_func op;
+    };
+
+    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
+         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+        /* instruction ${instr.instruction.name} */
+        {${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+    }};
+ 
+    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
+    /* instruction ${idx}: ${instr.name} */
+    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){<%instr.code.eachLine{%>
+    	${it}<%}%>
+    }
+    <%}%>
+    /****************************************************************************
+     * end opcode definitions
+     ****************************************************************************/
+    std::tuple<continuation_e, BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
+		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
+        this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
+                                   get_reg_ptr(traits<ARCH>::PC), true);
+        this->builder.CreateStore(
+            this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
+                                     this->gen_const(64U, 1)),
+            get_reg_ptr(traits<ARCH>::ICOUNT), true);
+        pc = pc + ((instr & 3) == 3 ? 4 : 2);
+        this->gen_raise_trap(0, 2);     // illegal instruction trap
+		this->gen_sync(iss::POST_SYNC, instr_descr.size());
+        this->gen_trap_check(this->leave_blk);
+        return std::make_tuple(BRANCH, nullptr);
+    }
+};
+
+template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
+    volatile CODE_WORD x = insn;
+    insn = 2 * x;
+}
+
+template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
+
+template <typename ARCH>
+vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
+: vm_base<ARCH>(core, core_id, cluster_id) {
+    qlut[0] = lut_00.data();
+    qlut[1] = lut_01.data();
+    qlut[2] = lut_10.data();
+    qlut[3] = lut_11.data();
+    for (auto instr : instr_descr) {
+        auto quantrant = instr.value & 0x3;
+        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
+    }
+}
+
+template <typename ARCH>
+std::tuple<continuation_e, BasicBlock *>
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
+    // we fetch at max 4 byte, alignment is 2
+    enum {TRAP_ID=1<<16};
+    code_word_t insn = 0;
+    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
+    phys_addr_t paddr(pc);
+    auto *const data = (uint8_t *)&insn;
+    paddr = this->core.v2p(pc);
+    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+        auto res = this->core.read(paddr, 2, data);
+        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
+            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+        }
+    } else {
+        auto res = this->core.read(paddr, 4, data);
+        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+    }
+    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    // curr pc on stack
+    ++inst_cnt;
+    auto lut_val = extract_fields(insn);
+    auto f = qlut[insn & 0x3][lut_val];
+    if (f == nullptr) {
+        f = &this_class::illegal_intruction;
+    }
+    return (this->*f)(pc, insn, this_block);
+}
+
+template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
+    this->builder.SetInsertPoint(leave_blk);
+    this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
+}
+
+template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
+    auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
+    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
+}
+
+template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
+    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
+    this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
+    auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
+    this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
+}
+
+template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
+    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
+    this->builder.CreateCall(this->mod->getFunction("wait"), args);
+}
+
+template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
+    this->builder.SetInsertPoint(trap_blk);
+    auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
+                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
+    std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
+                              this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
+    this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
+    auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
+    this->builder.CreateRet(trap_addr_val);
+}
+
+template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
+    auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
+    this->gen_cond_branch(this->builder.CreateICmp(
+                              ICmpInst::ICMP_EQ, v,
+                              ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
+                          bb, this->trap_blk, 1);
+}
+
+} // namespace ${coreDef.name.toLowerCase()}
+
+template <>
+std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
+    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
+    return std::unique_ptr<vm_if>(ret);
+}
+} // namespace llvm
+} // namespace iss

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -1,350 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2020-2024 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-// clang-format off
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/server.h>
-#include <iss/iss.h>
-#include <iss/tcc/vm_base.h>
-#include <util/logging.h>
-#include <sstream>
-#include <iss/instruction_decoder.h>
-<%def fcsr = registers.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-#include <vm/fp_functions.h><%}%>
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <fmt/format.h>
-
-#include <array>
-#include <iss/debugger/riscv_target_adapter.h>
-
-namespace iss {
-namespace tcc {
-namespace ${coreDef.name.toLowerCase()} {
-using namespace iss::arch;
-using namespace iss::debugger;
-
-template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
-public:
-    using traits = arch::traits<ARCH>;
-    using super       = typename iss::tcc::vm_base<ARCH>;
-    using virt_addr_t = typename super::virt_addr_t;
-    using phys_addr_t = typename super::phys_addr_t;
-    using code_word_t = typename super::code_word_t;
-    using mem_type_e  = typename traits::mem_type_e;    
-    using addr_t      = typename super::addr_t;
-    using tu_builder  = typename super::tu_builder;
-
-    vm_impl();
-
-    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
-
-    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
-
-    target_adapter_if *accquire_target_adapter(server_if *srv) override {
-        debugger_if::dbg_enabled = true;
-        if (vm_base<ARCH>::tgt_adapter == nullptr)
-            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
-        return vm_base<ARCH>::tgt_adapter;
-    }
-
-protected:
-    using vm_base<ARCH>::get_reg_ptr;
-
-    using this_class = vm_impl<ARCH>;
-    using compile_ret_t = std::tuple<continuation_e>;
-    using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
-
-    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
-<%
-if(fcsr != null) {%>
-    inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}   
-
-    void add_prologue(tu_builder& tu) override;
-<%}%>
-    void setup_module(std::string m) override {
-        super::setup_module(m);
-    }
-
-    compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, tu_builder&) override;
-
-    void gen_trap_behavior(tu_builder& tu) override;
-
-    void gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause);
-
-    void gen_leave_trap(tu_builder& tu, unsigned lvl);
-
-    inline void gen_set_tval(tu_builder& tu, uint64_t new_tval);
-
-    inline void gen_set_tval(tu_builder& tu, value new_tval);
-
-    inline void gen_trap_check(tu_builder& tu) {
-        tu("if(*trap_state!=0) goto trap_entry;");
-    }
-
-    inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
-        switch(reg_num){
-        case traits::NEXT_PC:
-            tu("*next_pc = {:#x};", pc.val);
-            break;
-        case traits::PC:
-            tu("*pc = {:#x};", pc.val);
-            break;
-        default:
-            if(!tu.defined_regs[reg_num]){
-                tu("reg_t* reg{:02d} = (reg_t*){:#x};", reg_num, reinterpret_cast<uintptr_t>(get_reg_ptr(reg_num)));
-            tu.defined_regs[reg_num]=true;
-            }
-            tu("*reg{:02d} = {:#x};", reg_num, pc.val);
-        }
-    }
-
-    
-    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
-    inline S sext(U from) {
-        auto mask = (1ULL<<W) - 1;
-        auto sign_mask = 1ULL<<(W-1);
-        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
-    }
-
-<%functions.each{ it.eachLine { %>
-    ${it}<%}%>
-<%}%>
-private:
-    /****************************************************************************
-     * start opcode definitions
-     ****************************************************************************/
-    struct instruction_descriptor {
-        uint32_t length;
-        uint32_t value;
-        uint32_t mask;
-        compile_func op;
-    };
-
-    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
-         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
-    }};
-
-    //needs to be declared after instr_descr
-    decoder instr_decoder;
-
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
-        tu("${instr.name}_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,${idx});
-        uint64_t PC = pc.val;
-        <%instr.fields.eachLine{%>${it}
-        <%}%>if(this->disass_enabled){
-            /* generate console output when executing the command */<%instr.disass.eachLine{%>
-            ${it}<%}%>
-            tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
-        }
-        auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc=pc+ ${instr.length/8};
-        gen_set_pc(tu, pc, traits::NEXT_PC);
-        tu.open_scope();
-        this->gen_set_tval(tu, instr);
-        <%instr.behavior.eachLine{%>${it}
-        <%}%>
-        tu.close_scope();
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
-        gen_trap_check(tu);        
-        return returnValue;
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    compile_ret_t illegal_instruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
-        vm_impl::gen_sync(tu, iss::PRE_SYNC, instr_descr.size());
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, std::string("illegal_instruction"));
-        }
-        pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
-        this->gen_set_tval(tu, instr);
-        vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
-        vm_impl::gen_trap_check(tu);
-        return ILLEGAL_INSTR;
-    }
-};
-
-template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
-    volatile CODE_WORD x = instr;
-    instr = 2 * x;
-}
-
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
-
-template <typename ARCH>
-vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id)
-, instr_decoder([this]() {
-        std::vector<generic_instruction_descriptor> g_instr_descr;
-        g_instr_descr.reserve(instr_descr.size());
-        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
-            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
-            g_instr_descr.push_back(new_instr_descr);
-        }
-        return std::move(g_instr_descr);
-    }()) {}
-
-template <typename ARCH>
-std::tuple<continuation_e>
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
-    // we fetch at max 4 byte, alignment is 2
-    enum {TRAP_ID=1<<16};
-    code_word_t instr = 0;
-    phys_addr_t paddr(pc);
-    if(this->core.has_mmu())
-        paddr = this->core.virt2phys(pc);
-    auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
-    if (res != iss::Ok)
-        return ILLEGAL_FETCH;
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001) 
-        return JUMP_TO_SELF;
-    ++inst_cnt;
-    uint32_t inst_index = instr_decoder.decode_instr(instr);
-    compile_func f = nullptr;
-    if(inst_index < instr_descr.size())
-        f = instr_descr[inst_index].op;
-    if (f == nullptr) {
-        f = &this_class::illegal_instruction;
-    }
-    return (this->*f)(pc, instr, tu);
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
-    tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
-    tu("leave_trap(core_ptr, {});", lvl);
-    tu.store(traits::NEXT_PC, tu.read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN));
-    tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP), 32));
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, uint64_t new_tval) {
-    tu(fmt::format("tval = {};", new_tval));
-}
-template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, value new_tval) {
-    tu(fmt::format("tval = {};", new_tval.str));
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
-    tu("trap_entry:");
-    this->gen_sync(tu, POST_SYNC, -1);    
-    tu("enter_trap(core_ptr, *trap_state, *pc, tval);");
-    tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP),32));
-    tu("return *next_pc;");
-}
-<%
-if(fcsr != null) {%>
-template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
-    std::ostringstream os;
-    os << "uint32_t (*fget_flags)()=" << (uintptr_t)&fget_flags << ";\\n";
-    os << "uint32_t (*fadd_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fadd_s << ";\\n";
-    os << "uint32_t (*fsub_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fsub_s << ";\\n";
-    os << "uint32_t (*fmul_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fmul_s << ";\\n";
-    os << "uint32_t (*fdiv_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_s << ";\\n";
-    os << "uint32_t (*fsqrt_s)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_s << ";\\n";
-    os << "uint32_t (*fcmp_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fcmp_s << ";\\n";
-    os << "uint32_t (*fcvt_s)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_s << ";\\n";
-    os << "uint32_t (*fmadd_s)(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_s << ";\\n";
-    os << "uint32_t (*fsel_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fsel_s << ";\\n";
-    os << "uint32_t (*fclass_s)( uint32_t v1 )=" << (uintptr_t)&fclass_s << ";\\n";
-    os << "uint32_t (*fconv_d2f)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fconv_d2f << ";\\n";
-    os << "uint64_t (*fconv_f2d)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fconv_f2d << ";\\n";
-    os << "uint64_t (*fadd_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fadd_d << ";\\n";
-    os << "uint64_t (*fsub_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fsub_d << ";\\n";
-    os << "uint64_t (*fmul_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fmul_d << ";\\n";
-    os << "uint64_t (*fdiv_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_d << ";\\n";
-    os << "uint64_t (*fsqrt_d)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_d << ";\\n";
-    os << "uint64_t (*fcmp_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fcmp_d << ";\\n";
-    os << "uint64_t (*fcvt_d)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_d << ";\\n";
-    os << "uint64_t (*fmadd_d)(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_d << ";\\n";
-    os << "uint64_t (*fsel_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fsel_d << ";\\n";
-    os << "uint64_t (*fclass_d)(uint64_t v1  )=" << (uintptr_t)&fclass_d << ";\\n";
-    os << "uint64_t (*fcvt_32_64)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_32_64 << ";\\n";
-    os << "uint32_t (*fcvt_64_32)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_64_32 << ";\\n";
-    os << "uint32_t (*unbox_s)(uint64_t v)=" << (uintptr_t)&unbox_s << ";\\n";
-    tu.add_prologue(os.str());
-}
-<%}%>
-
-} // namespace ${coreDef.name.toLowerCase()}
-
-template <>
-std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
-    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
-    return std::unique_ptr<vm_if>(ret);
-}
-} // namesapce tcc
-} // namespace iss
-
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-#include <iss/factory.h>
-namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        })
-};
-}
-}
-// clang-format on

gen_input/templates/tcc/CORENAME_cyles.txt.gtl

@@ -0,0 +1,9 @@
+{ 
+	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
+		{
+			"name"  : "${instr.name}",
+			"size"  : ${instr.length},
+			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
+		}<%}%>
+	]
+}

gen_input/templates/tcc/incl-CORENAME.h.gtl

@@ -0,0 +1,223 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+<% 
+import com.minres.coredsl.coreDsl.Register
+import com.minres.coredsl.coreDsl.RegisterFile
+import com.minres.coredsl.coreDsl.RegisterAlias
+def getTypeSize(size){
+	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
+}
+def getOriginalName(reg){
+    if( reg.original instanceof RegisterFile) {
+    	if( reg.index != null ) {
+        	return reg.original.name+generator.generateHostCode(reg.index)
+        } else {
+        	return reg.original.name
+        }
+    } else if(reg.original instanceof Register){
+        return reg.original.name
+    }
+}
+def getRegisterNames(){
+	def regNames = []
+ 	allRegs.each { reg -> 
+		if( reg instanceof RegisterFile) {
+			(reg.range.right..reg.range.left).each{
+    			regNames+=reg.name.toLowerCase()+it
+            }
+        } else if(reg instanceof Register){
+    		regNames+=reg.name.toLowerCase()
+        }
+    }
+    return regNames
+}
+def getRegisterAliasNames(){
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
+		if( reg instanceof RegisterFile) {
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
+        } else if(reg instanceof Register){
+    		regMap[reg.name]?:reg.name.toLowerCase()
+        }
+ 	}.flatten()
+}
+%>
+#ifndef _${coreDef.name.toUpperCase()}_H_
+#define _${coreDef.name.toUpperCase()}_H_
+
+#include <array>
+#include <iss/arch/traits.h>
+#include <iss/arch_if.h>
+#include <iss/vm_if.h>
+
+namespace iss {
+namespace arch {
+
+struct ${coreDef.name.toLowerCase()};
+
+template <> struct traits<${coreDef.name.toLowerCase()}> {
+
+	constexpr static char const* const core_type = "${coreDef.name}";
+    
+  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
+ 		{"${getRegisterNames().join("\", \"")}"}};
+ 
+  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
+ 		{"${getRegisterAliasNames().join("\", \"")}"}};
+
+    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
+
+    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
+
+    enum reg_e {<%
+     	allRegs.each { reg -> 
+    		if( reg instanceof RegisterFile) {
+    			(reg.range.right..reg.range.left).each{%>
+        ${reg.name}${it},<%
+                }
+            } else if(reg instanceof Register){ %>
+        ${reg.name},<%  
+            }
+        }%>
+        NUM_REGS,
+        NEXT_${pc.name}=NUM_REGS,
+        TRAP_STATE,
+        PENDING_TRAP,
+        MACHINE_STATE,
+        LAST_BRANCH,
+        ICOUNT<% 
+     	allRegs.each { reg -> 
+    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
+        ${reg.name} = ${aliasname}<%
+            }
+        }%>
+    };
+
+    using reg_t = uint${regDataWidth}_t;
+
+    using addr_t = uint${addrDataWidth}_t;
+
+    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
+
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
+
+ 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
+ 		{${regSizes.join(",")}}};
+
+    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
+    	{${regOffsets.join(",")}}};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
+};
+
+struct ${coreDef.name.toLowerCase()}: public arch_if {
+
+    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
+    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
+    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
+    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
+
+    ${coreDef.name.toLowerCase()}();
+    ~${coreDef.name.toLowerCase()}();
+
+    void reset(uint64_t address=0) override;
+
+    uint8_t* get_regs_base_ptr() override;
+    /// deprecated
+    void get_reg(short idx, std::vector<uint8_t>& value) override {}
+    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
+    /// deprecated
+    bool get_flag(int flag) override {return false;}
+    void set_flag(int, bool value) override {};
+    /// deprecated
+    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
+
+    inline uint64_t get_icount() { return reg.icount; }
+
+    inline bool should_stop() { return interrupt_sim; }
+
+    inline uint64_t stop_code() { return interrupt_sim; }
+
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
+
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
+
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
+protected:
+    struct ${coreDef.name}_regs {<%
+     	allRegs.each { reg -> 
+    		if( reg instanceof RegisterFile) {
+    			(reg.range.right..reg.range.left).each{%>
+        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
+                }
+            } else if(reg instanceof Register){ %>
+        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
+            }
+        }%>
+        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
+        uint64_t icount = 0;
+    } reg;
+
+    std::array<address_type, 4> addr_mode;
+    
+    uint64_t interrupt_sim=0;
+<%
+def fcsr = allRegs.find {it.name=='FCSR'}
+if(fcsr != null) {%>
+	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
+	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
+<%} else { %>
+	uint32_t get_fcsr(){return 0;}
+	void set_fcsr(uint32_t val){}
+<%}%>
+};
+
+}
+}            
+#endif /* _${coreDef.name.toUpperCase()}_H_ */

gen_input/templates/tcc/src-CORENAME.cpp.gtl

@@ -0,0 +1,107 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+ <% 
+import com.minres.coredsl.coreDsl.Register
+import com.minres.coredsl.coreDsl.RegisterFile
+import com.minres.coredsl.coreDsl.RegisterAlias
+def getOriginalName(reg){
+    if( reg.original instanceof RegisterFile) {
+    	if( reg.index != null ) {
+        	return reg.original.name+generator.generateHostCode(reg.index)
+        } else {
+        	return reg.original.name
+        }
+    } else if(reg.original instanceof Register){
+        return reg.original.name
+    }
+}
+def getRegisterNames(){
+	def regNames = []
+ 	allRegs.each { reg -> 
+		if( reg instanceof RegisterFile) {
+			(reg.range.right..reg.range.left).each{
+    			regNames+=reg.name.toLowerCase()+it
+            }
+        } else if(reg instanceof Register){
+    		regNames+=reg.name.toLowerCase()
+        }
+    }
+    return regNames
+}
+def getRegisterAliasNames(){
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
+		if( reg instanceof RegisterFile) {
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
+        } else if(reg instanceof Register){
+    		regMap[reg.name]?:reg.name.toLowerCase()
+        }
+ 	}.flatten()
+}
+%>
+#include "util/ities.h"
+#include <util/logging.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <cstdio>
+#include <cstring>
+#include <fstream>
+
+using namespace iss::arch;
+
+constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
+
+${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
+    reg.icount = 0;
+}
+
+${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
+
+void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
+    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
+    reg.PC=address;
+    reg.NEXT_PC=reg.PC;
+    reg.trap_state=0;
+    reg.machine_state=0x3;
+    reg.icount=0;
+}
+
+uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
+	return reinterpret_cast<uint8_t*>(&reg);
+}
+
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
+    return phys_addr_t(pc); // change logical address to physical address
+}
+

gen_input/templates/tcc/vm-vm_CORENAME.cpp.gtl

@@ -0,0 +1,291 @@
+/*******************************************************************************
+ * Copyright (C) 2020 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/server.h>
+#include <iss/iss.h>
+#include <iss/tcc/vm_base.h>
+#include <util/logging.h>
+#include <sstream>
+
+#ifndef FMT_HEADER_ONLY
+#define FMT_HEADER_ONLY
+#endif
+#include <fmt/format.h>
+
+#include <array>
+#include <iss/debugger/riscv_target_adapter.h>
+
+namespace iss {
+namespace tcc {
+namespace ${coreDef.name.toLowerCase()} {
+using namespace iss::arch;
+using namespace iss::debugger;
+
+template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
+public:
+    using super       = typename iss::tcc::vm_base<ARCH>;
+    using virt_addr_t = typename super::virt_addr_t;
+    using phys_addr_t = typename super::phys_addr_t;
+    using code_word_t = typename super::code_word_t;
+    using addr_t      = typename super::addr_t;
+    using tu_builder  = typename super::tu_builder;
+
+    vm_impl();
+
+    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
+
+    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
+
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
+        debugger_if::dbg_enabled = true;
+        if (vm_base<ARCH>::tgt_adapter == nullptr)
+            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
+        return vm_base<ARCH>::tgt_adapter;
+    }
+
+protected:
+    using vm_base<ARCH>::get_reg_ptr;
+
+    using this_class = vm_impl<ARCH>;
+    using compile_ret_t = std::tuple<continuation_e>;
+    using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
+
+    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
+
+    void setup_module(std::string m) override {
+        super::setup_module(m);
+    }
+
+    compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, tu_builder&) override;
+
+    void gen_trap_behavior(tu_builder& tu) override;
+
+    void gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause);
+
+    void gen_leave_trap(tu_builder& tu, unsigned lvl);
+
+    void gen_wait(tu_builder& tu, unsigned type);
+
+    inline void gen_trap_check(tu_builder& tu) {
+        tu("if(*trap_state!=0) goto trap_entry;");
+    }
+
+    inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
+        switch(reg_num){
+        case traits<ARCH>::NEXT_PC:
+            tu("*next_pc = {:#x};", pc.val);
+            break;
+        case traits<ARCH>::PC:
+            tu("*pc = {:#x};", pc.val);
+            break;
+        default:
+            if(!tu.defined_regs[reg_num]){
+                tu("reg_t* reg{:02d} = (reg_t*){:#x};", reg_num, reinterpret_cast<uintptr_t>(get_reg_ptr(reg_num)));
+            tu.defined_regs[reg_num]=true;
+            }
+            tu("*reg{:02d} = {:#x};", reg_num, pc.val);
+        }
+    }
+
+    // some compile time constants
+    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
+    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
+    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
+    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
+
+    std::array<compile_func, LUT_SIZE> lut;
+
+    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
+    std::array<compile_func, LUT_SIZE> lut_11;
+
+    std::array<compile_func *, 4> qlut;
+
+    std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
+
+    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
+                         compile_func f) {
+        if (pos < 0) {
+            lut[idx] = f;
+        } else {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
+            } else {
+                if ((valid & bitmask) == 0) {
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
+                } else {
+                    auto new_val = idx << 1;
+                    if ((value & bitmask) != 0) new_val++;
+                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
+                }
+            }
+        }
+    }
+
+    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
+
+    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
+        if (pos >= 0) {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                lut_val = extract_fields(pos - 1, val, mask, lut_val);
+            } else {
+                auto new_val = lut_val << 1;
+                if ((val & bitmask) != 0) new_val++;
+                lut_val = extract_fields(pos - 1, val, mask, new_val);
+            }
+        }
+        return lut_val;
+    }
+
+private:
+    /****************************************************************************
+     * start opcode definitions
+     ****************************************************************************/
+    struct InstructionDesriptor {
+        size_t length;
+        uint32_t value;
+        uint32_t mask;
+        compile_func op;
+    };
+
+    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
+         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
+        {${instr.length}, 0b${instr.value}, 0b${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+    }};
+ 
+    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
+    /* instruction ${idx}: ${instr.name} */
+    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){<%instr.code.eachLine{%>
+        ${it}<%}%>
+    }
+    <%}%>
+    /****************************************************************************
+     * end opcode definitions
+     ****************************************************************************/
+    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
+        vm_impl::gen_sync(tu, iss::PRE_SYNC, instr_descr.size());
+        pc = pc + ((instr & 3) == 3 ? 4 : 2);
+        gen_raise_trap(tu, 0, 2);     // illegal instruction trap
+        vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
+        vm_impl::gen_trap_check(tu);
+        return BRANCH;
+    }
+};
+
+template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
+    volatile CODE_WORD x = insn;
+    insn = 2 * x;
+}
+
+template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
+
+template <typename ARCH>
+vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
+: vm_base<ARCH>(core, core_id, cluster_id) {
+    qlut[0] = lut_00.data();
+    qlut[1] = lut_01.data();
+    qlut[2] = lut_10.data();
+    qlut[3] = lut_11.data();
+    for (auto instr : instr_descr) {
+        auto quantrant = instr.value & 0x3;
+        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
+    }
+}
+
+template <typename ARCH>
+std::tuple<continuation_e>
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
+    // we fetch at max 4 byte, alignment is 2
+    enum {TRAP_ID=1<<16};
+    code_word_t insn = 0;
+    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
+    phys_addr_t paddr(pc);
+    auto *const data = (uint8_t *)&insn;
+    paddr = this->core.v2p(pc);
+    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+        auto res = this->core.read(paddr, 2, data);
+        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
+            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+        }
+    } else {
+        auto res = this->core.read(paddr, 4, data);
+        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+    }
+    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    // curr pc on stack
+    ++inst_cnt;
+    auto lut_val = extract_fields(insn);
+    auto f = qlut[insn & 0x3][lut_val];
+    if (f == nullptr) {
+        f = &this_class::illegal_intruction;
+    }
+    return (this->*f)(pc, insn, tu);
+}
+
+template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
+    tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
+    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
+}
+
+template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
+    tu("leave_trap(core_ptr, {});", lvl);
+    tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
+    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
+}
+
+template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
+}
+
+template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
+    tu("trap_entry:");
+    tu("enter_trap(core_ptr, *trap_state, *pc);");
+    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
+    tu("return *next_pc;");
+}
+
+} // namespace mnrv32
+
+template <>
+std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
+    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
+    return std::unique_ptr<vm_if>(ret);
+}
+}
+} // namespace iss

incl/iss/arch/riscv_hart_m_p.h

@@ -0,0 +1,944 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial implementation
+ ******************************************************************************/
+
+#ifndef _RISCV_CORE_H_
+#define _RISCV_CORE_H_
+
+#include "iss/arch/traits.h"
+#include "iss/arch_if.h"
+#include "iss/instrumentation_if.h"
+#include "iss/log_categories.h"
+#include "iss/vm_if.h"
+#ifndef FMT_HEADER_ONLY
+#define FMT_HEADER_ONLY
+#endif
+#include <array>
+#include <elfio/elfio.hpp>
+#include <fmt/format.h>
+#include <iomanip>
+#include <sstream>
+#include <type_traits>
+#include <unordered_map>
+#include <util/bit_field.h>
+#include <util/ities.h>
+#include <util/sparse_array.h>
+
+#if defined(__GNUC__)
+#define likely(x) __builtin_expect(!!(x), 1)
+#define unlikely(x) __builtin_expect(!!(x), 0)
+#else
+#define likely(x) x
+#define unlikely(x) x
+#endif
+
+namespace iss {
+namespace arch {
+
+enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
+
+enum riscv_csr {
+    /* user-level CSR */
+    // User Trap Setup
+    ustatus = 0x000,
+    uie = 0x004,
+    utvec = 0x005,
+    // User Trap Handling
+    uscratch = 0x040,
+    uepc = 0x041,
+    ucause = 0x042,
+    utval = 0x043,
+    uip = 0x044,
+    // User Floating-Point CSRs
+    fflags = 0x001,
+    frm = 0x002,
+    fcsr = 0x003,
+    // User Counter/Timers
+    cycle = 0xC00,
+    time = 0xC01,
+    instret = 0xC02,
+    hpmcounter3 = 0xC03,
+    hpmcounter4 = 0xC04,
+    /*...*/
+    hpmcounter31 = 0xC1F,
+    cycleh = 0xC80,
+    timeh = 0xC81,
+    instreth = 0xC82,
+    hpmcounter3h = 0xC83,
+    hpmcounter4h = 0xC84,
+    /*...*/
+    hpmcounter31h = 0xC9F,
+    /* supervisor-level CSR */
+    // Supervisor Trap Setup
+    sstatus = 0x100,
+    sedeleg = 0x102,
+    sideleg = 0x103,
+    sie = 0x104,
+    stvec = 0x105,
+    scounteren = 0x106,
+    // Supervisor Trap Handling
+    sscratch = 0x140,
+    sepc = 0x141,
+    scause = 0x142,
+    stval = 0x143,
+    sip = 0x144,
+    // Supervisor Protection and Translation
+    satp = 0x180,
+    /* machine-level CSR */
+    // Machine Information Registers
+    mvendorid = 0xF11,
+    marchid = 0xF12,
+    mimpid = 0xF13,
+    mhartid = 0xF14,
+    // Machine Trap Setup
+    mstatus = 0x300,
+    misa = 0x301,
+    medeleg = 0x302,
+    mideleg = 0x303,
+    mie = 0x304,
+    mtvec = 0x305,
+    mcounteren = 0x306,
+    // Machine Trap Handling
+    mscratch = 0x340,
+    mepc = 0x341,
+    mcause = 0x342,
+    mtval = 0x343,
+    mip = 0x344,
+    // Machine Protection and Translation
+    pmpcfg0 = 0x3A0,
+    pmpcfg1 = 0x3A1,
+    pmpcfg2 = 0x3A2,
+    pmpcfg3 = 0x3A3,
+    pmpaddr0 = 0x3B0,
+    pmpaddr1 = 0x3B1,
+    /*...*/
+    pmpaddr15 = 0x3BF,
+    // Machine Counter/Timers
+    mcycle = 0xB00,
+    minstret = 0xB02,
+    mhpmcounter3 = 0xB03,
+    mhpmcounter4 = 0xB04,
+    /*...*/
+    mhpmcounter31 = 0xB1F,
+    mcycleh = 0xB80,
+    minstreth = 0xB82,
+    mhpmcounter3h = 0xB83,
+    mhpmcounter4h = 0xB84,
+    /*...*/
+    mhpmcounter31h = 0xB9F,
+    // Machine Counter Setup
+    mhpmevent3 = 0x323,
+    mhpmevent4 = 0x324,
+    /*...*/
+    mhpmevent31 = 0x33F,
+    // Debug/Trace Registers (shared with Debug Mode)
+    tselect = 0x7A0,
+    tdata1 = 0x7A1,
+    tdata2 = 0x7A2,
+    tdata3 = 0x7A3,
+    // Debug Mode Registers
+    dcsr = 0x7B0,
+    dpc = 0x7B1,
+    dscratch = 0x7B2
+};
+
+namespace {
+
+std::array<const char *, 16> trap_str = {{""
+                                          "Instruction address misaligned", // 0
+                                          "Instruction access fault",       // 1
+                                          "Illegal instruction",            // 2
+                                          "Breakpoint",                     // 3
+                                          "Load address misaligned",        // 4
+                                          "Load access fault",              // 5
+                                          "Store/AMO address misaligned",   // 6
+                                          "Store/AMO access fault",         // 7
+                                          "Environment call from U-mode",   // 8
+                                          "Environment call from S-mode",   // 9
+                                          "Reserved",                       // a
+                                          "Environment call from M-mode",   // b
+                                          "Instruction page fault",         // c
+                                          "Load page fault",                // d
+                                          "Reserved",                       // e
+                                          "Store/AMO page fault"}};
+std::array<const char *, 12> irq_str = {
+    {"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
+     "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
+     "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
+
+enum {
+    PGSHIFT = 12,
+    PTE_PPN_SHIFT = 10,
+    // page table entry (PTE) fields
+    PTE_V = 0x001,   // Valid
+    PTE_R = 0x002,   // Read
+    PTE_W = 0x004,   // Write
+    PTE_X = 0x008,   // Execute
+    PTE_U = 0x010,   // User
+    PTE_G = 0x020,   // Global
+    PTE_A = 0x040,   // Accessed
+    PTE_D = 0x080,   // Dirty
+    PTE_SOFT = 0x300 // Reserved for Software
+};
+
+template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
+
+enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3 };
+
+enum {
+    ISA_A = 1,
+    ISA_B = 1 << 1,
+    ISA_C = 1 << 2,
+    ISA_D = 1 << 3,
+    ISA_E = 1 << 4,
+    ISA_F = 1 << 5,
+    ISA_G = 1 << 6,
+    ISA_I = 1 << 8,
+    ISA_M = 1 << 12,
+    ISA_N = 1 << 13,
+    ISA_Q = 1 << 16,
+    ISA_S = 1 << 18,
+    ISA_U = 1 << 20
+};
+
+class trap_load_access_fault : public trap_access {
+public:
+    trap_load_access_fault(uint64_t badaddr)
+    : trap_access(5 << 16, badaddr) {}
+};
+class illegal_instruction_fault : public trap_access {
+public:
+    illegal_instruction_fault(uint64_t badaddr)
+    : trap_access(2 << 16, badaddr) {}
+};
+} // namespace
+
+template <typename BASE> class riscv_hart_m_p : public BASE {
+public:
+    using super = BASE;
+    using this_class = riscv_hart_m_p<BASE>;
+    using phys_addr_t = typename super::phys_addr_t;
+    using reg_t = typename super::reg_t;
+    using addr_t = typename super::addr_t;
+
+    using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
+    using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
+
+    // primary template
+    template <class T, class Enable = void> struct hart_state {};
+    // specialization 32bit
+    template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint32_t>::value>::type> {
+    public:
+        BEGIN_BF_DECL(mstatus_t, T);
+        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
+        BF_FIELD(SD, 31, 1);
+        // Trap SRET
+        BF_FIELD(TSR, 22, 1);
+        // Timeout Wait
+        BF_FIELD(TW, 21, 1);
+        // Trap Virtual Memory
+        BF_FIELD(TVM, 20, 1);
+        // Make eXecutable Readable
+        BF_FIELD(MXR, 19, 1);
+        // permit Supervisor User Memory access
+        BF_FIELD(SUM, 18, 1);
+        // Modify PRiVilege
+        BF_FIELD(MPRV, 17, 1);
+        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
+        BF_FIELD(XS, 15, 2);
+        // floating-point unit status Off/Initial/Clean/Dirty
+        BF_FIELD(FS, 13, 2);
+        // machine previous privilege
+        BF_FIELD(MPP, 11, 2);
+        // supervisor previous privilege
+        BF_FIELD(SPP, 8, 1);
+        // previous machine interrupt-enable
+        BF_FIELD(MPIE, 7, 1);
+        // previous supervisor interrupt-enable
+        BF_FIELD(SPIE, 5, 1);
+        // previous user interrupt-enable
+        BF_FIELD(UPIE, 4, 1);
+        // machine interrupt-enable
+        BF_FIELD(MIE, 3, 1);
+        // supervisor interrupt-enable
+        BF_FIELD(SIE, 1, 1);
+        // user interrupt-enable
+        BF_FIELD(UIE, 0, 1);
+        END_BF_DECL();
+
+        mstatus_t mstatus;
+
+        static const reg_t mstatus_reset_val = 0;
+
+        void write_mstatus(T val) {
+            auto mask = get_mask();
+            auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
+            mstatus = new_val;
+        }
+
+        T satp;
+
+        static constexpr T get_misa() { return (1UL << 30) | ISA_I | ISA_M | ISA_A | ISA_U | ISA_S | ISA_M; }
+
+        static constexpr uint32_t get_mask() {
+            return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011  // only machine mode is supported
+        }
+    };
+
+    constexpr reg_t get_irq_mask() {
+        return 0b101110111011; // only machine mode is supported
+    }
+
+    riscv_hart_m_p();
+    virtual ~riscv_hart_m_p() = default;
+
+    void reset(uint64_t address) override;
+
+    std::pair<uint64_t, bool> load_file(std::string name, int type = -1) override;
+
+    iss::status read(const address_type type, const access_type access, const uint32_t space,
+            const uint64_t addr, const unsigned length, uint8_t *const data) override;
+    iss::status write(const address_type type, const access_type access, const uint32_t space,
+            const uint64_t addr, const unsigned length, const uint8_t *const data) override;
+
+    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data); }
+    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr) override;
+    virtual uint64_t leave_trap(uint64_t flags) override;
+
+    const reg_t& get_mhartid() const { return mhartid_reg;	}
+	void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
+
+    void disass_output(uint64_t pc, const std::string instr) override {
+        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [s:0x{:x};c:{}]",
+                pc, instr, (reg_t)state.mstatus, this->reg.icount);
+    };
+
+    iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
+ 
+protected:
+    struct riscv_instrumentation_if : public iss::instrumentation_if {
+
+        riscv_instrumentation_if(riscv_hart_m_p<BASE> &arch)
+        : arch(arch) {}
+        /**
+         * get the name of this architecture
+         *
+         * @return the name of this architecture
+         */
+        const std::string core_type_name() const override { return traits<BASE>::core_type; }
+
+        virtual uint64_t get_pc() { return arch.get_pc(); };
+
+        virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
+
+        virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
+
+        riscv_hart_m_p<BASE> &arch;
+    };
+
+    friend struct riscv_instrumentation_if;
+    addr_t get_pc() { return this->reg.PC; }
+    addr_t get_next_pc() { return this->reg.NEXT_PC; }
+
+    virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
+    virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
+
+    virtual iss::status read_csr(unsigned addr, reg_t &val);
+    virtual iss::status write_csr(unsigned addr, reg_t val);
+
+    hart_state<reg_t> state;
+    uint64_t cycle_offset;
+    reg_t fault_data;
+    uint64_t tohost = tohost_dflt;
+    uint64_t fromhost = fromhost_dflt;
+    unsigned to_host_wr_cnt = 0;
+    riscv_instrumentation_if instr_if;
+
+    using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
+    using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
+    using csr_page_type = typename csr_type::page_type;
+    mem_type mem;
+    csr_type csr;
+    std::stringstream uart_buf;
+    std::unordered_map<reg_t, uint64_t> ptw;
+    std::unordered_map<uint64_t, uint8_t> atomic_reservation;
+    std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
+    std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
+
+private:
+    iss::status read_cycle(unsigned addr, reg_t &val);
+    iss::status read_time(unsigned addr, reg_t &val);
+    iss::status read_status(unsigned addr, reg_t &val);
+    iss::status write_status(unsigned addr, reg_t val);
+    iss::status read_ie(unsigned addr, reg_t &val);
+    iss::status write_ie(unsigned addr, reg_t val);
+    iss::status read_ip(unsigned addr, reg_t &val);
+    iss::status write_ip(unsigned addr, reg_t val);
+    iss::status read_hartid(unsigned addr, reg_t &val);
+
+    reg_t mhartid_reg{0xF};
+
+protected:
+    void check_interrupt();
+};
+
+template <typename BASE>
+riscv_hart_m_p<BASE>::riscv_hart_m_p()
+: state()
+, cycle_offset(0)
+, instr_if(*this) {
+    csr[misa] = hart_state<reg_t>::get_misa();
+    uart_buf.str("");
+    // read-only registers
+    csr_wr_cb[misa] = nullptr;
+    for (unsigned addr = mcycle; addr <= hpmcounter31; ++addr) csr_wr_cb[addr] = nullptr;
+    for (unsigned addr = mcycleh; addr <= hpmcounter31h; ++addr) csr_wr_cb[addr] = nullptr;
+    // special handling
+    csr_rd_cb[time] = &riscv_hart_m_p<BASE>::read_time;
+    csr_wr_cb[time] = nullptr;
+    csr_rd_cb[timeh] = &riscv_hart_m_p<BASE>::read_time;
+    csr_wr_cb[timeh] = nullptr;
+    csr_rd_cb[mcycle] = &riscv_hart_m_p<BASE>::read_cycle;
+    csr_rd_cb[mcycleh] = &riscv_hart_m_p<BASE>::read_cycle;
+    csr_rd_cb[minstret] = &riscv_hart_m_p<BASE>::read_cycle;
+    csr_rd_cb[minstreth] = &riscv_hart_m_p<BASE>::read_cycle;
+    csr_rd_cb[mstatus] = &riscv_hart_m_p<BASE>::read_status;
+    csr_wr_cb[mstatus] = &riscv_hart_m_p<BASE>::write_status;
+    csr_rd_cb[mip] = &riscv_hart_m_p<BASE>::read_ip;
+    csr_wr_cb[mip] = &riscv_hart_m_p<BASE>::write_ip;
+    csr_rd_cb[mie] = &riscv_hart_m_p<BASE>::read_ie;
+    csr_wr_cb[mie] = &riscv_hart_m_p<BASE>::write_ie;
+    csr_rd_cb[mhartid] = &riscv_hart_m_p<BASE>::read_hartid;
+}
+
+template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
+    FILE *fp = fopen(name.c_str(), "r");
+    if (fp) {
+        std::array<char, 5> buf;
+        auto n = fread(buf.data(), 1, 4, fp);
+        if (n != 4) throw std::runtime_error("input file has insufficient size");
+        buf[4] = 0;
+        if (strcmp(buf.data() + 1, "ELF") == 0) {
+            fclose(fp);
+            // Create elfio reader
+            ELFIO::elfio reader;
+            // Load ELF data
+            if (!reader.load(name)) throw std::runtime_error("could not process elf file");
+            // check elf properties
+            if (reader.get_class() != ELFCLASS32)
+                if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
+            if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
+            if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
+            for (const auto pseg : reader.segments) {
+                const auto fsize = pseg->get_file_size(); // 0x42c/0x0
+                const auto seg_data = pseg->get_data();
+                if (fsize > 0) {
+                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE,
+                            traits<BASE>::MEM, pseg->get_physical_address(),
+                            fsize, reinterpret_cast<const uint8_t *const>(seg_data));
+                    if (res != iss::Ok)
+                        LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex
+                                   << pseg->get_physical_address();
+                }
+            }
+            for (const auto sec : reader.sections) {
+                if (sec->get_name() == ".tohost") {
+                    tohost = sec->get_address();
+                    fromhost = tohost + 0x40;
+                }
+            }
+
+            return std::make_pair(reader.get_entry(), true);
+        }
+        throw std::runtime_error("memory load file is not a valid elf file");
+    }
+    throw std::runtime_error("memory load file not found");
+}
+
+template <typename BASE>
+iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_type access, const uint32_t space,
+        const uint64_t addr, const unsigned length, uint8_t *const data) {
+#ifndef NDEBUG
+    if (access && iss::access_type::DEBUG) {
+        LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
+    } else if(access && iss::access_type::FETCH){
+        LOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
+    } else {
+        LOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
+   }
+#endif
+    try {
+        switch (space) {
+        case traits<BASE>::MEM: {
+            if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
+                fault_data = addr;
+                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
+                this->reg.trap_state = (1 << 31); // issue trap 0
+                return iss::Err;
+            }
+            try {
+                auto res = type==iss::address_type::PHYSICAL?
+                        read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
+                        read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
+                if (unlikely(res != iss::Ok)) this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
+                return res;
+            } catch (trap_access &ta) {
+                this->reg.trap_state = (1 << 31) | ta.id;
+                return iss::Err;
+            }
+        } break;
+        case traits<BASE>::CSR: {
+            if (length != sizeof(reg_t)) return iss::Err;
+            return read_csr(addr, *reinterpret_cast<reg_t *const>(data));
+        } break;
+        case traits<BASE>::FENCE: {
+            if ((addr + length) > mem.size()) return iss::Err;
+            return iss::Ok;
+        } break;
+        case traits<BASE>::RES: {
+            auto it = atomic_reservation.find(addr);
+            if (it != atomic_reservation.end() && it->second != 0) {
+                memset(data, 0xff, length);
+                atomic_reservation.erase(addr);
+            } else
+                memset(data, 0, length);
+        } break;
+        default:
+            return iss::Err; // assert("Not supported");
+        }
+        return iss::Ok;
+    } catch (trap_access &ta) {
+        this->reg.trap_state = (1 << 31) | ta.id;
+        return iss::Err;
+    }
+}
+
+template <typename BASE>
+iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_type access, const uint32_t space,
+        const uint64_t addr, const unsigned length, const uint8_t *const data) {
+#ifndef NDEBUG
+    const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
+    switch (length) {
+    case 8:
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec
+                   << ") @addr 0x" << std::hex << addr;
+        break;
+    case 4:
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t *)&data[0] << std::dec
+                   << ") @addr 0x" << std::hex << addr;
+        break;
+    case 2:
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t *)&data[0] << std::dec
+                   << ") @addr 0x" << std::hex << addr;
+        break;
+    case 1:
+        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec
+                   << ") @addr 0x" << std::hex << addr;
+        break;
+    default:
+        LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
+    }
+#endif
+    try {
+        switch (space) {
+        case traits<BASE>::MEM: {
+            if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
+                fault_data = addr;
+                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
+                this->reg.trap_state = (1 << 31); // issue trap 0
+                return iss::Err;
+            }
+            try {
+                auto res = type==iss::address_type::PHYSICAL?
+                        write_mem(phys_addr_t{access, space, addr}, length, data):
+                        write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
+                if (unlikely(res != iss::Ok))
+                    this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 7 (Store/AMO access fault)
+                return res;
+            } catch (trap_access &ta) {
+                this->reg.trap_state = (1 << 31) | ta.id;
+                return iss::Err;
+            }
+
+            phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
+            if ((paddr.val + length) > mem.size()) return iss::Err;
+            switch (paddr.val) {
+            case 0x10013000: // UART0 base, TXFIFO reg
+            case 0x10023000: // UART1 base, TXFIFO reg
+                uart_buf << (char)data[0];
+                if (((char)data[0]) == '\n' || data[0] == 0) {
+                    // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
+                    // '"<<uart_buf.str()<<"'";
+                    std::cout << uart_buf.str();
+                    uart_buf.str("");
+                }
+                return iss::Ok;
+            case 0x10008000: { // HFROSC base, hfrosccfg reg
+                auto &p = mem(paddr.val / mem.page_size);
+                auto offs = paddr.val & mem.page_addr_mask;
+                std::copy(data, data + length, p.data() + offs);
+                auto &x = *(p.data() + offs + 3);
+                if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
+                return iss::Ok;
+            }
+            case 0x10008008: { // HFROSC base, pllcfg reg
+                auto &p = mem(paddr.val / mem.page_size);
+                auto offs = paddr.val & mem.page_addr_mask;
+                std::copy(data, data + length, p.data() + offs);
+                auto &x = *(p.data() + offs + 3);
+                x |= 0x80; // set pll lock upon writing
+                return iss::Ok;
+            } break;
+            default: {}
+            }
+        } break;
+        case traits<BASE>::CSR: {
+            if (length != sizeof(reg_t)) return iss::Err;
+            return write_csr(addr, *reinterpret_cast<const reg_t *>(data));
+        } break;
+        case traits<BASE>::FENCE: {
+            if ((addr + length) > mem.size()) return iss::Err;
+            switch (addr) {
+            case 2:
+            case 3: {
+                ptw.clear();
+                auto tvm = state.mstatus.TVM;
+                return iss::Ok;
+            }
+            }
+        } break;
+        case traits<BASE>::RES: {
+            atomic_reservation[addr] = data[0];
+        } break;
+        default:
+            return iss::Err;
+        }
+        return iss::Ok;
+    } catch (trap_access &ta) {
+        this->reg.trap_state = (1 << 31) | ta.id;
+        return iss::Err;
+    }
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned addr, reg_t &val) {
+    if (addr >= csr.size()) return iss::Err;
+    auto req_priv_lvl = (addr >> 8) & 0x3;
+    if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
+    auto it = csr_rd_cb.find(addr);
+    if (it == csr_rd_cb.end()) {
+        val = csr[addr & csr.page_addr_mask];
+        return iss::Ok;
+    }
+    rd_csr_f f = it->second;
+    if (f == nullptr) throw illegal_instruction_fault(this->fault_data);
+    return (this->*f)(addr, val);
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned addr, reg_t val) {
+    if (addr >= csr.size()) return iss::Err;
+    auto req_priv_lvl = (addr >> 8) & 0x3;
+    if (this->reg.machine_state < req_priv_lvl)
+        throw illegal_instruction_fault(this->fault_data);
+    if((addr&0xc00)==0xc00)
+        throw illegal_instruction_fault(this->fault_data);
+    auto it = csr_wr_cb.find(addr);
+    if (it == csr_wr_cb.end()) {
+        csr[addr & csr.page_addr_mask] = val;
+        return iss::Ok;
+    }
+    wr_csr_f f = it->second;
+    if (f == nullptr) throw illegal_instruction_fault(this->fault_data);
+    return (this->*f)(addr, val);
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
+    auto cycle_val = this->reg.icount + cycle_offset;
+    if (addr == mcycle) {
+        val = static_cast<reg_t>(cycle_val);
+    } else if (addr == mcycleh) {
+        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
+        val = static_cast<reg_t>(cycle_val >> 32);
+    }
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) {
+    uint64_t time_val = (this->reg.icount + cycle_offset) / (100000000 / 32768 - 1); //-> ~3052;
+    if (addr == time) {
+        val = static_cast<reg_t>(time_val);
+    } else if (addr == timeh) {
+        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
+        val = static_cast<reg_t>(time_val >> 32);
+    }
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_status(unsigned addr, reg_t &val) {
+    val = state.mstatus & hart_state<reg_t>::get_mask();
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_status(unsigned addr, reg_t val) {
+    state.write_mstatus(val);
+    check_interrupt();
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr, reg_t &val) {
+    val = csr[mie];
+    val &= csr[mideleg];
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_hartid(unsigned addr, reg_t &val) {
+    val = mhartid_reg;
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ie(unsigned addr, reg_t val) {
+    auto mask = get_irq_mask();
+    csr[mie] = (csr[mie] & ~mask) | (val & mask);
+    check_interrupt();
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ip(unsigned addr, reg_t &val) {
+    val = csr[mip];
+    val &= csr[mideleg];
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned addr, reg_t val) {
+    auto mask = get_irq_mask();
+    mask &= ~(1 << 7); // MTIP is read only
+    csr[mip] = (csr[mip] & ~mask) | (val & mask);
+    check_interrupt();
+    return iss::Ok;
+}
+
+template <typename BASE>
+iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
+    if ((paddr.val + length) > mem.size()) return iss::Err;
+    switch (paddr.val) {
+    case 0x0200BFF8: { // CLINT base, mtime reg
+        if (sizeof(reg_t) < length) return iss::Err;
+        reg_t time_val;
+        this->read_csr(time, time_val);
+        std::copy((uint8_t *)&time_val, ((uint8_t *)&time_val) + length, data);
+    } break;
+    case 0x10008000: {
+        const mem_type::page_type &p = mem(paddr.val / mem.page_size);
+        uint64_t offs = paddr.val & mem.page_addr_mask;
+        std::copy(p.data() + offs, p.data() + offs + length, data);
+        if (this->reg.icount > 30000) data[3] |= 0x80;
+    } break;
+    default: {
+        const auto &p = mem(paddr.val / mem.page_size);
+        auto offs = paddr.val & mem.page_addr_mask;
+        std::copy(p.data() + offs, p.data() + offs + length, data);
+    }
+    }
+    return iss::Ok;
+}
+
+template <typename BASE>
+iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
+    if ((paddr.val + length) > mem.size()) return iss::Err;
+    switch (paddr.val) {
+    case 0x10013000: // UART0 base, TXFIFO reg
+    case 0x10023000: // UART1 base, TXFIFO reg
+        uart_buf << (char)data[0];
+        if (((char)data[0]) == '\n' || data[0] == 0) {
+            // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
+            // '"<<uart_buf.str()<<"'";
+            std::cout << uart_buf.str();
+            uart_buf.str("");
+        }
+        break;
+    case 0x10008000: { // HFROSC base, hfrosccfg reg
+        mem_type::page_type &p = mem(paddr.val / mem.page_size);
+        size_t offs = paddr.val & mem.page_addr_mask;
+        std::copy(data, data + length, p.data() + offs);
+        uint8_t &x = *(p.data() + offs + 3);
+        if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
+    } break;
+    case 0x10008008: { // HFROSC base, pllcfg reg
+        mem_type::page_type &p = mem(paddr.val / mem.page_size);
+        size_t offs = paddr.val & mem.page_addr_mask;
+        std::copy(data, data + length, p.data() + offs);
+        uint8_t &x = *(p.data() + offs + 3);
+        x |= 0x80; // set pll lock upon writing
+    } break;
+    default: {
+        mem_type::page_type &p = mem(paddr.val / mem.page_size);
+        std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
+        // tohost handling in case of riscv-test
+        if (paddr.access && iss::access_type::FUNC) {
+            auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4));
+            auto tohost_lower =
+                (traits<BASE>::XLEN == 32 && paddr.val == tohost);
+            if (tohost_lower || tohost_upper) {
+                uint64_t hostvar = *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask));
+                if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
+                    switch (hostvar >> 48) {
+                    case 0:
+                        if (hostvar != 0x1) {
+                            LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
+                                       << "), stopping simulation";
+                        } else {
+                            LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
+                                      << "), stopping simulation";
+                        }
+                        this->reg.trap_state=std::numeric_limits<uint32_t>::max();
+                        this->interrupt_sim=hostvar;
+                        break;
+                        //throw(iss::simulation_stopped(hostvar));
+                    case 0x0101: {
+                        char c = static_cast<char>(hostvar & 0xff);
+                        if (c == '\n' || c == 0) {
+                            LOG(INFO) << "tohost send '" << uart_buf.str() << "'";
+                            uart_buf.str("");
+                        } else
+                            uart_buf << c;
+                        to_host_wr_cnt = 0;
+                    } break;
+                    default:
+                        break;
+                    }
+                } else if (tohost_lower)
+                    to_host_wr_cnt++;
+            } else if (traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) {
+                uint64_t fhostvar = *reinterpret_cast<uint64_t *>(p.data() + (fromhost & mem.page_addr_mask));
+                *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
+            }
+        }
+    }
+    }
+    return iss::Ok;
+}
+
+template <typename BASE> inline void riscv_hart_m_p<BASE>::reset(uint64_t address) {
+    BASE::reset(address);
+    state.mstatus = hart_state<reg_t>::mstatus_reset_val;
+}
+
+template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
+    auto ideleg = csr[mideleg];
+    // Multiple simultaneous interrupts and traps at the same privilege level are
+    // handled in the following decreasing priority order:
+    // external interrupts, software interrupts, timer interrupts, then finally
+    // any synchronous traps.
+    auto ena_irq = csr[mip] & csr[mie];
+
+    bool mie = state.mstatus.MIE;
+    auto m_enabled = this->reg.machine_state < PRIV_M || (this->reg.machine_state == PRIV_M && mie);
+    auto enabled_interrupts = m_enabled ? ena_irq & ~ideleg : 0;
+
+    if (enabled_interrupts != 0) {
+        int res = 0;
+        while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++;
+        this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
+    }
+}
+
+template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flags, uint64_t addr) {
+    // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
+    // calculate and write mcause val
+    auto trap_id = bit_sub<0, 16>(flags);
+    auto cause = bit_sub<16, 15>(flags);
+    if (trap_id == 0 && cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
+    // calculate effective privilege level
+    if (trap_id == 0) { // exception
+        // store ret addr in xepc register
+        csr[mepc] = static_cast<reg_t>(addr); // store actual address instruction of exception
+        csr[mtval] = fault_data;
+        fault_data = 0;
+    } else {
+        csr[mepc] = this->reg.NEXT_PC; // store next address if interrupt
+        this->reg.pending_trap = 0;
+    }
+    csr[mcause] = (trap_id << 31) + cause;
+    // update mstatus
+    // xPP field of mstatus is written with the active privilege mode at the time
+    // of the trap; the x PIE field of mstatus
+    // is written with the value of the active interrupt-enable bit at the time of
+    // the trap; and the x IE field of mstatus
+    // is cleared
+    // store the actual privilege level in yPP and store interrupt enable flags
+    state.mstatus.MPP = PRIV_M;
+    state.mstatus.MPIE = state.mstatus.MIE;
+    state.mstatus.MIE = false;
+
+    // get trap vector
+    auto ivec = csr[mtvec];
+    // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
+    // bits in mtvec
+    this->reg.NEXT_PC = ivec & ~0x1UL;
+    if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
+    // reset trap state
+    this->reg.machine_state = PRIV_M;
+    this->reg.trap_state = 0;
+    std::array<char, 32> buffer;
+    sprintf(buffer.data(), "0x%016lx", addr);
+    if((flags&0xffffffff) != 0xffffffff)
+    CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
+                       << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
+                       << " at address " << buffer.data() << " occurred";
+    return this->reg.NEXT_PC;
+}
+
+template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
+    auto cur_priv = this->reg.machine_state;
+    auto inst_priv = flags & 0x3;
+    auto status = state.mstatus;
+
+    // pop the relevant lower-privilege interrupt enable and privilege mode stack
+    // clear respective yIE
+    if (inst_priv == PRIV_M) {
+        this->reg.machine_state = state.mstatus.MPP;
+        state.mstatus.MPP = 0; // clear mpp to U mode
+        state.mstatus.MIE = state.mstatus.MPIE;
+    } else {
+    	CLOG(ERROR, disass) << "Unsupported mode:" << inst_priv;
+    }
+
+    // sets the pc to the value stored in the x epc register.
+    this->reg.NEXT_PC = csr[mepc];
+    CLOG(INFO, disass) << "Executing xRET";
+    return this->reg.NEXT_PC;
+}
+
+} // namespace arch
+} // namespace iss
+
+#endif /* _RISCV_CORE_H_ */

incl/iss/arch/tgf_b.h

@@ -0,0 +1,252 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+
+#ifndef _TGF_B_H_
+#define _TGF_B_H_
+
+#include <array>
+#include <iss/arch/traits.h>
+#include <iss/arch_if.h>
+#include <iss/vm_if.h>
+
+namespace iss {
+namespace arch {
+
+struct tgf_b;
+
+template <> struct traits<tgf_b> {
+
+	constexpr static char const* const core_type = "TGF_B";
+    
+  	static constexpr std::array<const char*, 33> reg_names{
+ 		{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
+ 
+  	static constexpr std::array<const char*, 33> reg_aliases{
+ 		{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
+
+    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000000000100000000, PGSIZE=0x1000, PGMASK=0xfff};
+
+    constexpr static unsigned FP_REGS_SIZE = 0;
+
+    enum reg_e {
+        X0,
+        X1,
+        X2,
+        X3,
+        X4,
+        X5,
+        X6,
+        X7,
+        X8,
+        X9,
+        X10,
+        X11,
+        X12,
+        X13,
+        X14,
+        X15,
+        X16,
+        X17,
+        X18,
+        X19,
+        X20,
+        X21,
+        X22,
+        X23,
+        X24,
+        X25,
+        X26,
+        X27,
+        X28,
+        X29,
+        X30,
+        X31,
+        PC,
+        NUM_REGS,
+        NEXT_PC=NUM_REGS,
+        TRAP_STATE,
+        PENDING_TRAP,
+        MACHINE_STATE,
+        LAST_BRANCH,
+        ICOUNT,
+        ZERO = X0,
+        RA = X1,
+        SP = X2,
+        GP = X3,
+        TP = X4,
+        T0 = X5,
+        T1 = X6,
+        T2 = X7,
+        S0 = X8,
+        S1 = X9,
+        A0 = X10,
+        A1 = X11,
+        A2 = X12,
+        A3 = X13,
+        A4 = X14,
+        A5 = X15,
+        A6 = X16,
+        A7 = X17,
+        S2 = X18,
+        S3 = X19,
+        S4 = X20,
+        S5 = X21,
+        S6 = X22,
+        S7 = X23,
+        S8 = X24,
+        S9 = X25,
+        S10 = X26,
+        S11 = X27,
+        T3 = X28,
+        T4 = X29,
+        T5 = X30,
+        T6 = X31
+    };
+
+    using reg_t = uint32_t;
+
+    using addr_t = uint32_t;
+
+    using code_word_t = uint32_t; //TODO: check removal
+
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
+
+ 	static constexpr std::array<const uint32_t, 39> reg_bit_widths{
+ 		{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
+
+    static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
+    	{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { MEM, CSR, FENCE, RES };
+};
+
+struct tgf_b: public arch_if {
+
+    using virt_addr_t = typename traits<tgf_b>::virt_addr_t;
+    using phys_addr_t = typename traits<tgf_b>::phys_addr_t;
+    using reg_t =  typename traits<tgf_b>::reg_t;
+    using addr_t = typename traits<tgf_b>::addr_t;
+
+    tgf_b();
+    ~tgf_b();
+
+    void reset(uint64_t address=0) override;
+
+    uint8_t* get_regs_base_ptr() override;
+    /// deprecated
+    void get_reg(short idx, std::vector<uint8_t>& value) override {}
+    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
+    /// deprecated
+    bool get_flag(int flag) override {return false;}
+    void set_flag(int, bool value) override {};
+    /// deprecated
+    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
+
+    inline uint64_t get_icount() { return reg.icount; }
+
+    inline bool should_stop() { return interrupt_sim; }
+
+    inline uint64_t stop_code() { return interrupt_sim; }
+
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<tgf_b>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf_b>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
+
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
+
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
+protected:
+    struct TGF_B_regs {
+        uint32_t X0 = 0;
+        uint32_t X1 = 0;
+        uint32_t X2 = 0;
+        uint32_t X3 = 0;
+        uint32_t X4 = 0;
+        uint32_t X5 = 0;
+        uint32_t X6 = 0;
+        uint32_t X7 = 0;
+        uint32_t X8 = 0;
+        uint32_t X9 = 0;
+        uint32_t X10 = 0;
+        uint32_t X11 = 0;
+        uint32_t X12 = 0;
+        uint32_t X13 = 0;
+        uint32_t X14 = 0;
+        uint32_t X15 = 0;
+        uint32_t X16 = 0;
+        uint32_t X17 = 0;
+        uint32_t X18 = 0;
+        uint32_t X19 = 0;
+        uint32_t X20 = 0;
+        uint32_t X21 = 0;
+        uint32_t X22 = 0;
+        uint32_t X23 = 0;
+        uint32_t X24 = 0;
+        uint32_t X25 = 0;
+        uint32_t X26 = 0;
+        uint32_t X27 = 0;
+        uint32_t X28 = 0;
+        uint32_t X29 = 0;
+        uint32_t X30 = 0;
+        uint32_t X31 = 0;
+        uint32_t PC = 0;
+        uint32_t NEXT_PC = 0;
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
+        uint64_t icount = 0;
+    } reg;
+
+    std::array<address_type, 4> addr_mode;
+    
+    uint64_t interrupt_sim=0;
+
+	uint32_t get_fcsr(){return 0;}
+	void set_fcsr(uint32_t val){}
+
+};
+
+}
+}            
+#endif /* _TGF_B_H_ */

incl/iss/arch/tgf_c.h

@@ -0,0 +1,252 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+
+#ifndef _TGF_C_H_
+#define _TGF_C_H_
+
+#include <array>
+#include <iss/arch/traits.h>
+#include <iss/arch_if.h>
+#include <iss/vm_if.h>
+
+namespace iss {
+namespace arch {
+
+struct tgf_c;
+
+template <> struct traits<tgf_c> {
+
+	constexpr static char const* const core_type = "TGF_C";
+    
+  	static constexpr std::array<const char*, 33> reg_names{
+ 		{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
+ 
+  	static constexpr std::array<const char*, 33> reg_aliases{
+ 		{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
+
+    enum constants {XLEN=32, PCLEN=32, MUL_LEN=64, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff};
+
+    constexpr static unsigned FP_REGS_SIZE = 0;
+
+    enum reg_e {
+        X0,
+        X1,
+        X2,
+        X3,
+        X4,
+        X5,
+        X6,
+        X7,
+        X8,
+        X9,
+        X10,
+        X11,
+        X12,
+        X13,
+        X14,
+        X15,
+        X16,
+        X17,
+        X18,
+        X19,
+        X20,
+        X21,
+        X22,
+        X23,
+        X24,
+        X25,
+        X26,
+        X27,
+        X28,
+        X29,
+        X30,
+        X31,
+        PC,
+        NUM_REGS,
+        NEXT_PC=NUM_REGS,
+        TRAP_STATE,
+        PENDING_TRAP,
+        MACHINE_STATE,
+        LAST_BRANCH,
+        ICOUNT,
+        ZERO = X0,
+        RA = X1,
+        SP = X2,
+        GP = X3,
+        TP = X4,
+        T0 = X5,
+        T1 = X6,
+        T2 = X7,
+        S0 = X8,
+        S1 = X9,
+        A0 = X10,
+        A1 = X11,
+        A2 = X12,
+        A3 = X13,
+        A4 = X14,
+        A5 = X15,
+        A6 = X16,
+        A7 = X17,
+        S2 = X18,
+        S3 = X19,
+        S4 = X20,
+        S5 = X21,
+        S6 = X22,
+        S7 = X23,
+        S8 = X24,
+        S9 = X25,
+        S10 = X26,
+        S11 = X27,
+        T3 = X28,
+        T4 = X29,
+        T5 = X30,
+        T6 = X31
+    };
+
+    using reg_t = uint32_t;
+
+    using addr_t = uint32_t;
+
+    using code_word_t = uint32_t; //TODO: check removal
+
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
+
+ 	static constexpr std::array<const uint32_t, 39> reg_bit_widths{
+ 		{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
+
+    static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
+    	{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { MEM, CSR, FENCE, RES };
+};
+
+struct tgf_c: public arch_if {
+
+    using virt_addr_t = typename traits<tgf_c>::virt_addr_t;
+    using phys_addr_t = typename traits<tgf_c>::phys_addr_t;
+    using reg_t =  typename traits<tgf_c>::reg_t;
+    using addr_t = typename traits<tgf_c>::addr_t;
+
+    tgf_c();
+    ~tgf_c();
+
+    void reset(uint64_t address=0) override;
+
+    uint8_t* get_regs_base_ptr() override;
+    /// deprecated
+    void get_reg(short idx, std::vector<uint8_t>& value) override {}
+    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
+    /// deprecated
+    bool get_flag(int flag) override {return false;}
+    void set_flag(int, bool value) override {};
+    /// deprecated
+    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
+
+    inline uint64_t get_icount() { return reg.icount; }
+
+    inline bool should_stop() { return interrupt_sim; }
+
+    inline uint64_t stop_code() { return interrupt_sim; }
+
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<tgf_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf_c>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
+
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
+
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
+protected:
+    struct TGF_C_regs {
+        uint32_t X0 = 0;
+        uint32_t X1 = 0;
+        uint32_t X2 = 0;
+        uint32_t X3 = 0;
+        uint32_t X4 = 0;
+        uint32_t X5 = 0;
+        uint32_t X6 = 0;
+        uint32_t X7 = 0;
+        uint32_t X8 = 0;
+        uint32_t X9 = 0;
+        uint32_t X10 = 0;
+        uint32_t X11 = 0;
+        uint32_t X12 = 0;
+        uint32_t X13 = 0;
+        uint32_t X14 = 0;
+        uint32_t X15 = 0;
+        uint32_t X16 = 0;
+        uint32_t X17 = 0;
+        uint32_t X18 = 0;
+        uint32_t X19 = 0;
+        uint32_t X20 = 0;
+        uint32_t X21 = 0;
+        uint32_t X22 = 0;
+        uint32_t X23 = 0;
+        uint32_t X24 = 0;
+        uint32_t X25 = 0;
+        uint32_t X26 = 0;
+        uint32_t X27 = 0;
+        uint32_t X28 = 0;
+        uint32_t X29 = 0;
+        uint32_t X30 = 0;
+        uint32_t X31 = 0;
+        uint32_t PC = 0;
+        uint32_t NEXT_PC = 0;
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
+        uint64_t icount = 0;
+    } reg;
+
+    std::array<address_type, 4> addr_mode;
+    
+    uint64_t interrupt_sim=0;
+
+	uint32_t get_fcsr(){return 0;}
+	void set_fcsr(uint32_t val){}
+
+};
+
+}
+}            
+#endif /* _TGF_C_H_ */

incl/iss/debugger/riscv_target_adapter.h

@@ -0,0 +1,445 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
+#define _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
+
+#include "iss/arch_if.h"
+#include <iss/arch/traits.h>
+#include <iss/debugger/target_adapter_base.h>
+#include <iss/iss.h>
+
+#include <array>
+#include <memory>
+#ifndef FMT_HEADER_ONLY
+#define FMT_HEADER_ONLY
+#endif
+#include <fmt/format.h>
+#include <util/logging.h>
+
+namespace iss {
+namespace debugger {
+using namespace iss::arch;
+using namespace iss::debugger;
+
+template <typename ARCH> class riscv_target_adapter : public target_adapter_base {
+public:
+    riscv_target_adapter(server_if *srv, iss::arch_if *core)
+    : target_adapter_base(srv)
+    , core(core) {}
+
+    /*============== Thread Control ===============================*/
+
+    /* Set generic thread */
+    status set_gen_thread(rp_thread_ref &thread) override;
+
+    /* Set control thread */
+    status set_ctrl_thread(rp_thread_ref &thread) override;
+
+    /* Get thread status */
+    status is_thread_alive(rp_thread_ref &thread, bool &alive) override;
+
+    /*============= Register Access ================================*/
+
+    /* Read all registers. buf is 4-byte aligned and it is in
+     target byte order. If  register is not available
+     corresponding bytes in avail_buf are 0, otherwise
+     avail buf is 1 */
+    status read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) override;
+
+    /* Write all registers. buf is 4-byte aligned and it is in target
+     byte order */
+    status write_registers(const std::vector<uint8_t> &data) override;
+
+    /* Read one register. buf is 4-byte aligned and it is in
+     target byte order. If  register is not available
+     corresponding bytes in avail_buf are 0, otherwise
+     avail buf is 1 */
+    status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
+                                std::vector<uint8_t> &avail_buf) override;
+
+    /* Write one register. buf is 4-byte aligned and it is in target byte
+     order */
+    status write_single_register(unsigned int reg_no, const std::vector<uint8_t> &buf) override;
+
+    /*=================== Memory Access =====================*/
+
+    /* Read memory, buf is 4-bytes aligned and it is in target
+     byte order */
+    status read_mem(uint64_t addr, std::vector<uint8_t> &buf) override;
+
+    /* Write memory, buf is 4-bytes aligned and it is in target
+     byte order */
+    status write_mem(uint64_t addr, const std::vector<uint8_t> &buf) override;
+
+    status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
+
+    status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
+                             size_t &num, bool &done) override;
+
+    status current_thread_query(rp_thread_ref &thread) override;
+
+    status offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) override;
+
+    status crc_query(uint64_t addr, size_t len, uint32_t &val) override;
+
+    status raw_query(std::string in_buf, std::string &out_buf) override;
+
+    status threadinfo_query(int first, std::string &out_buf) override;
+
+    status threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) override;
+
+    status packetsize_query(std::string &out_buf) override;
+
+    status add_break(int type, uint64_t addr, unsigned int length) override;
+
+    status remove_break(int type, uint64_t addr, unsigned int length) override;
+
+    status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
+                            std::function<void(unsigned)> stop_callback) override;
+
+    status target_xml_query(std::string &out_buf) override;
+
+protected:
+    static inline constexpr addr_t map_addr(const addr_t &i) { return i; }
+
+    iss::arch_if *core;
+    rp_thread_ref thread_idx;
+};
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::set_gen_thread(rp_thread_ref &thread) {
+    thread_idx = thread;
+    return Ok;
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::set_ctrl_thread(rp_thread_ref &thread) {
+    thread_idx = thread;
+    return Ok;
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_thread_ref &thread, bool &alive) {
+    alive = 1;
+    return Ok;
+}
+
+/* List threads. If first is non-zero then start from the first thread,
+ * otherwise start from arg, result points to array of threads to be
+ * filled out, result size is number of elements in the result,
+ * num points to the actual number of threads found, done is
+ * set if all threads are processed.
+ */
+template <typename ARCH>
+status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
+                                                     std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
+                                                     bool &done) {
+    if (first == 0) {
+        result.clear();
+        result.push_back(thread_idx);
+        num = 1;
+        done = true;
+        return Ok;
+    } else
+        return NotSupported;
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query(rp_thread_ref &thread) {
+    thread = thread_idx;
+    return Ok;
+}
+
+template <typename ARCH>
+status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) {
+    LOG(TRACE) << "reading target registers";
+    // return idx<0?:;
+    data.clear();
+    avail.clear();
+    const uint8_t *reg_base = core->get_regs_base_ptr();
+    for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) {
+        auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
+        unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
+        for (size_t j = 0; j < reg_width; ++j) {
+            data.push_back(*(reg_base + offset + j));
+            avail.push_back(0xff);
+        }
+    }
+    // work around fill with F type registers
+//    if (arch::traits<ARCH>::NUM_REGS < 65) {
+//        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
+//        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
+//            for (size_t j = 0; j < reg_width; ++j) {
+//                data.push_back(0x0);
+//                avail.push_back(0x00);
+//            }
+//            // if(arch::traits<ARCH>::XLEN < 64)
+//            //     for(unsigned j=0; j<4; ++j){
+//            //         data.push_back(0x0);
+//            //         avail.push_back(0x00);
+//            //     }
+//        }
+//    }
+    return Ok;
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(const std::vector<uint8_t> &data) {
+    auto reg_count = arch::traits<ARCH>::NUM_REGS;
+    auto *reg_base = core->get_regs_base_ptr();
+    auto iter = data.data();
+    for (size_t reg_no = 0; reg_no < reg_count; ++reg_no) {
+        auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
+        auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
+        std::copy(iter, iter + reg_width, reg_base);
+        iter += 4;
+        reg_base += offset;
+    }
+    return Ok;
+}
+
+template <typename ARCH>
+status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
+                                                        std::vector<uint8_t> &avail) {
+    if (reg_no < 65) {
+        // auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
+        // arch::traits<ARCH>::reg_e>(reg_no))/8;
+        auto *reg_base = core->get_regs_base_ptr();
+        auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
+        data.resize(reg_width);
+        avail.resize(reg_width);
+        auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
+        std::copy(reg_base + offset, reg_base + offset + reg_width, data.begin());
+        std::fill(avail.begin(), avail.end(), 0xff);
+    } else {
+        typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, reg_no - 65);
+        data.resize(sizeof(typename traits<ARCH>::reg_t));
+        avail.resize(sizeof(typename traits<ARCH>::reg_t));
+        std::fill(avail.begin(), avail.end(), 0xff);
+        core->read(a, data.size(), data.data());
+    }
+    return data.size() > 0 ? Ok : Err;
+}
+
+template <typename ARCH>
+status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t> &data) {
+    if (reg_no < 65) {
+        auto *reg_base = core->get_regs_base_ptr();
+        auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
+        auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
+        std::copy(data.begin(), data.begin() + reg_width, reg_base + offset);
+    } else {
+        typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_WRITE, traits<ARCH>::CSR, reg_no - 65);
+        core->write(a, data.size(), data.data());
+    }
+    return Ok;
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t> &data) {
+    auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
+    auto f = [&]() -> status { return core->read(a, data.size(), data.data()); };
+    return srv->execute_syncronized(f);
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t> &data) {
+    auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
+    auto f = [&]() -> status { return core->write(a, data.size(), data.data()); };
+    return srv->execute_syncronized(f);
+}
+
+template <typename ARCH>
+status riscv_target_adapter<ARCH>::process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) {
+    return NotSupported;
+}
+
+template <typename ARCH>
+status riscv_target_adapter<ARCH>::offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) {
+    text = 0;
+    data = 0;
+    bss = 0;
+    return Ok;
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t &val) {
+    return NotSupported;
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::raw_query(std::string in_buf, std::string &out_buf) {
+    return NotSupported;
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::threadinfo_query(int first, std::string &out_buf) {
+    if (first) {
+        out_buf = fmt::format("m{:x}", thread_idx.val);
+    } else {
+        out_buf = "l";
+    }
+    return Ok;
+}
+
+template <typename ARCH>
+status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) {
+    std::array<char, 20> buf;
+    memset(buf.data(), 0, 20);
+    sprintf(buf.data(), "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
+    out_buf = buf.data();
+    return Ok;
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std::string &out_buf) {
+    out_buf = "PacketSize=1000";
+    return Ok;
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
+    auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
+    auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
+    target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
+    LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
+               << saddr.val << std::dec;
+    LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+    return Ok;
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
+    auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
+    unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
+    if (handle) {
+        LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
+                   << std::dec;
+        // TODO: check length of addr range
+        target_adapter_base::bp_lut.removeEntry(handle);
+        LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+        return Ok;
+    }
+    LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+    return Err;
+}
+
+template <typename ARCH>
+status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
+                                                    std::function<void(unsigned)> stop_callback) {
+    auto *reg_base = core->get_regs_base_ptr();
+    auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
+    auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
+    const uint8_t *iter = reinterpret_cast<const uint8_t *>(&addr);
+    std::copy(iter, iter + reg_width, reg_base);
+    return resume_from_current(step, sig, thread, stop_callback);
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string &out_buf) {
+    const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
+                          "<target><architecture>riscv:rv32</architecture>"
+                          //"  <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
+                          //"    <reg name=\"x0\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x1\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x2\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x3\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x4\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x5\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x6\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x7\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x8\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x9\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"  </feature>\n"
+                          "</target>"};
+    out_buf = res;
+    return Ok;
+}
+
+/*
+ *
+<?xml version="1.0"?>
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+  <architecture>riscv:rv32</architecture>
+
+  <feature name="org.gnu.gdb.riscv.rv32i">
+    <reg name="x0"  bitsize="32" group="general"/>
+    <reg name="x1"  bitsize="32" group="general"/>
+    <reg name="x2"  bitsize="32" group="general"/>
+    <reg name="x3"  bitsize="32" group="general"/>
+    <reg name="x4"  bitsize="32" group="general"/>
+    <reg name="x5"  bitsize="32" group="general"/>
+    <reg name="x6"  bitsize="32" group="general"/>
+    <reg name="x7"  bitsize="32" group="general"/>
+    <reg name="x8"  bitsize="32" group="general"/>
+    <reg name="x9"  bitsize="32" group="general"/>
+    <reg name="x10" bitsize="32" group="general"/>
+    <reg name="x11" bitsize="32" group="general"/>
+    <reg name="x12" bitsize="32" group="general"/>
+    <reg name="x13" bitsize="32" group="general"/>
+    <reg name="x14" bitsize="32" group="general"/>
+    <reg name="x15" bitsize="32" group="general"/>
+    <reg name="x16" bitsize="32" group="general"/>
+    <reg name="x17" bitsize="32" group="general"/>
+    <reg name="x18" bitsize="32" group="general"/>
+    <reg name="x19" bitsize="32" group="general"/>
+    <reg name="x20" bitsize="32" group="general"/>
+    <reg name="x21" bitsize="32" group="general"/>
+    <reg name="x22" bitsize="32" group="general"/>
+    <reg name="x23" bitsize="32" group="general"/>
+    <reg name="x24" bitsize="32" group="general"/>
+    <reg name="x25" bitsize="32" group="general"/>
+    <reg name="x26" bitsize="32" group="general"/>
+    <reg name="x27" bitsize="32" group="general"/>
+    <reg name="x28" bitsize="32" group="general"/>
+    <reg name="x29" bitsize="32" group="general"/>
+    <reg name="x30" bitsize="32" group="general"/>
+    <reg name="x31" bitsize="32" group="general"/>
+  </feature>
+
+</target>
+
+ */
+}
+}
+
+#endif /* _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */

incl/iss/plugin/cycle_estimate.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
+ * Copyright (C) 2017, 2018, MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -37,61 +37,60 @@
 
 #include "iss/instrumentation_if.h"
 #include "iss/vm_plugin.h"
-#include <functional>
+#include <json/json.h>
 #include <string>
 #include <unordered_map>
-#include <vector>
 
 namespace iss {
 
 namespace plugin {
 
-class cycle_estimate : public vm_plugin {
+class cycle_estimate: public iss::vm_plugin {
-    struct instr_desc {
+	BEGIN_BF_DECL(instr_desc, uint32_t)
-        size_t size{0};
+		BF_FIELD(taken, 24, 8)
-        bool is_branch{false};
+		BF_FIELD(not_taken, 16, 8)
-        unsigned not_taken{1};
+		BF_FIELD(size, 0, 16)
-        unsigned taken{1};
+		instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken): instr_desc() {
-        std::function<unsigned(uint64_t)> f;
+			this->size=size;
-    };
+			this->taken=taken;
+			this->not_taken=not_taken;
+		}
+	END_BF_DECL();
 
 public:
     cycle_estimate() = delete;
 
-    cycle_estimate(const cycle_estimate&) = delete;
+    cycle_estimate(const cycle_estimate &) = delete;
 
-    cycle_estimate(const cycle_estimate&&) = delete;
+    cycle_estimate(const cycle_estimate &&) = delete;
 
-    cycle_estimate(std::string const& config_file_name);
+    cycle_estimate(std::string config_file_name);
 
     virtual ~cycle_estimate();
 
-    cycle_estimate& operator=(const cycle_estimate&) = delete;
+    cycle_estimate &operator=(const cycle_estimate &) = delete;
 
-    cycle_estimate& operator=(const cycle_estimate&&) = delete;
+    cycle_estimate &operator=(const cycle_estimate &&) = delete;
 
-    bool registration(const char* const version, vm_if& arch) override;
+    bool registration(const char *const version, vm_if &arch) override;
 
-    sync_type get_sync() override { return ALL_SYNC; };
+    sync_type get_sync() override { return POST_SYNC; };
 
     void callback(instr_info_t instr_info) override;
 
 private:
-    iss::instrumentation_if* instr_if{nullptr};
+    iss::instrumentation_if *arch_instr;
-    uint32_t* reg_base_ptr{nullptr};
-    instr_desc illegal_desc{};
     std::vector<instr_desc> delays;
-    unsigned current_delay{0};
     struct pair_hash {
-        size_t operator()(const std::pair<uint64_t, uint64_t>& p) const {
+        size_t operator()(const std::pair<uint64_t, uint64_t> &p) const {
             std::hash<uint64_t> hash;
             return hash(p.first) + hash(p.second);
         }
     };
     std::unordered_map<std::pair<uint64_t, uint64_t>, uint64_t, pair_hash> blocks;
-    std::string config_file_name;
+    Json::Value root;
 };
-} // namespace plugin
+}
-} // namespace iss
+}
 
 #endif /* _ISS_PLUGIN_CYCLE_ESTIMATE_H_ */

incl/iss/plugin/instruction_count.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
+ * Copyright (C) 2017, 2018, MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -36,8 +36,8 @@
 #define _ISS_PLUGIN_INSTRUCTION_COUNTER_H_
 
 #include <iss/vm_plugin.h>
+#include <json/json.h>
 #include <string>
-#include <vector>
 
 namespace iss {
 namespace plugin {
@@ -53,29 +53,30 @@ class instruction_count : public iss::vm_plugin {
 public:
     instruction_count() = delete;
 
-    instruction_count(const instruction_count&) = delete;
+    instruction_count(const instruction_count &) = delete;
 
-    instruction_count(const instruction_count&&) = delete;
+    instruction_count(const instruction_count &&) = delete;
 
     instruction_count(std::string config_file_name);
 
     virtual ~instruction_count();
 
-    instruction_count& operator=(const instruction_count&) = delete;
+    instruction_count &operator=(const instruction_count &) = delete;
 
-    instruction_count& operator=(const instruction_count&&) = delete;
+    instruction_count &operator=(const instruction_count &&) = delete;
 
-    bool registration(const char* const version, vm_if& arch) override;
+    bool registration(const char *const version, vm_if &arch) override;
 
     sync_type get_sync() override { return POST_SYNC; };
 
-    void callback(instr_info_t) override;
+    void callback(instr_info_t instr_info) override;
 
 private:
+    Json::Value root;
     std::vector<instr_delay> delays;
     std::vector<uint64_t> rep_counts;
 };
-} // namespace plugin
+}
-} // namespace iss
+}
 
 #endif /* _ISS_PLUGIN_INSTRUCTION_COUNTER_H_ */

incl/sysc/core_complex.h

@@ -0,0 +1,166 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _SYSC_SIFIVE_FE310_H_
+#define _SYSC_SIFIVE_FE310_H_
+
+#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
+#include "tlm/scc/initiator_mixin.h"
+#include "scc/traceable.h"
+#include "scc/utilities.h"
+#include <cci_configuration>
+#include <tlm>
+#include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
+#include <tlm_utils/tlm_quantumkeeper.h>
+#include <util/range_lut.h>
+
+class scv_tr_db;
+class scv_tr_stream;
+struct _scv_tr_generator_default_data;
+template <class T_begin, class T_end> class scv_tr_generator;
+
+namespace iss {
+class vm_if;
+namespace arch {
+template <typename BASE> class riscv_hart_m_p;
+}
+namespace debugger {
+class target_adapter_if;
+}
+} // namespace iss
+
+namespace sysc {
+
+class tlm_dmi_ext : public tlm::tlm_dmi {
+public:
+    bool operator==(const tlm_dmi_ext &o) const {
+        return this->get_granted_access() == o.get_granted_access() &&
+               this->get_start_address() == o.get_start_address() && this->get_end_address() == o.get_end_address();
+    }
+
+    bool operator!=(const tlm_dmi_ext &o) const { return !operator==(o); }
+};
+
+namespace SiFive {
+class core_wrapper;
+
+class core_complex : public sc_core::sc_module, public scc::traceable {
+public:
+    tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
+
+    sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
+
+    sc_core::sc_in<bool> rst_i{"rst_i"};
+
+    sc_core::sc_in<bool> global_irq_i{"global_irq_i"};
+
+    sc_core::sc_in<bool> timer_irq_i{"timer_irq_i"};
+
+    sc_core::sc_in<bool> sw_irq_i{"sw_irq_i"};
+
+    sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i{"local_irq_i", 16};
+
+    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
+
+    cci::cci_param<std::string> elf_file{"elf_file", ""};
+
+    cci::cci_param<bool> enable_disass{"enable_disass", false};
+
+    cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
+
+    cci::cci_param<std::string> backend{"backend", "tcc"};
+
+    cci::cci_param<unsigned short> gdb_server_port{"gdb_server_port", 0};
+
+    cci::cci_param<bool> dump_ir{"dump_ir", false};
+
+    cci::cci_param<uint32_t> mhartid{"mhartid", 0};
+
+    core_complex(sc_core::sc_module_name name);
+
+    ~core_complex();
+
+    inline void sync(uint64_t cycle) {
+        auto time = curr_clk * (cycle - last_sync_cycle);
+        quantum_keeper.inc(time);
+        if (quantum_keeper.need_sync()) {
+            wait(quantum_keeper.get_local_time());
+            quantum_keeper.reset();
+        }
+        last_sync_cycle = cycle;
+    }
+
+    bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
+
+    bool write_mem(uint64_t addr, unsigned length, const uint8_t *const data);
+
+    bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data);
+
+    bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data);
+
+    void trace(sc_core::sc_trace_file *trf) const override;
+
+    void disass_output(uint64_t pc, const std::string instr);
+
+protected:
+    void before_end_of_elaboration() override;
+    void start_of_simulation() override;
+    void run();
+    void clk_cb();
+    void rst_cb();
+    void sw_irq_cb();
+    void timer_irq_cb();
+    void global_irq_cb();
+    uint64_t last_sync_cycle = 0;
+    util::range_lut<tlm_dmi_ext> read_lut, write_lut;
+    tlm_utils::tlm_quantumkeeper quantum_keeper;
+    std::vector<uint8_t> write_buf;
+    std::unique_ptr<core_wrapper> cpu;
+    std::unique_ptr<iss::vm_if> vm;
+    sc_core::sc_time curr_clk;
+    iss::debugger::target_adapter_if *tgt_adapter;
+#ifdef WITH_SCV
+    //! transaction recording database
+    scv_tr_db *m_db;
+    //! blocking transaction recording stream handle
+    scv_tr_stream *stream_handle;
+    //! transaction generator handle for blocking transactions
+    scv_tr_generator<_scv_tr_generator_default_data, _scv_tr_generator_default_data> *instr_tr_handle;
+    scv_tr_generator<uint64_t, _scv_tr_generator_default_data> *fetch_tr_handle;
+    scv_tr_handle tr_handle;
+#endif
+};
+
+} /* namespace SiFive */
+} /* namespace sysc */
+
+#endif /* _SYSC_SIFIVE_FE310_H_ */

softfloat/.gitignore

@@ -1,2 +0,0 @@
-build/*/*.o
-build/*/*.a

softfloat/CMakeLists.txt

@@ -8,7 +8,7 @@ project("sotfloat" VERSION 3.0.0)
 # Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0)
 set(VERSION "3e")
 
-#include(Common)
+include(Common)
 include(GNUInstallDirs)
 
 set(SPECIALIZATION RISCV)
@@ -327,7 +327,7 @@ set(OTHERS
 
 set(LIB_SOURCES ${PRIMITIVES} ${SPECIALIZE} ${OTHERS})
 
-add_library(softfloat STATIC ${LIB_SOURCES})
+add_library(softfloat ${LIB_SOURCES})
 set_property(TARGET softfloat PROPERTY C_STANDARD 99)
 target_compile_definitions(softfloat PRIVATE 
 	SOFTFLOAT_ROUND_ODD 
@@ -347,7 +347,7 @@ set_target_properties(softfloat PROPERTIES
 
 install(TARGETS softfloat
   EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
-  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}/static COMPONENT libs   # static lib
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # static lib
   LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # shared lib
   FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac
   PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} COMPONENT devel   # headers for mac (note the different component -> different package)

softfloat/COPYING.txt

@@ -1,37 +1,37 @@
-
+
-License for Berkeley SoftFloat Release 3e
+License for Berkeley SoftFloat Release 3e
-
+
-John R. Hauser
+John R. Hauser
-2018 January 20
+2018 January 20
-
+
-The following applies to the whole of SoftFloat Release 3e as well as to
+The following applies to the whole of SoftFloat Release 3e as well as to
-each source file individually.
+each source file individually.
-
+
-Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
-University of California.  All rights reserved.
+University of California.  All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright
+ 2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions, and the following disclaimer in the
+    notice, this list of conditions, and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
+    documentation and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors
+ 3. Neither the name of the University nor the names of its contributors
-    may be used to endorse or promote products derived from this software
+    may be used to endorse or promote products derived from this software
-    without specific prior written permission.
+    without specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+

softfloat/README.html

@@ -1,49 +1,49 @@
-
+
-<HTML>
+<HTML>
-
+
-<HEAD>
+<HEAD>
-<TITLE>Berkeley SoftFloat Package Overview</TITLE>
+<TITLE>Berkeley SoftFloat Package Overview</TITLE>
-</HEAD>
+</HEAD>
-
+
-<BODY>
+<BODY>
-
+
-<H1>Package Overview for Berkeley SoftFloat Release 3e</H1>
+<H1>Package Overview for Berkeley SoftFloat Release 3e</H1>
-
+
-<P>
+<P>
-John R. Hauser<BR>
+John R. Hauser<BR>
-2018 January 20<BR>
+2018 January 20<BR>
-</P>
+</P>
-
+
-<P>
+<P>
-Berkeley SoftFloat is a software implementation of binary floating-point that
+Berkeley SoftFloat is a software implementation of binary floating-point that
-conforms to the IEEE Standard for Floating-Point Arithmetic.
+conforms to the IEEE Standard for Floating-Point Arithmetic.
-SoftFloat is distributed in the form of C source code.
+SoftFloat is distributed in the form of C source code.
-Building the SoftFloat sources generates a library file (typically
+Building the SoftFloat sources generates a library file (typically
-<CODE>softfloat.a</CODE> or <CODE>libsoftfloat.a</CODE>) containing the
+<CODE>softfloat.a</CODE> or <CODE>libsoftfloat.a</CODE>) containing the
-floating-point subroutines.
+floating-point subroutines.
-</P>
+</P>
-
+
-<P>
+<P>
-The SoftFloat package is documented in the following files in the
+The SoftFloat package is documented in the following files in the
-<CODE>doc</CODE> subdirectory:
+<CODE>doc</CODE> subdirectory:
-<BLOCKQUOTE>
+<BLOCKQUOTE>
-<TABLE>
+<TABLE>
-<TR>
+<TR>
-<TD><A HREF="doc/SoftFloat.html"><NOBR><CODE>SoftFloat.html</CODE></NOBR></A></TD>
+<TD><A HREF="doc/SoftFloat.html"><NOBR><CODE>SoftFloat.html</CODE></NOBR></A></TD>
-<TD>Documentation for using the SoftFloat functions.</TD>
+<TD>Documentation for using the SoftFloat functions.</TD>
-</TR>
+</TR>
-<TR>
+<TR>
-<TD><A HREF="doc/SoftFloat-source.html"><NOBR><CODE>SoftFloat-source.html</CODE></NOBR></A></TD>
+<TD><A HREF="doc/SoftFloat-source.html"><NOBR><CODE>SoftFloat-source.html</CODE></NOBR></A></TD>
-<TD>Documentation for building SoftFloat.</TD>
+<TD>Documentation for building SoftFloat.</TD>
-</TR>
+</TR>
-<TR>
+<TR>
-<TD><A HREF="doc/SoftFloat-history.html"><NOBR><CODE>SoftFloat-history.html</CODE></A><CODE>&nbsp;&nbsp;&nbsp;</CODE></NOBR></TD>
+<TD><A HREF="doc/SoftFloat-history.html"><NOBR><CODE>SoftFloat-history.html</CODE></A><CODE>&nbsp;&nbsp;&nbsp;</CODE></NOBR></TD>
-<TD>History of the major changes to SoftFloat.</TD>
+<TD>History of the major changes to SoftFloat.</TD>
-</TR>
+</TR>
-</TABLE>
+</TABLE>
-</BLOCKQUOTE>
+</BLOCKQUOTE>
-Other files in the package comprise the source code for SoftFloat.
+Other files in the package comprise the source code for SoftFloat.
-</P>
+</P>
-
+
-</BODY>
+</BODY>
-
+

softfloat/README.md

@@ -1,24 +0,0 @@
-
-Package Overview for Berkeley SoftFloat Release 3e
-==================================================
-
-John R. Hauser<br>
-2018 January 20
-
-
-Berkeley SoftFloat is a software implementation of binary floating-point
-that conforms to the IEEE Standard for Floating-Point Arithmetic.  SoftFloat
-is distributed in the form of C source code.  Building the SoftFloat sources
-generates a library file (typically `softfloat.a` or `libsoftfloat.a`)
-containing the floating-point subroutines.
-
-
-The SoftFloat package is documented in the following files in the `doc`
-subdirectory:
-
-* [SoftFloat.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat.html) Documentation for using the SoftFloat functions.
-* [SoftFloat-source.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat-source.html) Documentation for building SoftFloat.
-* [SoftFloat-history.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat-history.html) History of the major changes to SoftFloat.
-
-Other files in the package comprise the source code for SoftFloat.
-

softfloat/README.txt

@@ -1,21 +1,21 @@
-
+
-Package Overview for Berkeley SoftFloat Release 3e
+Package Overview for Berkeley SoftFloat Release 3e
-
+
-John R. Hauser
+John R. Hauser
-2018 January 20
+2018 January 20
-
+
-Berkeley SoftFloat is a software implementation of binary floating-point
+Berkeley SoftFloat is a software implementation of binary floating-point
-that conforms to the IEEE Standard for Floating-Point Arithmetic.  SoftFloat
+that conforms to the IEEE Standard for Floating-Point Arithmetic.  SoftFloat
-is distributed in the form of C source code.  Building the SoftFloat sources
+is distributed in the form of C source code.  Building the SoftFloat sources
-generates a library file (typically "softfloat.a" or "libsoftfloat.a")
+generates a library file (typically "softfloat.a" or "libsoftfloat.a")
-containing the floating-point subroutines.
+containing the floating-point subroutines.
-
+
-The SoftFloat package is documented in the following files in the "doc"
+The SoftFloat package is documented in the following files in the "doc"
-subdirectory:
+subdirectory:
-
+
-    SoftFloat.html          Documentation for using the SoftFloat functions.
+    SoftFloat.html          Documentation for using the SoftFloat functions.
-    SoftFloat-source.html   Documentation for building SoftFloat.
+    SoftFloat-source.html   Documentation for building SoftFloat.
-    SoftFloat-history.html  History of the major changes to SoftFloat.
+    SoftFloat-history.html  History of the major changes to SoftFloat.
-
+
-Other files in the package comprise the source code for SoftFloat.
+Other files in the package comprise the source code for SoftFloat.
-
+

softfloat/build/Linux-386-GCC/Makefile

@@ -1,325 +1,325 @@
-
+
-#=============================================================================
+#=============================================================================
-#
+#
-# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
-# Package, Release 3e, by John R. Hauser.
+# Package, Release 3e, by John R. Hauser.
-#
+#
-# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-# University of California.  All rights reserved.
+# University of California.  All rights reserved.
-#
+#
-# Redistribution and use in source and binary forms, with or without
+# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
+# modification, are permitted provided that the following conditions are met:
-#
+#
-#  1. Redistributions of source code must retain the above copyright notice,
+#  1. Redistributions of source code must retain the above copyright notice,
-#     this list of conditions, and the following disclaimer.
+#     this list of conditions, and the following disclaimer.
-#
+#
-#  2. Redistributions in binary form must reproduce the above copyright
+#  2. Redistributions in binary form must reproduce the above copyright
-#     notice, this list of conditions, and the following disclaimer in the
+#     notice, this list of conditions, and the following disclaimer in the
-#     documentation and/or other materials provided with the distribution.
+#     documentation and/or other materials provided with the distribution.
-#
+#
-#  3. Neither the name of the University nor the names of its contributors
+#  3. Neither the name of the University nor the names of its contributors
-#     may be used to endorse or promote products derived from this software
+#     may be used to endorse or promote products derived from this software
-#     without specific prior written permission.
+#     without specific prior written permission.
-#
+#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
+#
-#=============================================================================
+#=============================================================================
-
+
-SOURCE_DIR ?= ../../source
+SOURCE_DIR ?= ../../source
-SPECIALIZE_TYPE ?= 8086
+SPECIALIZE_TYPE ?= 8086
-
+
-SOFTFLOAT_OPTS ?= \
+SOFTFLOAT_OPTS ?= \
-  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-  -DSOFTFLOAT_FAST_DIV64TO32
+  -DSOFTFLOAT_FAST_DIV64TO32
-
+
-DELETE = rm -f
+DELETE = rm -f
-C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
-COMPILE_C = \
+COMPILE_C = \
-  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
+  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
-    $(C_INCLUDES) -O2 -o $@
+    $(C_INCLUDES) -O2 -o $@
-MAKELIB = ar crs $@
+MAKELIB = ar crs $@
-
+
-OBJ = .o
+OBJ = .o
-LIB = .a
+LIB = .a
-
+
-OTHER_HEADERS =
+OTHER_HEADERS =
-
+
-.PHONY: all
+.PHONY: all
-all: softfloat$(LIB)
+all: softfloat$(LIB)
-
+
-OBJS_PRIMITIVES = \
+OBJS_PRIMITIVES = \
-  s_compare96M$(OBJ) \
+  s_compare96M$(OBJ) \
-  s_compare128M$(OBJ) \
+  s_compare128M$(OBJ) \
-  s_shortShiftLeft64To96M$(OBJ) \
+  s_shortShiftLeft64To96M$(OBJ) \
-  s_shortShiftLeftM$(OBJ) \
+  s_shortShiftLeftM$(OBJ) \
-  s_shiftLeftM$(OBJ) \
+  s_shiftLeftM$(OBJ) \
-  s_shortShiftRightM$(OBJ) \
+  s_shortShiftRightM$(OBJ) \
-  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
-  s_shortShiftRightJamM$(OBJ) \
+  s_shortShiftRightJamM$(OBJ) \
-  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
-  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
-  s_shiftRightJamM$(OBJ) \
+  s_shiftRightJamM$(OBJ) \
-  s_shiftRightM$(OBJ) \
+  s_shiftRightM$(OBJ) \
-  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
-  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
-  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
-  s_countLeadingZeros64$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
-  s_addM$(OBJ) \
+  s_addM$(OBJ) \
-  s_addCarryM$(OBJ) \
+  s_addCarryM$(OBJ) \
-  s_addComplCarryM$(OBJ) \
+  s_addComplCarryM$(OBJ) \
-  s_negXM$(OBJ) \
+  s_negXM$(OBJ) \
-  s_sub1XM$(OBJ) \
+  s_sub1XM$(OBJ) \
-  s_subM$(OBJ) \
+  s_subM$(OBJ) \
-  s_mul64To128M$(OBJ) \
+  s_mul64To128M$(OBJ) \
-  s_mul128MTo256M$(OBJ) \
+  s_mul128MTo256M$(OBJ) \
-  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
-  s_approxRecip32_1$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
-  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
-  s_approxRecipSqrt32_1$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
-  s_remStepMBy32$(OBJ) \
+  s_remStepMBy32$(OBJ) \
-
+
-OBJS_SPECIALIZE = \
+OBJS_SPECIALIZE = \
-  softfloat_raiseFlags$(OBJ) \
+  softfloat_raiseFlags$(OBJ) \
-  s_f16UIToCommonNaN$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
-  s_commonNaNToF16UI$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
-  s_propagateNaNF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
-  s_f32UIToCommonNaN$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
-  s_commonNaNToF32UI$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
-  s_propagateNaNF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
-  s_f64UIToCommonNaN$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
-  s_commonNaNToF64UI$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
-  s_propagateNaNF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
-  extF80M_isSignalingNaN$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
-  s_extF80MToCommonNaN$(OBJ) \
+  s_extF80MToCommonNaN$(OBJ) \
-  s_commonNaNToExtF80M$(OBJ) \
+  s_commonNaNToExtF80M$(OBJ) \
-  s_propagateNaNExtF80M$(OBJ) \
+  s_propagateNaNExtF80M$(OBJ) \
-  f128M_isSignalingNaN$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
-  s_f128MToCommonNaN$(OBJ) \
+  s_f128MToCommonNaN$(OBJ) \
-  s_commonNaNToF128M$(OBJ) \
+  s_commonNaNToF128M$(OBJ) \
-  s_propagateNaNF128M$(OBJ) \
+  s_propagateNaNF128M$(OBJ) \
-
+
-OBJS_OTHERS = \
+OBJS_OTHERS = \
-  s_roundToUI32$(OBJ) \
+  s_roundToUI32$(OBJ) \
-  s_roundMToUI64$(OBJ) \
+  s_roundMToUI64$(OBJ) \
-  s_roundToI32$(OBJ) \
+  s_roundToI32$(OBJ) \
-  s_roundMToI64$(OBJ) \
+  s_roundMToI64$(OBJ) \
-  s_normSubnormalF16Sig$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
-  s_roundPackToF16$(OBJ) \
+  s_roundPackToF16$(OBJ) \
-  s_normRoundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
-  s_addMagsF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
-  s_subMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
-  s_mulAddF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
-  s_normSubnormalF32Sig$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
-  s_roundPackToF32$(OBJ) \
+  s_roundPackToF32$(OBJ) \
-  s_normRoundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
-  s_addMagsF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
-  s_subMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
-  s_mulAddF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
-  s_normSubnormalF64Sig$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
-  s_roundPackToF64$(OBJ) \
+  s_roundPackToF64$(OBJ) \
-  s_normRoundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
-  s_addMagsF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
-  s_subMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
-  s_mulAddF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
-  s_tryPropagateNaNExtF80M$(OBJ) \
+  s_tryPropagateNaNExtF80M$(OBJ) \
-  s_invalidExtF80M$(OBJ) \
+  s_invalidExtF80M$(OBJ) \
-  s_normExtF80SigM$(OBJ) \
+  s_normExtF80SigM$(OBJ) \
-  s_roundPackMToExtF80M$(OBJ) \
+  s_roundPackMToExtF80M$(OBJ) \
-  s_normRoundPackMToExtF80M$(OBJ) \
+  s_normRoundPackMToExtF80M$(OBJ) \
-  s_addExtF80M$(OBJ) \
+  s_addExtF80M$(OBJ) \
-  s_compareNonnormExtF80M$(OBJ) \
+  s_compareNonnormExtF80M$(OBJ) \
-  s_isNaNF128M$(OBJ) \
+  s_isNaNF128M$(OBJ) \
-  s_tryPropagateNaNF128M$(OBJ) \
+  s_tryPropagateNaNF128M$(OBJ) \
-  s_invalidF128M$(OBJ) \
+  s_invalidF128M$(OBJ) \
-  s_shiftNormSigF128M$(OBJ) \
+  s_shiftNormSigF128M$(OBJ) \
-  s_roundPackMToF128M$(OBJ) \
+  s_roundPackMToF128M$(OBJ) \
-  s_normRoundPackMToF128M$(OBJ) \
+  s_normRoundPackMToF128M$(OBJ) \
-  s_addF128M$(OBJ) \
+  s_addF128M$(OBJ) \
-  s_mulAddF128M$(OBJ) \
+  s_mulAddF128M$(OBJ) \
-  softfloat_state$(OBJ) \
+  softfloat_state$(OBJ) \
-  ui32_to_f16$(OBJ) \
+  ui32_to_f16$(OBJ) \
-  ui32_to_f32$(OBJ) \
+  ui32_to_f32$(OBJ) \
-  ui32_to_f64$(OBJ) \
+  ui32_to_f64$(OBJ) \
-  ui32_to_extF80M$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
-  ui32_to_f128M$(OBJ) \
+  ui32_to_f128M$(OBJ) \
-  ui64_to_f16$(OBJ) \
+  ui64_to_f16$(OBJ) \
-  ui64_to_f32$(OBJ) \
+  ui64_to_f32$(OBJ) \
-  ui64_to_f64$(OBJ) \
+  ui64_to_f64$(OBJ) \
-  ui64_to_extF80M$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
-  ui64_to_f128M$(OBJ) \
+  ui64_to_f128M$(OBJ) \
-  i32_to_f16$(OBJ) \
+  i32_to_f16$(OBJ) \
-  i32_to_f32$(OBJ) \
+  i32_to_f32$(OBJ) \
-  i32_to_f64$(OBJ) \
+  i32_to_f64$(OBJ) \
-  i32_to_extF80M$(OBJ) \
+  i32_to_extF80M$(OBJ) \
-  i32_to_f128M$(OBJ) \
+  i32_to_f128M$(OBJ) \
-  i64_to_f16$(OBJ) \
+  i64_to_f16$(OBJ) \
-  i64_to_f32$(OBJ) \
+  i64_to_f32$(OBJ) \
-  i64_to_f64$(OBJ) \
+  i64_to_f64$(OBJ) \
-  i64_to_extF80M$(OBJ) \
+  i64_to_extF80M$(OBJ) \
-  i64_to_f128M$(OBJ) \
+  i64_to_f128M$(OBJ) \
-  f16_to_ui32$(OBJ) \
+  f16_to_ui32$(OBJ) \
-  f16_to_ui64$(OBJ) \
+  f16_to_ui64$(OBJ) \
-  f16_to_i32$(OBJ) \
+  f16_to_i32$(OBJ) \
-  f16_to_i64$(OBJ) \
+  f16_to_i64$(OBJ) \
-  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
-  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
-  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
-  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
-  f16_to_f32$(OBJ) \
+  f16_to_f32$(OBJ) \
-  f16_to_f64$(OBJ) \
+  f16_to_f64$(OBJ) \
-  f16_to_extF80M$(OBJ) \
+  f16_to_extF80M$(OBJ) \
-  f16_to_f128M$(OBJ) \
+  f16_to_f128M$(OBJ) \
-  f16_roundToInt$(OBJ) \
+  f16_roundToInt$(OBJ) \
-  f16_add$(OBJ) \
+  f16_add$(OBJ) \
-  f16_sub$(OBJ) \
+  f16_sub$(OBJ) \
-  f16_mul$(OBJ) \
+  f16_mul$(OBJ) \
-  f16_mulAdd$(OBJ) \
+  f16_mulAdd$(OBJ) \
-  f16_div$(OBJ) \
+  f16_div$(OBJ) \
-  f16_rem$(OBJ) \
+  f16_rem$(OBJ) \
-  f16_sqrt$(OBJ) \
+  f16_sqrt$(OBJ) \
-  f16_eq$(OBJ) \
+  f16_eq$(OBJ) \
-  f16_le$(OBJ) \
+  f16_le$(OBJ) \
-  f16_lt$(OBJ) \
+  f16_lt$(OBJ) \
-  f16_eq_signaling$(OBJ) \
+  f16_eq_signaling$(OBJ) \
-  f16_le_quiet$(OBJ) \
+  f16_le_quiet$(OBJ) \
-  f16_lt_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
-  f16_isSignalingNaN$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
-  f32_to_ui32$(OBJ) \
+  f32_to_ui32$(OBJ) \
-  f32_to_ui64$(OBJ) \
+  f32_to_ui64$(OBJ) \
-  f32_to_i32$(OBJ) \
+  f32_to_i32$(OBJ) \
-  f32_to_i64$(OBJ) \
+  f32_to_i64$(OBJ) \
-  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
-  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
-  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
-  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
-  f32_to_f16$(OBJ) \
+  f32_to_f16$(OBJ) \
-  f32_to_f64$(OBJ) \
+  f32_to_f64$(OBJ) \
-  f32_to_extF80M$(OBJ) \
+  f32_to_extF80M$(OBJ) \
-  f32_to_f128M$(OBJ) \
+  f32_to_f128M$(OBJ) \
-  f32_roundToInt$(OBJ) \
+  f32_roundToInt$(OBJ) \
-  f32_add$(OBJ) \
+  f32_add$(OBJ) \
-  f32_sub$(OBJ) \
+  f32_sub$(OBJ) \
-  f32_mul$(OBJ) \
+  f32_mul$(OBJ) \
-  f32_mulAdd$(OBJ) \
+  f32_mulAdd$(OBJ) \
-  f32_div$(OBJ) \
+  f32_div$(OBJ) \
-  f32_rem$(OBJ) \
+  f32_rem$(OBJ) \
-  f32_sqrt$(OBJ) \
+  f32_sqrt$(OBJ) \
-  f32_eq$(OBJ) \
+  f32_eq$(OBJ) \
-  f32_le$(OBJ) \
+  f32_le$(OBJ) \
-  f32_lt$(OBJ) \
+  f32_lt$(OBJ) \
-  f32_eq_signaling$(OBJ) \
+  f32_eq_signaling$(OBJ) \
-  f32_le_quiet$(OBJ) \
+  f32_le_quiet$(OBJ) \
-  f32_lt_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
-  f32_isSignalingNaN$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
-  f64_to_ui32$(OBJ) \
+  f64_to_ui32$(OBJ) \
-  f64_to_ui64$(OBJ) \
+  f64_to_ui64$(OBJ) \
-  f64_to_i32$(OBJ) \
+  f64_to_i32$(OBJ) \
-  f64_to_i64$(OBJ) \
+  f64_to_i64$(OBJ) \
-  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
-  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
-  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
-  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
-  f64_to_f16$(OBJ) \
+  f64_to_f16$(OBJ) \
-  f64_to_f32$(OBJ) \
+  f64_to_f32$(OBJ) \
-  f64_to_extF80M$(OBJ) \
+  f64_to_extF80M$(OBJ) \
-  f64_to_f128M$(OBJ) \
+  f64_to_f128M$(OBJ) \
-  f64_roundToInt$(OBJ) \
+  f64_roundToInt$(OBJ) \
-  f64_add$(OBJ) \
+  f64_add$(OBJ) \
-  f64_sub$(OBJ) \
+  f64_sub$(OBJ) \
-  f64_mul$(OBJ) \
+  f64_mul$(OBJ) \
-  f64_mulAdd$(OBJ) \
+  f64_mulAdd$(OBJ) \
-  f64_div$(OBJ) \
+  f64_div$(OBJ) \
-  f64_rem$(OBJ) \
+  f64_rem$(OBJ) \
-  f64_sqrt$(OBJ) \
+  f64_sqrt$(OBJ) \
-  f64_eq$(OBJ) \
+  f64_eq$(OBJ) \
-  f64_le$(OBJ) \
+  f64_le$(OBJ) \
-  f64_lt$(OBJ) \
+  f64_lt$(OBJ) \
-  f64_eq_signaling$(OBJ) \
+  f64_eq_signaling$(OBJ) \
-  f64_le_quiet$(OBJ) \
+  f64_le_quiet$(OBJ) \
-  f64_lt_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
-  f64_isSignalingNaN$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
-  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
-  extF80M_to_ui64$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
-  extF80M_to_i32$(OBJ) \
+  extF80M_to_i32$(OBJ) \
-  extF80M_to_i64$(OBJ) \
+  extF80M_to_i64$(OBJ) \
-  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
-  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
-  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
-  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
-  extF80M_to_f16$(OBJ) \
+  extF80M_to_f16$(OBJ) \
-  extF80M_to_f32$(OBJ) \
+  extF80M_to_f32$(OBJ) \
-  extF80M_to_f64$(OBJ) \
+  extF80M_to_f64$(OBJ) \
-  extF80M_to_f128M$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
-  extF80M_roundToInt$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
-  extF80M_add$(OBJ) \
+  extF80M_add$(OBJ) \
-  extF80M_sub$(OBJ) \
+  extF80M_sub$(OBJ) \
-  extF80M_mul$(OBJ) \
+  extF80M_mul$(OBJ) \
-  extF80M_div$(OBJ) \
+  extF80M_div$(OBJ) \
-  extF80M_rem$(OBJ) \
+  extF80M_rem$(OBJ) \
-  extF80M_sqrt$(OBJ) \
+  extF80M_sqrt$(OBJ) \
-  extF80M_eq$(OBJ) \
+  extF80M_eq$(OBJ) \
-  extF80M_le$(OBJ) \
+  extF80M_le$(OBJ) \
-  extF80M_lt$(OBJ) \
+  extF80M_lt$(OBJ) \
-  extF80M_eq_signaling$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
-  extF80M_le_quiet$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
-  extF80M_lt_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
-  f128M_to_ui32$(OBJ) \
+  f128M_to_ui32$(OBJ) \
-  f128M_to_ui64$(OBJ) \
+  f128M_to_ui64$(OBJ) \
-  f128M_to_i32$(OBJ) \
+  f128M_to_i32$(OBJ) \
-  f128M_to_i64$(OBJ) \
+  f128M_to_i64$(OBJ) \
-  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
-  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
-  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
-  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
-  f128M_to_f16$(OBJ) \
+  f128M_to_f16$(OBJ) \
-  f128M_to_f32$(OBJ) \
+  f128M_to_f32$(OBJ) \
-  f128M_to_f64$(OBJ) \
+  f128M_to_f64$(OBJ) \
-  f128M_to_extF80M$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
-  f128M_roundToInt$(OBJ) \
+  f128M_roundToInt$(OBJ) \
-  f128M_add$(OBJ) \
+  f128M_add$(OBJ) \
-  f128M_sub$(OBJ) \
+  f128M_sub$(OBJ) \
-  f128M_mul$(OBJ) \
+  f128M_mul$(OBJ) \
-  f128M_mulAdd$(OBJ) \
+  f128M_mulAdd$(OBJ) \
-  f128M_div$(OBJ) \
+  f128M_div$(OBJ) \
-  f128M_rem$(OBJ) \
+  f128M_rem$(OBJ) \
-  f128M_sqrt$(OBJ) \
+  f128M_sqrt$(OBJ) \
-  f128M_eq$(OBJ) \
+  f128M_eq$(OBJ) \
-  f128M_le$(OBJ) \
+  f128M_le$(OBJ) \
-  f128M_lt$(OBJ) \
+  f128M_lt$(OBJ) \
-  f128M_eq_signaling$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
-  f128M_le_quiet$(OBJ) \
+  f128M_le_quiet$(OBJ) \
-  f128M_lt_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
-
+
-OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
-
+
-$(OBJS_ALL): \
+$(OBJS_ALL): \
-  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
-  $(SOURCE_DIR)/include/primitives.h
+  $(SOURCE_DIR)/include/primitives.h
-$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
-  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
-  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
-  $(SOURCE_DIR)/include/softfloat.h
+  $(SOURCE_DIR)/include/softfloat.h
-
+
-$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
-
+
-$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
-
+
-softfloat$(LIB): $(OBJS_ALL)
+softfloat$(LIB): $(OBJS_ALL)
-	$(DELETE) $@
+	$(DELETE) $@
-	$(MAKELIB) $^
+	$(MAKELIB) $^
-
+
-.PHONY: clean
+.PHONY: clean
-clean:
+clean:
-	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
-
+

softfloat/build/Linux-386-GCC/platform.h

@@ -1,53 +1,53 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-University of California.  All rights reserved.
+University of California.  All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#define LITTLEENDIAN 1
+#define LITTLEENDIAN 1
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#ifdef __GNUC_STDC_INLINE__
+#ifdef __GNUC_STDC_INLINE__
-#define INLINE inline
+#define INLINE inline
-#else
+#else
-#define INLINE extern inline
+#define INLINE extern inline
-#endif
+#endif
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#define SOFTFLOAT_BUILTIN_CLZ 1
+#define SOFTFLOAT_BUILTIN_CLZ 1
-#include "opts-GCC.h"
+#include "opts-GCC.h"
-
+

softfloat/build/Linux-386-SSE2-GCC/Makefile

@@ -1,325 +1,325 @@
-
+
-#=============================================================================
+#=============================================================================
-#
+#
-# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
-# Package, Release 3e, by John R. Hauser.
+# Package, Release 3e, by John R. Hauser.
-#
+#
-# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-# University of California.  All rights reserved.
+# University of California.  All rights reserved.
-#
+#
-# Redistribution and use in source and binary forms, with or without
+# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
+# modification, are permitted provided that the following conditions are met:
-#
+#
-#  1. Redistributions of source code must retain the above copyright notice,
+#  1. Redistributions of source code must retain the above copyright notice,
-#     this list of conditions, and the following disclaimer.
+#     this list of conditions, and the following disclaimer.
-#
+#
-#  2. Redistributions in binary form must reproduce the above copyright
+#  2. Redistributions in binary form must reproduce the above copyright
-#     notice, this list of conditions, and the following disclaimer in the
+#     notice, this list of conditions, and the following disclaimer in the
-#     documentation and/or other materials provided with the distribution.
+#     documentation and/or other materials provided with the distribution.
-#
+#
-#  3. Neither the name of the University nor the names of its contributors
+#  3. Neither the name of the University nor the names of its contributors
-#     may be used to endorse or promote products derived from this software
+#     may be used to endorse or promote products derived from this software
-#     without specific prior written permission.
+#     without specific prior written permission.
-#
+#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
+#
-#=============================================================================
+#=============================================================================
-
+
-SOURCE_DIR ?= ../../source
+SOURCE_DIR ?= ../../source
-SPECIALIZE_TYPE ?= 8086-SSE
+SPECIALIZE_TYPE ?= 8086-SSE
-
+
-SOFTFLOAT_OPTS ?= \
+SOFTFLOAT_OPTS ?= \
-  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-  -DSOFTFLOAT_FAST_DIV64TO32
+  -DSOFTFLOAT_FAST_DIV64TO32
-
+
-DELETE = rm -f
+DELETE = rm -f
-C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
-COMPILE_C = \
+COMPILE_C = \
-  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
+  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
-    $(C_INCLUDES) -O2 -o $@
+    $(C_INCLUDES) -O2 -o $@
-MAKELIB = ar crs $@
+MAKELIB = ar crs $@
-
+
-OBJ = .o
+OBJ = .o
-LIB = .a
+LIB = .a
-
+
-OTHER_HEADERS =
+OTHER_HEADERS =
-
+
-.PHONY: all
+.PHONY: all
-all: softfloat$(LIB)
+all: softfloat$(LIB)
-
+
-OBJS_PRIMITIVES = \
+OBJS_PRIMITIVES = \
-  s_compare96M$(OBJ) \
+  s_compare96M$(OBJ) \
-  s_compare128M$(OBJ) \
+  s_compare128M$(OBJ) \
-  s_shortShiftLeft64To96M$(OBJ) \
+  s_shortShiftLeft64To96M$(OBJ) \
-  s_shortShiftLeftM$(OBJ) \
+  s_shortShiftLeftM$(OBJ) \
-  s_shiftLeftM$(OBJ) \
+  s_shiftLeftM$(OBJ) \
-  s_shortShiftRightM$(OBJ) \
+  s_shortShiftRightM$(OBJ) \
-  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
-  s_shortShiftRightJamM$(OBJ) \
+  s_shortShiftRightJamM$(OBJ) \
-  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
-  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
-  s_shiftRightJamM$(OBJ) \
+  s_shiftRightJamM$(OBJ) \
-  s_shiftRightM$(OBJ) \
+  s_shiftRightM$(OBJ) \
-  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
-  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
-  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
-  s_countLeadingZeros64$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
-  s_addM$(OBJ) \
+  s_addM$(OBJ) \
-  s_addCarryM$(OBJ) \
+  s_addCarryM$(OBJ) \
-  s_addComplCarryM$(OBJ) \
+  s_addComplCarryM$(OBJ) \
-  s_negXM$(OBJ) \
+  s_negXM$(OBJ) \
-  s_sub1XM$(OBJ) \
+  s_sub1XM$(OBJ) \
-  s_subM$(OBJ) \
+  s_subM$(OBJ) \
-  s_mul64To128M$(OBJ) \
+  s_mul64To128M$(OBJ) \
-  s_mul128MTo256M$(OBJ) \
+  s_mul128MTo256M$(OBJ) \
-  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
-  s_approxRecip32_1$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
-  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
-  s_approxRecipSqrt32_1$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
-  s_remStepMBy32$(OBJ) \
+  s_remStepMBy32$(OBJ) \
-
+
-OBJS_SPECIALIZE = \
+OBJS_SPECIALIZE = \
-  softfloat_raiseFlags$(OBJ) \
+  softfloat_raiseFlags$(OBJ) \
-  s_f16UIToCommonNaN$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
-  s_commonNaNToF16UI$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
-  s_propagateNaNF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
-  s_f32UIToCommonNaN$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
-  s_commonNaNToF32UI$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
-  s_propagateNaNF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
-  s_f64UIToCommonNaN$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
-  s_commonNaNToF64UI$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
-  s_propagateNaNF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
-  extF80M_isSignalingNaN$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
-  s_extF80MToCommonNaN$(OBJ) \
+  s_extF80MToCommonNaN$(OBJ) \
-  s_commonNaNToExtF80M$(OBJ) \
+  s_commonNaNToExtF80M$(OBJ) \
-  s_propagateNaNExtF80M$(OBJ) \
+  s_propagateNaNExtF80M$(OBJ) \
-  f128M_isSignalingNaN$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
-  s_f128MToCommonNaN$(OBJ) \
+  s_f128MToCommonNaN$(OBJ) \
-  s_commonNaNToF128M$(OBJ) \
+  s_commonNaNToF128M$(OBJ) \
-  s_propagateNaNF128M$(OBJ) \
+  s_propagateNaNF128M$(OBJ) \
-
+
-OBJS_OTHERS = \
+OBJS_OTHERS = \
-  s_roundToUI32$(OBJ) \
+  s_roundToUI32$(OBJ) \
-  s_roundMToUI64$(OBJ) \
+  s_roundMToUI64$(OBJ) \
-  s_roundToI32$(OBJ) \
+  s_roundToI32$(OBJ) \
-  s_roundMToI64$(OBJ) \
+  s_roundMToI64$(OBJ) \
-  s_normSubnormalF16Sig$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
-  s_roundPackToF16$(OBJ) \
+  s_roundPackToF16$(OBJ) \
-  s_normRoundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
-  s_addMagsF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
-  s_subMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
-  s_mulAddF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
-  s_normSubnormalF32Sig$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
-  s_roundPackToF32$(OBJ) \
+  s_roundPackToF32$(OBJ) \
-  s_normRoundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
-  s_addMagsF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
-  s_subMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
-  s_mulAddF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
-  s_normSubnormalF64Sig$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
-  s_roundPackToF64$(OBJ) \
+  s_roundPackToF64$(OBJ) \
-  s_normRoundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
-  s_addMagsF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
-  s_subMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
-  s_mulAddF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
-  s_tryPropagateNaNExtF80M$(OBJ) \
+  s_tryPropagateNaNExtF80M$(OBJ) \
-  s_invalidExtF80M$(OBJ) \
+  s_invalidExtF80M$(OBJ) \
-  s_normExtF80SigM$(OBJ) \
+  s_normExtF80SigM$(OBJ) \
-  s_roundPackMToExtF80M$(OBJ) \
+  s_roundPackMToExtF80M$(OBJ) \
-  s_normRoundPackMToExtF80M$(OBJ) \
+  s_normRoundPackMToExtF80M$(OBJ) \
-  s_addExtF80M$(OBJ) \
+  s_addExtF80M$(OBJ) \
-  s_compareNonnormExtF80M$(OBJ) \
+  s_compareNonnormExtF80M$(OBJ) \
-  s_isNaNF128M$(OBJ) \
+  s_isNaNF128M$(OBJ) \
-  s_tryPropagateNaNF128M$(OBJ) \
+  s_tryPropagateNaNF128M$(OBJ) \
-  s_invalidF128M$(OBJ) \
+  s_invalidF128M$(OBJ) \
-  s_shiftNormSigF128M$(OBJ) \
+  s_shiftNormSigF128M$(OBJ) \
-  s_roundPackMToF128M$(OBJ) \
+  s_roundPackMToF128M$(OBJ) \
-  s_normRoundPackMToF128M$(OBJ) \
+  s_normRoundPackMToF128M$(OBJ) \
-  s_addF128M$(OBJ) \
+  s_addF128M$(OBJ) \
-  s_mulAddF128M$(OBJ) \
+  s_mulAddF128M$(OBJ) \
-  softfloat_state$(OBJ) \
+  softfloat_state$(OBJ) \
-  ui32_to_f16$(OBJ) \
+  ui32_to_f16$(OBJ) \
-  ui32_to_f32$(OBJ) \
+  ui32_to_f32$(OBJ) \
-  ui32_to_f64$(OBJ) \
+  ui32_to_f64$(OBJ) \
-  ui32_to_extF80M$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
-  ui32_to_f128M$(OBJ) \
+  ui32_to_f128M$(OBJ) \
-  ui64_to_f16$(OBJ) \
+  ui64_to_f16$(OBJ) \
-  ui64_to_f32$(OBJ) \
+  ui64_to_f32$(OBJ) \
-  ui64_to_f64$(OBJ) \
+  ui64_to_f64$(OBJ) \
-  ui64_to_extF80M$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
-  ui64_to_f128M$(OBJ) \
+  ui64_to_f128M$(OBJ) \
-  i32_to_f16$(OBJ) \
+  i32_to_f16$(OBJ) \
-  i32_to_f32$(OBJ) \
+  i32_to_f32$(OBJ) \
-  i32_to_f64$(OBJ) \
+  i32_to_f64$(OBJ) \
-  i32_to_extF80M$(OBJ) \
+  i32_to_extF80M$(OBJ) \
-  i32_to_f128M$(OBJ) \
+  i32_to_f128M$(OBJ) \
-  i64_to_f16$(OBJ) \
+  i64_to_f16$(OBJ) \
-  i64_to_f32$(OBJ) \
+  i64_to_f32$(OBJ) \
-  i64_to_f64$(OBJ) \
+  i64_to_f64$(OBJ) \
-  i64_to_extF80M$(OBJ) \
+  i64_to_extF80M$(OBJ) \
-  i64_to_f128M$(OBJ) \
+  i64_to_f128M$(OBJ) \
-  f16_to_ui32$(OBJ) \
+  f16_to_ui32$(OBJ) \
-  f16_to_ui64$(OBJ) \
+  f16_to_ui64$(OBJ) \
-  f16_to_i32$(OBJ) \
+  f16_to_i32$(OBJ) \
-  f16_to_i64$(OBJ) \
+  f16_to_i64$(OBJ) \
-  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
-  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
-  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
-  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
-  f16_to_f32$(OBJ) \
+  f16_to_f32$(OBJ) \
-  f16_to_f64$(OBJ) \
+  f16_to_f64$(OBJ) \
-  f16_to_extF80M$(OBJ) \
+  f16_to_extF80M$(OBJ) \
-  f16_to_f128M$(OBJ) \
+  f16_to_f128M$(OBJ) \
-  f16_roundToInt$(OBJ) \
+  f16_roundToInt$(OBJ) \
-  f16_add$(OBJ) \
+  f16_add$(OBJ) \
-  f16_sub$(OBJ) \
+  f16_sub$(OBJ) \
-  f16_mul$(OBJ) \
+  f16_mul$(OBJ) \
-  f16_mulAdd$(OBJ) \
+  f16_mulAdd$(OBJ) \
-  f16_div$(OBJ) \
+  f16_div$(OBJ) \
-  f16_rem$(OBJ) \
+  f16_rem$(OBJ) \
-  f16_sqrt$(OBJ) \
+  f16_sqrt$(OBJ) \
-  f16_eq$(OBJ) \
+  f16_eq$(OBJ) \
-  f16_le$(OBJ) \
+  f16_le$(OBJ) \
-  f16_lt$(OBJ) \
+  f16_lt$(OBJ) \
-  f16_eq_signaling$(OBJ) \
+  f16_eq_signaling$(OBJ) \
-  f16_le_quiet$(OBJ) \
+  f16_le_quiet$(OBJ) \
-  f16_lt_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
-  f16_isSignalingNaN$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
-  f32_to_ui32$(OBJ) \
+  f32_to_ui32$(OBJ) \
-  f32_to_ui64$(OBJ) \
+  f32_to_ui64$(OBJ) \
-  f32_to_i32$(OBJ) \
+  f32_to_i32$(OBJ) \
-  f32_to_i64$(OBJ) \
+  f32_to_i64$(OBJ) \
-  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
-  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
-  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
-  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
-  f32_to_f16$(OBJ) \
+  f32_to_f16$(OBJ) \
-  f32_to_f64$(OBJ) \
+  f32_to_f64$(OBJ) \
-  f32_to_extF80M$(OBJ) \
+  f32_to_extF80M$(OBJ) \
-  f32_to_f128M$(OBJ) \
+  f32_to_f128M$(OBJ) \
-  f32_roundToInt$(OBJ) \
+  f32_roundToInt$(OBJ) \
-  f32_add$(OBJ) \
+  f32_add$(OBJ) \
-  f32_sub$(OBJ) \
+  f32_sub$(OBJ) \
-  f32_mul$(OBJ) \
+  f32_mul$(OBJ) \
-  f32_mulAdd$(OBJ) \
+  f32_mulAdd$(OBJ) \
-  f32_div$(OBJ) \
+  f32_div$(OBJ) \
-  f32_rem$(OBJ) \
+  f32_rem$(OBJ) \
-  f32_sqrt$(OBJ) \
+  f32_sqrt$(OBJ) \
-  f32_eq$(OBJ) \
+  f32_eq$(OBJ) \
-  f32_le$(OBJ) \
+  f32_le$(OBJ) \
-  f32_lt$(OBJ) \
+  f32_lt$(OBJ) \
-  f32_eq_signaling$(OBJ) \
+  f32_eq_signaling$(OBJ) \
-  f32_le_quiet$(OBJ) \
+  f32_le_quiet$(OBJ) \
-  f32_lt_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
-  f32_isSignalingNaN$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
-  f64_to_ui32$(OBJ) \
+  f64_to_ui32$(OBJ) \
-  f64_to_ui64$(OBJ) \
+  f64_to_ui64$(OBJ) \
-  f64_to_i32$(OBJ) \
+  f64_to_i32$(OBJ) \
-  f64_to_i64$(OBJ) \
+  f64_to_i64$(OBJ) \
-  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
-  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
-  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
-  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
-  f64_to_f16$(OBJ) \
+  f64_to_f16$(OBJ) \
-  f64_to_f32$(OBJ) \
+  f64_to_f32$(OBJ) \
-  f64_to_extF80M$(OBJ) \
+  f64_to_extF80M$(OBJ) \
-  f64_to_f128M$(OBJ) \
+  f64_to_f128M$(OBJ) \
-  f64_roundToInt$(OBJ) \
+  f64_roundToInt$(OBJ) \
-  f64_add$(OBJ) \
+  f64_add$(OBJ) \
-  f64_sub$(OBJ) \
+  f64_sub$(OBJ) \
-  f64_mul$(OBJ) \
+  f64_mul$(OBJ) \
-  f64_mulAdd$(OBJ) \
+  f64_mulAdd$(OBJ) \
-  f64_div$(OBJ) \
+  f64_div$(OBJ) \
-  f64_rem$(OBJ) \
+  f64_rem$(OBJ) \
-  f64_sqrt$(OBJ) \
+  f64_sqrt$(OBJ) \
-  f64_eq$(OBJ) \
+  f64_eq$(OBJ) \
-  f64_le$(OBJ) \
+  f64_le$(OBJ) \
-  f64_lt$(OBJ) \
+  f64_lt$(OBJ) \
-  f64_eq_signaling$(OBJ) \
+  f64_eq_signaling$(OBJ) \
-  f64_le_quiet$(OBJ) \
+  f64_le_quiet$(OBJ) \
-  f64_lt_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
-  f64_isSignalingNaN$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
-  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
-  extF80M_to_ui64$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
-  extF80M_to_i32$(OBJ) \
+  extF80M_to_i32$(OBJ) \
-  extF80M_to_i64$(OBJ) \
+  extF80M_to_i64$(OBJ) \
-  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
-  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
-  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
-  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
-  extF80M_to_f16$(OBJ) \
+  extF80M_to_f16$(OBJ) \
-  extF80M_to_f32$(OBJ) \
+  extF80M_to_f32$(OBJ) \
-  extF80M_to_f64$(OBJ) \
+  extF80M_to_f64$(OBJ) \
-  extF80M_to_f128M$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
-  extF80M_roundToInt$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
-  extF80M_add$(OBJ) \
+  extF80M_add$(OBJ) \
-  extF80M_sub$(OBJ) \
+  extF80M_sub$(OBJ) \
-  extF80M_mul$(OBJ) \
+  extF80M_mul$(OBJ) \
-  extF80M_div$(OBJ) \
+  extF80M_div$(OBJ) \
-  extF80M_rem$(OBJ) \
+  extF80M_rem$(OBJ) \
-  extF80M_sqrt$(OBJ) \
+  extF80M_sqrt$(OBJ) \
-  extF80M_eq$(OBJ) \
+  extF80M_eq$(OBJ) \
-  extF80M_le$(OBJ) \
+  extF80M_le$(OBJ) \
-  extF80M_lt$(OBJ) \
+  extF80M_lt$(OBJ) \
-  extF80M_eq_signaling$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
-  extF80M_le_quiet$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
-  extF80M_lt_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
-  f128M_to_ui32$(OBJ) \
+  f128M_to_ui32$(OBJ) \
-  f128M_to_ui64$(OBJ) \
+  f128M_to_ui64$(OBJ) \
-  f128M_to_i32$(OBJ) \
+  f128M_to_i32$(OBJ) \
-  f128M_to_i64$(OBJ) \
+  f128M_to_i64$(OBJ) \
-  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
-  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
-  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
-  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
-  f128M_to_f16$(OBJ) \
+  f128M_to_f16$(OBJ) \
-  f128M_to_f32$(OBJ) \
+  f128M_to_f32$(OBJ) \
-  f128M_to_f64$(OBJ) \
+  f128M_to_f64$(OBJ) \
-  f128M_to_extF80M$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
-  f128M_roundToInt$(OBJ) \
+  f128M_roundToInt$(OBJ) \
-  f128M_add$(OBJ) \
+  f128M_add$(OBJ) \
-  f128M_sub$(OBJ) \
+  f128M_sub$(OBJ) \
-  f128M_mul$(OBJ) \
+  f128M_mul$(OBJ) \
-  f128M_mulAdd$(OBJ) \
+  f128M_mulAdd$(OBJ) \
-  f128M_div$(OBJ) \
+  f128M_div$(OBJ) \
-  f128M_rem$(OBJ) \
+  f128M_rem$(OBJ) \
-  f128M_sqrt$(OBJ) \
+  f128M_sqrt$(OBJ) \
-  f128M_eq$(OBJ) \
+  f128M_eq$(OBJ) \
-  f128M_le$(OBJ) \
+  f128M_le$(OBJ) \
-  f128M_lt$(OBJ) \
+  f128M_lt$(OBJ) \
-  f128M_eq_signaling$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
-  f128M_le_quiet$(OBJ) \
+  f128M_le_quiet$(OBJ) \
-  f128M_lt_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
-
+
-OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
-
+
-$(OBJS_ALL): \
+$(OBJS_ALL): \
-  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
-  $(SOURCE_DIR)/include/primitives.h
+  $(SOURCE_DIR)/include/primitives.h
-$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
-  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
-  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
-  $(SOURCE_DIR)/include/softfloat.h
+  $(SOURCE_DIR)/include/softfloat.h
-
+
-$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
-
+
-$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
-
+
-softfloat$(LIB): $(OBJS_ALL)
+softfloat$(LIB): $(OBJS_ALL)
-	$(DELETE) $@
+	$(DELETE) $@
-	$(MAKELIB) $^
+	$(MAKELIB) $^
-
+
-.PHONY: clean
+.PHONY: clean
-clean:
+clean:
-	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
-
+

softfloat/build/Linux-386-SSE2-GCC/platform.h

@@ -1,53 +1,53 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-University of California.  All rights reserved.
+University of California.  All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#define LITTLEENDIAN 1
+#define LITTLEENDIAN 1
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#ifdef __GNUC_STDC_INLINE__
+#ifdef __GNUC_STDC_INLINE__
-#define INLINE inline
+#define INLINE inline
-#else
+#else
-#define INLINE extern inline
+#define INLINE extern inline
-#endif
+#endif
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#define SOFTFLOAT_BUILTIN_CLZ 1
+#define SOFTFLOAT_BUILTIN_CLZ 1
-#include "opts-GCC.h"
+#include "opts-GCC.h"
-
+

softfloat/build/Linux-ARM-VFPv2-GCC/Makefile

@@ -1,323 +1,323 @@
-
+
-#=============================================================================
+#=============================================================================
-#
+#
-# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
-# Package, Release 3e, by John R. Hauser.
+# Package, Release 3e, by John R. Hauser.
-#
+#
-# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-# University of California.  All rights reserved.
+# University of California.  All rights reserved.
-#
+#
-# Redistribution and use in source and binary forms, with or without
+# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
+# modification, are permitted provided that the following conditions are met:
-#
+#
-#  1. Redistributions of source code must retain the above copyright notice,
+#  1. Redistributions of source code must retain the above copyright notice,
-#     this list of conditions, and the following disclaimer.
+#     this list of conditions, and the following disclaimer.
-#
+#
-#  2. Redistributions in binary form must reproduce the above copyright
+#  2. Redistributions in binary form must reproduce the above copyright
-#     notice, this list of conditions, and the following disclaimer in the
+#     notice, this list of conditions, and the following disclaimer in the
-#     documentation and/or other materials provided with the distribution.
+#     documentation and/or other materials provided with the distribution.
-#
+#
-#  3. Neither the name of the University nor the names of its contributors
+#  3. Neither the name of the University nor the names of its contributors
-#     may be used to endorse or promote products derived from this software
+#     may be used to endorse or promote products derived from this software
-#     without specific prior written permission.
+#     without specific prior written permission.
-#
+#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
+#
-#=============================================================================
+#=============================================================================
-
+
-SOURCE_DIR ?= ../../source
+SOURCE_DIR ?= ../../source
-SPECIALIZE_TYPE ?= ARM-VFPv2
+SPECIALIZE_TYPE ?= ARM-VFPv2
-
+
-SOFTFLOAT_OPTS ?= -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5
+SOFTFLOAT_OPTS ?= -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5
-
+
-DELETE = rm -f
+DELETE = rm -f
-C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
-COMPILE_C = \
+COMPILE_C = \
-  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
+  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
-    $(C_INCLUDES) -O2 -o $@
+    $(C_INCLUDES) -O2 -o $@
-MAKELIB = ar crs $@
+MAKELIB = ar crs $@
-
+
-OBJ = .o
+OBJ = .o
-LIB = .a
+LIB = .a
-
+
-OTHER_HEADERS =
+OTHER_HEADERS =
-
+
-.PHONY: all
+.PHONY: all
-all: softfloat$(LIB)
+all: softfloat$(LIB)
-
+
-OBJS_PRIMITIVES = \
+OBJS_PRIMITIVES = \
-  s_compare96M$(OBJ) \
+  s_compare96M$(OBJ) \
-  s_compare128M$(OBJ) \
+  s_compare128M$(OBJ) \
-  s_shortShiftLeft64To96M$(OBJ) \
+  s_shortShiftLeft64To96M$(OBJ) \
-  s_shortShiftLeftM$(OBJ) \
+  s_shortShiftLeftM$(OBJ) \
-  s_shiftLeftM$(OBJ) \
+  s_shiftLeftM$(OBJ) \
-  s_shortShiftRightM$(OBJ) \
+  s_shortShiftRightM$(OBJ) \
-  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
-  s_shortShiftRightJamM$(OBJ) \
+  s_shortShiftRightJamM$(OBJ) \
-  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
-  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
-  s_shiftRightJamM$(OBJ) \
+  s_shiftRightJamM$(OBJ) \
-  s_shiftRightM$(OBJ) \
+  s_shiftRightM$(OBJ) \
-  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
-  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
-  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
-  s_countLeadingZeros64$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
-  s_addM$(OBJ) \
+  s_addM$(OBJ) \
-  s_addCarryM$(OBJ) \
+  s_addCarryM$(OBJ) \
-  s_addComplCarryM$(OBJ) \
+  s_addComplCarryM$(OBJ) \
-  s_negXM$(OBJ) \
+  s_negXM$(OBJ) \
-  s_sub1XM$(OBJ) \
+  s_sub1XM$(OBJ) \
-  s_subM$(OBJ) \
+  s_subM$(OBJ) \
-  s_mul64To128M$(OBJ) \
+  s_mul64To128M$(OBJ) \
-  s_mul128MTo256M$(OBJ) \
+  s_mul128MTo256M$(OBJ) \
-  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
-  s_approxRecip32_1$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
-  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
-  s_approxRecipSqrt32_1$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
-  s_remStepMBy32$(OBJ) \
+  s_remStepMBy32$(OBJ) \
-
+
-OBJS_SPECIALIZE = \
+OBJS_SPECIALIZE = \
-  softfloat_raiseFlags$(OBJ) \
+  softfloat_raiseFlags$(OBJ) \
-  s_f16UIToCommonNaN$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
-  s_commonNaNToF16UI$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
-  s_propagateNaNF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
-  s_f32UIToCommonNaN$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
-  s_commonNaNToF32UI$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
-  s_propagateNaNF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
-  s_f64UIToCommonNaN$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
-  s_commonNaNToF64UI$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
-  s_propagateNaNF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
-  extF80M_isSignalingNaN$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
-  s_extF80MToCommonNaN$(OBJ) \
+  s_extF80MToCommonNaN$(OBJ) \
-  s_commonNaNToExtF80M$(OBJ) \
+  s_commonNaNToExtF80M$(OBJ) \
-  s_propagateNaNExtF80M$(OBJ) \
+  s_propagateNaNExtF80M$(OBJ) \
-  f128M_isSignalingNaN$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
-  s_f128MToCommonNaN$(OBJ) \
+  s_f128MToCommonNaN$(OBJ) \
-  s_commonNaNToF128M$(OBJ) \
+  s_commonNaNToF128M$(OBJ) \
-  s_propagateNaNF128M$(OBJ) \
+  s_propagateNaNF128M$(OBJ) \
-
+
-OBJS_OTHERS = \
+OBJS_OTHERS = \
-  s_roundToUI32$(OBJ) \
+  s_roundToUI32$(OBJ) \
-  s_roundMToUI64$(OBJ) \
+  s_roundMToUI64$(OBJ) \
-  s_roundToI32$(OBJ) \
+  s_roundToI32$(OBJ) \
-  s_roundMToI64$(OBJ) \
+  s_roundMToI64$(OBJ) \
-  s_normSubnormalF16Sig$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
-  s_roundPackToF16$(OBJ) \
+  s_roundPackToF16$(OBJ) \
-  s_normRoundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
-  s_addMagsF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
-  s_subMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
-  s_mulAddF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
-  s_normSubnormalF32Sig$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
-  s_roundPackToF32$(OBJ) \
+  s_roundPackToF32$(OBJ) \
-  s_normRoundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
-  s_addMagsF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
-  s_subMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
-  s_mulAddF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
-  s_normSubnormalF64Sig$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
-  s_roundPackToF64$(OBJ) \
+  s_roundPackToF64$(OBJ) \
-  s_normRoundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
-  s_addMagsF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
-  s_subMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
-  s_mulAddF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
-  s_tryPropagateNaNExtF80M$(OBJ) \
+  s_tryPropagateNaNExtF80M$(OBJ) \
-  s_invalidExtF80M$(OBJ) \
+  s_invalidExtF80M$(OBJ) \
-  s_normExtF80SigM$(OBJ) \
+  s_normExtF80SigM$(OBJ) \
-  s_roundPackMToExtF80M$(OBJ) \
+  s_roundPackMToExtF80M$(OBJ) \
-  s_normRoundPackMToExtF80M$(OBJ) \
+  s_normRoundPackMToExtF80M$(OBJ) \
-  s_addExtF80M$(OBJ) \
+  s_addExtF80M$(OBJ) \
-  s_compareNonnormExtF80M$(OBJ) \
+  s_compareNonnormExtF80M$(OBJ) \
-  s_isNaNF128M$(OBJ) \
+  s_isNaNF128M$(OBJ) \
-  s_tryPropagateNaNF128M$(OBJ) \
+  s_tryPropagateNaNF128M$(OBJ) \
-  s_invalidF128M$(OBJ) \
+  s_invalidF128M$(OBJ) \
-  s_shiftNormSigF128M$(OBJ) \
+  s_shiftNormSigF128M$(OBJ) \
-  s_roundPackMToF128M$(OBJ) \
+  s_roundPackMToF128M$(OBJ) \
-  s_normRoundPackMToF128M$(OBJ) \
+  s_normRoundPackMToF128M$(OBJ) \
-  s_addF128M$(OBJ) \
+  s_addF128M$(OBJ) \
-  s_mulAddF128M$(OBJ) \
+  s_mulAddF128M$(OBJ) \
-  softfloat_state$(OBJ) \
+  softfloat_state$(OBJ) \
-  ui32_to_f16$(OBJ) \
+  ui32_to_f16$(OBJ) \
-  ui32_to_f32$(OBJ) \
+  ui32_to_f32$(OBJ) \
-  ui32_to_f64$(OBJ) \
+  ui32_to_f64$(OBJ) \
-  ui32_to_extF80M$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
-  ui32_to_f128M$(OBJ) \
+  ui32_to_f128M$(OBJ) \
-  ui64_to_f16$(OBJ) \
+  ui64_to_f16$(OBJ) \
-  ui64_to_f32$(OBJ) \
+  ui64_to_f32$(OBJ) \
-  ui64_to_f64$(OBJ) \
+  ui64_to_f64$(OBJ) \
-  ui64_to_extF80M$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
-  ui64_to_f128M$(OBJ) \
+  ui64_to_f128M$(OBJ) \
-  i32_to_f16$(OBJ) \
+  i32_to_f16$(OBJ) \
-  i32_to_f32$(OBJ) \
+  i32_to_f32$(OBJ) \
-  i32_to_f64$(OBJ) \
+  i32_to_f64$(OBJ) \
-  i32_to_extF80M$(OBJ) \
+  i32_to_extF80M$(OBJ) \
-  i32_to_f128M$(OBJ) \
+  i32_to_f128M$(OBJ) \
-  i64_to_f16$(OBJ) \
+  i64_to_f16$(OBJ) \
-  i64_to_f32$(OBJ) \
+  i64_to_f32$(OBJ) \
-  i64_to_f64$(OBJ) \
+  i64_to_f64$(OBJ) \
-  i64_to_extF80M$(OBJ) \
+  i64_to_extF80M$(OBJ) \
-  i64_to_f128M$(OBJ) \
+  i64_to_f128M$(OBJ) \
-  f16_to_ui32$(OBJ) \
+  f16_to_ui32$(OBJ) \
-  f16_to_ui64$(OBJ) \
+  f16_to_ui64$(OBJ) \
-  f16_to_i32$(OBJ) \
+  f16_to_i32$(OBJ) \
-  f16_to_i64$(OBJ) \
+  f16_to_i64$(OBJ) \
-  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
-  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
-  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
-  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
-  f16_to_f32$(OBJ) \
+  f16_to_f32$(OBJ) \
-  f16_to_f64$(OBJ) \
+  f16_to_f64$(OBJ) \
-  f16_to_extF80M$(OBJ) \
+  f16_to_extF80M$(OBJ) \
-  f16_to_f128M$(OBJ) \
+  f16_to_f128M$(OBJ) \
-  f16_roundToInt$(OBJ) \
+  f16_roundToInt$(OBJ) \
-  f16_add$(OBJ) \
+  f16_add$(OBJ) \
-  f16_sub$(OBJ) \
+  f16_sub$(OBJ) \
-  f16_mul$(OBJ) \
+  f16_mul$(OBJ) \
-  f16_mulAdd$(OBJ) \
+  f16_mulAdd$(OBJ) \
-  f16_div$(OBJ) \
+  f16_div$(OBJ) \
-  f16_rem$(OBJ) \
+  f16_rem$(OBJ) \
-  f16_sqrt$(OBJ) \
+  f16_sqrt$(OBJ) \
-  f16_eq$(OBJ) \
+  f16_eq$(OBJ) \
-  f16_le$(OBJ) \
+  f16_le$(OBJ) \
-  f16_lt$(OBJ) \
+  f16_lt$(OBJ) \
-  f16_eq_signaling$(OBJ) \
+  f16_eq_signaling$(OBJ) \
-  f16_le_quiet$(OBJ) \
+  f16_le_quiet$(OBJ) \
-  f16_lt_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
-  f16_isSignalingNaN$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
-  f32_to_ui32$(OBJ) \
+  f32_to_ui32$(OBJ) \
-  f32_to_ui64$(OBJ) \
+  f32_to_ui64$(OBJ) \
-  f32_to_i32$(OBJ) \
+  f32_to_i32$(OBJ) \
-  f32_to_i64$(OBJ) \
+  f32_to_i64$(OBJ) \
-  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
-  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
-  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
-  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
-  f32_to_f16$(OBJ) \
+  f32_to_f16$(OBJ) \
-  f32_to_f64$(OBJ) \
+  f32_to_f64$(OBJ) \
-  f32_to_extF80M$(OBJ) \
+  f32_to_extF80M$(OBJ) \
-  f32_to_f128M$(OBJ) \
+  f32_to_f128M$(OBJ) \
-  f32_roundToInt$(OBJ) \
+  f32_roundToInt$(OBJ) \
-  f32_add$(OBJ) \
+  f32_add$(OBJ) \
-  f32_sub$(OBJ) \
+  f32_sub$(OBJ) \
-  f32_mul$(OBJ) \
+  f32_mul$(OBJ) \
-  f32_mulAdd$(OBJ) \
+  f32_mulAdd$(OBJ) \
-  f32_div$(OBJ) \
+  f32_div$(OBJ) \
-  f32_rem$(OBJ) \
+  f32_rem$(OBJ) \
-  f32_sqrt$(OBJ) \
+  f32_sqrt$(OBJ) \
-  f32_eq$(OBJ) \
+  f32_eq$(OBJ) \
-  f32_le$(OBJ) \
+  f32_le$(OBJ) \
-  f32_lt$(OBJ) \
+  f32_lt$(OBJ) \
-  f32_eq_signaling$(OBJ) \
+  f32_eq_signaling$(OBJ) \
-  f32_le_quiet$(OBJ) \
+  f32_le_quiet$(OBJ) \
-  f32_lt_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
-  f32_isSignalingNaN$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
-  f64_to_ui32$(OBJ) \
+  f64_to_ui32$(OBJ) \
-  f64_to_ui64$(OBJ) \
+  f64_to_ui64$(OBJ) \
-  f64_to_i32$(OBJ) \
+  f64_to_i32$(OBJ) \
-  f64_to_i64$(OBJ) \
+  f64_to_i64$(OBJ) \
-  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
-  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
-  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
-  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
-  f64_to_f16$(OBJ) \
+  f64_to_f16$(OBJ) \
-  f64_to_f32$(OBJ) \
+  f64_to_f32$(OBJ) \
-  f64_to_extF80M$(OBJ) \
+  f64_to_extF80M$(OBJ) \
-  f64_to_f128M$(OBJ) \
+  f64_to_f128M$(OBJ) \
-  f64_roundToInt$(OBJ) \
+  f64_roundToInt$(OBJ) \
-  f64_add$(OBJ) \
+  f64_add$(OBJ) \
-  f64_sub$(OBJ) \
+  f64_sub$(OBJ) \
-  f64_mul$(OBJ) \
+  f64_mul$(OBJ) \
-  f64_mulAdd$(OBJ) \
+  f64_mulAdd$(OBJ) \
-  f64_div$(OBJ) \
+  f64_div$(OBJ) \
-  f64_rem$(OBJ) \
+  f64_rem$(OBJ) \
-  f64_sqrt$(OBJ) \
+  f64_sqrt$(OBJ) \
-  f64_eq$(OBJ) \
+  f64_eq$(OBJ) \
-  f64_le$(OBJ) \
+  f64_le$(OBJ) \
-  f64_lt$(OBJ) \
+  f64_lt$(OBJ) \
-  f64_eq_signaling$(OBJ) \
+  f64_eq_signaling$(OBJ) \
-  f64_le_quiet$(OBJ) \
+  f64_le_quiet$(OBJ) \
-  f64_lt_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
-  f64_isSignalingNaN$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
-  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
-  extF80M_to_ui64$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
-  extF80M_to_i32$(OBJ) \
+  extF80M_to_i32$(OBJ) \
-  extF80M_to_i64$(OBJ) \
+  extF80M_to_i64$(OBJ) \
-  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
-  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
-  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
-  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
-  extF80M_to_f16$(OBJ) \
+  extF80M_to_f16$(OBJ) \
-  extF80M_to_f32$(OBJ) \
+  extF80M_to_f32$(OBJ) \
-  extF80M_to_f64$(OBJ) \
+  extF80M_to_f64$(OBJ) \
-  extF80M_to_f128M$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
-  extF80M_roundToInt$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
-  extF80M_add$(OBJ) \
+  extF80M_add$(OBJ) \
-  extF80M_sub$(OBJ) \
+  extF80M_sub$(OBJ) \
-  extF80M_mul$(OBJ) \
+  extF80M_mul$(OBJ) \
-  extF80M_div$(OBJ) \
+  extF80M_div$(OBJ) \
-  extF80M_rem$(OBJ) \
+  extF80M_rem$(OBJ) \
-  extF80M_sqrt$(OBJ) \
+  extF80M_sqrt$(OBJ) \
-  extF80M_eq$(OBJ) \
+  extF80M_eq$(OBJ) \
-  extF80M_le$(OBJ) \
+  extF80M_le$(OBJ) \
-  extF80M_lt$(OBJ) \
+  extF80M_lt$(OBJ) \
-  extF80M_eq_signaling$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
-  extF80M_le_quiet$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
-  extF80M_lt_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
-  f128M_to_ui32$(OBJ) \
+  f128M_to_ui32$(OBJ) \
-  f128M_to_ui64$(OBJ) \
+  f128M_to_ui64$(OBJ) \
-  f128M_to_i32$(OBJ) \
+  f128M_to_i32$(OBJ) \
-  f128M_to_i64$(OBJ) \
+  f128M_to_i64$(OBJ) \
-  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
-  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
-  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
-  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
-  f128M_to_f16$(OBJ) \
+  f128M_to_f16$(OBJ) \
-  f128M_to_f32$(OBJ) \
+  f128M_to_f32$(OBJ) \
-  f128M_to_f64$(OBJ) \
+  f128M_to_f64$(OBJ) \
-  f128M_to_extF80M$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
-  f128M_roundToInt$(OBJ) \
+  f128M_roundToInt$(OBJ) \
-  f128M_add$(OBJ) \
+  f128M_add$(OBJ) \
-  f128M_sub$(OBJ) \
+  f128M_sub$(OBJ) \
-  f128M_mul$(OBJ) \
+  f128M_mul$(OBJ) \
-  f128M_mulAdd$(OBJ) \
+  f128M_mulAdd$(OBJ) \
-  f128M_div$(OBJ) \
+  f128M_div$(OBJ) \
-  f128M_rem$(OBJ) \
+  f128M_rem$(OBJ) \
-  f128M_sqrt$(OBJ) \
+  f128M_sqrt$(OBJ) \
-  f128M_eq$(OBJ) \
+  f128M_eq$(OBJ) \
-  f128M_le$(OBJ) \
+  f128M_le$(OBJ) \
-  f128M_lt$(OBJ) \
+  f128M_lt$(OBJ) \
-  f128M_eq_signaling$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
-  f128M_le_quiet$(OBJ) \
+  f128M_le_quiet$(OBJ) \
-  f128M_lt_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
-
+
-OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
-
+
-$(OBJS_ALL): \
+$(OBJS_ALL): \
-  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
-  $(SOURCE_DIR)/include/primitives.h
+  $(SOURCE_DIR)/include/primitives.h
-$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
-  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
-  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
-  $(SOURCE_DIR)/include/softfloat.h
+  $(SOURCE_DIR)/include/softfloat.h
-
+
-$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
-
+
-$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
-
+
-softfloat$(LIB): $(OBJS_ALL)
+softfloat$(LIB): $(OBJS_ALL)
-	$(DELETE) $@
+	$(DELETE) $@
-	$(MAKELIB) $^
+	$(MAKELIB) $^
-
+
-.PHONY: clean
+.PHONY: clean
-clean:
+clean:
-	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
-
+

softfloat/build/Linux-ARM-VFPv2-GCC/platform.h

@@ -1,53 +1,53 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-University of California.  All rights reserved.
+University of California.  All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#define LITTLEENDIAN 1
+#define LITTLEENDIAN 1
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#ifdef __GNUC_STDC_INLINE__
+#ifdef __GNUC_STDC_INLINE__
-#define INLINE inline
+#define INLINE inline
-#else
+#else
-#define INLINE extern inline
+#define INLINE extern inline
-#endif
+#endif
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#define SOFTFLOAT_BUILTIN_CLZ 1
+#define SOFTFLOAT_BUILTIN_CLZ 1
-#include "opts-GCC.h"
+#include "opts-GCC.h"
-
+

softfloat/build/Linux-RISCV64-GCC/Makefile

@@ -1,399 +0,0 @@
-
-#=============================================================================
-#
-# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
-# Package, Release 3e, by John R. Hauser.
-#
-# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-# University of California.  All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-#  1. Redistributions of source code must retain the above copyright notice,
-#     this list of conditions, and the following disclaimer.
-#
-#  2. Redistributions in binary form must reproduce the above copyright
-#     notice, this list of conditions, and the following disclaimer in the
-#     documentation and/or other materials provided with the distribution.
-#
-#  3. Neither the name of the University nor the names of its contributors
-#     may be used to endorse or promote products derived from this software
-#     without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-#=============================================================================
-
-SOURCE_DIR ?= ../../source
-SPECIALIZE_TYPE ?= RISCV
-MARCH ?= rv64gcv_zfh_zfhmin
-MABI ?= lp64d
-
-SOFTFLOAT_OPTS ?= \
-  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-  -DSOFTFLOAT_FAST_DIV64TO32
-
-DELETE = rm -f
-C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
-COMPILE_C = \
-  riscv64-unknown-linux-gnu-gcc -c -march=$(MARCH) -mabi=$(MABI) -Werror-implicit-function-declaration -DSOFTFLOAT_FAST_INT64 \
-    $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
-MAKELIB = ar crs $@
-
-OBJ = .o
-LIB = .a
-
-OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h
-
-.PHONY: all
-all: softfloat$(LIB)
-
-OBJS_PRIMITIVES = \
-  s_eq128$(OBJ) \
-  s_le128$(OBJ) \
-  s_lt128$(OBJ) \
-  s_shortShiftLeft128$(OBJ) \
-  s_shortShiftRight128$(OBJ) \
-  s_shortShiftRightJam64$(OBJ) \
-  s_shortShiftRightJam64Extra$(OBJ) \
-  s_shortShiftRightJam128$(OBJ) \
-  s_shortShiftRightJam128Extra$(OBJ) \
-  s_shiftRightJam32$(OBJ) \
-  s_shiftRightJam64$(OBJ) \
-  s_shiftRightJam64Extra$(OBJ) \
-  s_shiftRightJam128$(OBJ) \
-  s_shiftRightJam128Extra$(OBJ) \
-  s_shiftRightJam256M$(OBJ) \
-  s_countLeadingZeros8$(OBJ) \
-  s_countLeadingZeros16$(OBJ) \
-  s_countLeadingZeros32$(OBJ) \
-  s_countLeadingZeros64$(OBJ) \
-  s_add128$(OBJ) \
-  s_add256M$(OBJ) \
-  s_sub128$(OBJ) \
-  s_sub256M$(OBJ) \
-  s_mul64ByShifted32To128$(OBJ) \
-  s_mul64To128$(OBJ) \
-  s_mul128By32$(OBJ) \
-  s_mul128To256M$(OBJ) \
-  s_approxRecip_1Ks$(OBJ) \
-  s_approxRecip32_1$(OBJ) \
-  s_approxRecipSqrt_1Ks$(OBJ) \
-  s_approxRecipSqrt32_1$(OBJ) \
-
-OBJS_SPECIALIZE = \
-  softfloat_raiseFlags$(OBJ) \
-  s_f16UIToCommonNaN$(OBJ) \
-  s_commonNaNToF16UI$(OBJ) \
-  s_propagateNaNF16UI$(OBJ) \
-  s_bf16UIToCommonNaN$(OBJ) \
-  s_commonNaNToBF16UI$(OBJ) \
-  s_f32UIToCommonNaN$(OBJ) \
-  s_commonNaNToF32UI$(OBJ) \
-  s_propagateNaNF32UI$(OBJ) \
-  s_f64UIToCommonNaN$(OBJ) \
-  s_commonNaNToF64UI$(OBJ) \
-  s_propagateNaNF64UI$(OBJ) \
-  extF80M_isSignalingNaN$(OBJ) \
-  s_extF80UIToCommonNaN$(OBJ) \
-  s_commonNaNToExtF80UI$(OBJ) \
-  s_propagateNaNExtF80UI$(OBJ) \
-  f128M_isSignalingNaN$(OBJ) \
-  s_f128UIToCommonNaN$(OBJ) \
-  s_commonNaNToF128UI$(OBJ) \
-  s_propagateNaNF128UI$(OBJ) \
-
-OBJS_OTHERS = \
-  s_roundToUI32$(OBJ) \
-  s_roundToUI64$(OBJ) \
-  s_roundToI32$(OBJ) \
-  s_roundToI64$(OBJ) \
-  s_normSubnormalBF16Sig$(OBJ) \
-  s_roundPackToBF16$(OBJ) \
-  s_normSubnormalF16Sig$(OBJ) \
-  s_roundPackToF16$(OBJ) \
-  s_normRoundPackToF16$(OBJ) \
-  s_addMagsF16$(OBJ) \
-  s_subMagsF16$(OBJ) \
-  s_mulAddF16$(OBJ) \
-  s_normSubnormalF32Sig$(OBJ) \
-  s_roundPackToF32$(OBJ) \
-  s_normRoundPackToF32$(OBJ) \
-  s_addMagsF32$(OBJ) \
-  s_subMagsF32$(OBJ) \
-  s_mulAddF32$(OBJ) \
-  s_normSubnormalF64Sig$(OBJ) \
-  s_roundPackToF64$(OBJ) \
-  s_normRoundPackToF64$(OBJ) \
-  s_addMagsF64$(OBJ) \
-  s_subMagsF64$(OBJ) \
-  s_mulAddF64$(OBJ) \
-  s_normSubnormalExtF80Sig$(OBJ) \
-  s_roundPackToExtF80$(OBJ) \
-  s_normRoundPackToExtF80$(OBJ) \
-  s_addMagsExtF80$(OBJ) \
-  s_subMagsExtF80$(OBJ) \
-  s_normSubnormalF128Sig$(OBJ) \
-  s_roundPackToF128$(OBJ) \
-  s_normRoundPackToF128$(OBJ) \
-  s_addMagsF128$(OBJ) \
-  s_subMagsF128$(OBJ) \
-  s_mulAddF128$(OBJ) \
-  softfloat_state$(OBJ) \
-  ui32_to_f16$(OBJ) \
-  ui32_to_f32$(OBJ) \
-  ui32_to_f64$(OBJ) \
-  ui32_to_extF80$(OBJ) \
-  ui32_to_extF80M$(OBJ) \
-  ui32_to_f128$(OBJ) \
-  ui32_to_f128M$(OBJ) \
-  ui64_to_f16$(OBJ) \
-  ui64_to_f32$(OBJ) \
-  ui64_to_f64$(OBJ) \
-  ui64_to_extF80$(OBJ) \
-  ui64_to_extF80M$(OBJ) \
-  ui64_to_f128$(OBJ) \
-  ui64_to_f128M$(OBJ) \
-  i32_to_f16$(OBJ) \
-  i32_to_f32$(OBJ) \
-  i32_to_f64$(OBJ) \
-  i32_to_extF80$(OBJ) \
-  i32_to_extF80M$(OBJ) \
-  i32_to_f128$(OBJ) \
-  i32_to_f128M$(OBJ) \
-  i64_to_f16$(OBJ) \
-  i64_to_f32$(OBJ) \
-  i64_to_f64$(OBJ) \
-  i64_to_extF80$(OBJ) \
-  i64_to_extF80M$(OBJ) \
-  i64_to_f128$(OBJ) \
-  i64_to_f128M$(OBJ) \
-  bf16_isSignalingNaN$(OBJ) \
-  bf16_to_f32$(OBJ) \
-  f16_to_ui32$(OBJ) \
-  f16_to_ui64$(OBJ) \
-  f16_to_i32$(OBJ) \
-  f16_to_i64$(OBJ) \
-  f16_to_ui32_r_minMag$(OBJ) \
-  f16_to_ui64_r_minMag$(OBJ) \
-  f16_to_i32_r_minMag$(OBJ) \
-  f16_to_i64_r_minMag$(OBJ) \
-  f16_to_f32$(OBJ) \
-  f16_to_f64$(OBJ) \
-  f16_to_extF80$(OBJ) \
-  f16_to_extF80M$(OBJ) \
-  f16_to_f128$(OBJ) \
-  f16_to_f128M$(OBJ) \
-  f16_roundToInt$(OBJ) \
-  f16_add$(OBJ) \
-  f16_sub$(OBJ) \
-  f16_mul$(OBJ) \
-  f16_mulAdd$(OBJ) \
-  f16_div$(OBJ) \
-  f16_rem$(OBJ) \
-  f16_sqrt$(OBJ) \
-  f16_eq$(OBJ) \
-  f16_le$(OBJ) \
-  f16_lt$(OBJ) \
-  f16_eq_signaling$(OBJ) \
-  f16_le_quiet$(OBJ) \
-  f16_lt_quiet$(OBJ) \
-  f16_isSignalingNaN$(OBJ) \
-  f32_to_ui32$(OBJ) \
-  f32_to_ui64$(OBJ) \
-  f32_to_i32$(OBJ) \
-  f32_to_i64$(OBJ) \
-  f32_to_ui32_r_minMag$(OBJ) \
-  f32_to_ui64_r_minMag$(OBJ) \
-  f32_to_i32_r_minMag$(OBJ) \
-  f32_to_i64_r_minMag$(OBJ) \
-  f32_to_bf16$(OBJ) \
-  f32_to_f16$(OBJ) \
-  f32_to_f64$(OBJ) \
-  f32_to_extF80$(OBJ) \
-  f32_to_extF80M$(OBJ) \
-  f32_to_f128$(OBJ) \
-  f32_to_f128M$(OBJ) \
-  f32_roundToInt$(OBJ) \
-  f32_add$(OBJ) \
-  f32_sub$(OBJ) \
-  f32_mul$(OBJ) \
-  f32_mulAdd$(OBJ) \
-  f32_div$(OBJ) \
-  f32_rem$(OBJ) \
-  f32_sqrt$(OBJ) \
-  f32_eq$(OBJ) \
-  f32_le$(OBJ) \
-  f32_lt$(OBJ) \
-  f32_eq_signaling$(OBJ) \
-  f32_le_quiet$(OBJ) \
-  f32_lt_quiet$(OBJ) \
-  f32_isSignalingNaN$(OBJ) \
-  f64_to_ui32$(OBJ) \
-  f64_to_ui64$(OBJ) \
-  f64_to_i32$(OBJ) \
-  f64_to_i64$(OBJ) \
-  f64_to_ui32_r_minMag$(OBJ) \
-  f64_to_ui64_r_minMag$(OBJ) \
-  f64_to_i32_r_minMag$(OBJ) \
-  f64_to_i64_r_minMag$(OBJ) \
-  f64_to_f16$(OBJ) \
-  f64_to_f32$(OBJ) \
-  f64_to_extF80$(OBJ) \
-  f64_to_extF80M$(OBJ) \
-  f64_to_f128$(OBJ) \
-  f64_to_f128M$(OBJ) \
-  f64_roundToInt$(OBJ) \
-  f64_add$(OBJ) \
-  f64_sub$(OBJ) \
-  f64_mul$(OBJ) \
-  f64_mulAdd$(OBJ) \
-  f64_div$(OBJ) \
-  f64_rem$(OBJ) \
-  f64_sqrt$(OBJ) \
-  f64_eq$(OBJ) \
-  f64_le$(OBJ) \
-  f64_lt$(OBJ) \
-  f64_eq_signaling$(OBJ) \
-  f64_le_quiet$(OBJ) \
-  f64_lt_quiet$(OBJ) \
-  f64_isSignalingNaN$(OBJ) \
-  extF80_to_ui32$(OBJ) \
-  extF80_to_ui64$(OBJ) \
-  extF80_to_i32$(OBJ) \
-  extF80_to_i64$(OBJ) \
-  extF80_to_ui32_r_minMag$(OBJ) \
-  extF80_to_ui64_r_minMag$(OBJ) \
-  extF80_to_i32_r_minMag$(OBJ) \
-  extF80_to_i64_r_minMag$(OBJ) \
-  extF80_to_f16$(OBJ) \
-  extF80_to_f32$(OBJ) \
-  extF80_to_f64$(OBJ) \
-  extF80_to_f128$(OBJ) \
-  extF80_roundToInt$(OBJ) \
-  extF80_add$(OBJ) \
-  extF80_sub$(OBJ) \
-  extF80_mul$(OBJ) \
-  extF80_div$(OBJ) \
-  extF80_rem$(OBJ) \
-  extF80_sqrt$(OBJ) \
-  extF80_eq$(OBJ) \
-  extF80_le$(OBJ) \
-  extF80_lt$(OBJ) \
-  extF80_eq_signaling$(OBJ) \
-  extF80_le_quiet$(OBJ) \
-  extF80_lt_quiet$(OBJ) \
-  extF80_isSignalingNaN$(OBJ) \
-  extF80M_to_ui32$(OBJ) \
-  extF80M_to_ui64$(OBJ) \
-  extF80M_to_i32$(OBJ) \
-  extF80M_to_i64$(OBJ) \
-  extF80M_to_ui32_r_minMag$(OBJ) \
-  extF80M_to_ui64_r_minMag$(OBJ) \
-  extF80M_to_i32_r_minMag$(OBJ) \
-  extF80M_to_i64_r_minMag$(OBJ) \
-  extF80M_to_f16$(OBJ) \
-  extF80M_to_f32$(OBJ) \
-  extF80M_to_f64$(OBJ) \
-  extF80M_to_f128M$(OBJ) \
-  extF80M_roundToInt$(OBJ) \
-  extF80M_add$(OBJ) \
-  extF80M_sub$(OBJ) \
-  extF80M_mul$(OBJ) \
-  extF80M_div$(OBJ) \
-  extF80M_rem$(OBJ) \
-  extF80M_sqrt$(OBJ) \
-  extF80M_eq$(OBJ) \
-  extF80M_le$(OBJ) \
-  extF80M_lt$(OBJ) \
-  extF80M_eq_signaling$(OBJ) \
-  extF80M_le_quiet$(OBJ) \
-  extF80M_lt_quiet$(OBJ) \
-  f128_to_ui32$(OBJ) \
-  f128_to_ui64$(OBJ) \
-  f128_to_i32$(OBJ) \
-  f128_to_i64$(OBJ) \
-  f128_to_ui32_r_minMag$(OBJ) \
-  f128_to_ui64_r_minMag$(OBJ) \
-  f128_to_i32_r_minMag$(OBJ) \
-  f128_to_i64_r_minMag$(OBJ) \
-  f128_to_f16$(OBJ) \
-  f128_to_f32$(OBJ) \
-  f128_to_extF80$(OBJ) \
-  f128_to_f64$(OBJ) \
-  f128_roundToInt$(OBJ) \
-  f128_add$(OBJ) \
-  f128_sub$(OBJ) \
-  f128_mul$(OBJ) \
-  f128_mulAdd$(OBJ) \
-  f128_div$(OBJ) \
-  f128_rem$(OBJ) \
-  f128_sqrt$(OBJ) \
-  f128_eq$(OBJ) \
-  f128_le$(OBJ) \
-  f128_lt$(OBJ) \
-  f128_eq_signaling$(OBJ) \
-  f128_le_quiet$(OBJ) \
-  f128_lt_quiet$(OBJ) \
-  f128_isSignalingNaN$(OBJ) \
-  f128M_to_ui32$(OBJ) \
-  f128M_to_ui64$(OBJ) \
-  f128M_to_i32$(OBJ) \
-  f128M_to_i64$(OBJ) \
-  f128M_to_ui32_r_minMag$(OBJ) \
-  f128M_to_ui64_r_minMag$(OBJ) \
-  f128M_to_i32_r_minMag$(OBJ) \
-  f128M_to_i64_r_minMag$(OBJ) \
-  f128M_to_f16$(OBJ) \
-  f128M_to_f32$(OBJ) \
-  f128M_to_extF80M$(OBJ) \
-  f128M_to_f64$(OBJ) \
-  f128M_roundToInt$(OBJ) \
-  f128M_add$(OBJ) \
-  f128M_sub$(OBJ) \
-  f128M_mul$(OBJ) \
-  f128M_mulAdd$(OBJ) \
-  f128M_div$(OBJ) \
-  f128M_rem$(OBJ) \
-  f128M_sqrt$(OBJ) \
-  f128M_eq$(OBJ) \
-  f128M_le$(OBJ) \
-  f128M_lt$(OBJ) \
-  f128M_eq_signaling$(OBJ) \
-  f128M_le_quiet$(OBJ) \
-  f128M_lt_quiet$(OBJ) \
-
-OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
-
-$(OBJS_ALL): \
-  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
-  $(SOURCE_DIR)/include/primitives.h
-$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
-  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
-  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
-  $(SOURCE_DIR)/include/softfloat.h
-
-$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$*.c
-
-$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
-
-softfloat$(LIB): $(OBJS_ALL)
-	$(DELETE) $@
-	$(MAKELIB) $^
-
-.PHONY: clean
-clean:
-	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
-

softfloat/build/Linux-RISCV64-GCC/platform.h

@@ -1,54 +0,0 @@
-
-/*============================================================================
-
-This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-University of California.  All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
-#define LITTLEENDIAN 1
-
-/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
-#ifdef __GNUC_STDC_INLINE__
-#define INLINE inline
-#else
-#define INLINE extern inline
-#endif
-
-/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
-#define SOFTFLOAT_BUILTIN_CLZ 1
-#define SOFTFLOAT_INTRINSIC_INT128 1
-#include "opts-GCC.h"
-

softfloat/build/Linux-x86_64-GCC/Makefile

@@ -1,397 +1,390 @@
-
+
-#=============================================================================
+#=============================================================================
-#
+#
-# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
-# Package, Release 3e, by John R. Hauser.
+# Package, Release 3e, by John R. Hauser.
-#
+#
-# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-# University of California.  All rights reserved.
+# University of California.  All rights reserved.
-#
+#
-# Redistribution and use in source and binary forms, with or without
+# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
+# modification, are permitted provided that the following conditions are met:
-#
+#
-#  1. Redistributions of source code must retain the above copyright notice,
+#  1. Redistributions of source code must retain the above copyright notice,
-#     this list of conditions, and the following disclaimer.
+#     this list of conditions, and the following disclaimer.
-#
+#
-#  2. Redistributions in binary form must reproduce the above copyright
+#  2. Redistributions in binary form must reproduce the above copyright
-#     notice, this list of conditions, and the following disclaimer in the
+#     notice, this list of conditions, and the following disclaimer in the
-#     documentation and/or other materials provided with the distribution.
+#     documentation and/or other materials provided with the distribution.
-#
+#
-#  3. Neither the name of the University nor the names of its contributors
+#  3. Neither the name of the University nor the names of its contributors
-#     may be used to endorse or promote products derived from this software
+#     may be used to endorse or promote products derived from this software
-#     without specific prior written permission.
+#     without specific prior written permission.
-#
+#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
+#
-#=============================================================================
+#=============================================================================
-
+
-SOURCE_DIR ?= ../../source
+SOURCE_DIR ?= ../../source
-SPECIALIZE_TYPE ?= 8086-SSE
+SPECIALIZE_TYPE ?= 8086-SSE
-
+
-SOFTFLOAT_OPTS ?= \
+SOFTFLOAT_OPTS ?= \
-  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-  -DSOFTFLOAT_FAST_DIV64TO32
+  -DSOFTFLOAT_FAST_DIV64TO32
-
+
-DELETE = rm -f
+DELETE = rm -f
-C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
-COMPILE_C = \
+COMPILE_C = \
-  gcc -c -Werror-implicit-function-declaration -DSOFTFLOAT_FAST_INT64 \
+  gcc -c -Werror-implicit-function-declaration -DSOFTFLOAT_FAST_INT64 \
-    $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
+    $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
-MAKELIB = ar crs $@
+MAKELIB = ar crs $@
-
+
-OBJ = .o
+OBJ = .o
-LIB = .a
+LIB = .a
-
+
-OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h
+OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h
-
+
-.PHONY: all
+.PHONY: all
-all: softfloat$(LIB)
+all: softfloat$(LIB)
-
+
-OBJS_PRIMITIVES = \
+OBJS_PRIMITIVES = \
-  s_eq128$(OBJ) \
+  s_eq128$(OBJ) \
-  s_le128$(OBJ) \
+  s_le128$(OBJ) \
-  s_lt128$(OBJ) \
+  s_lt128$(OBJ) \
-  s_shortShiftLeft128$(OBJ) \
+  s_shortShiftLeft128$(OBJ) \
-  s_shortShiftRight128$(OBJ) \
+  s_shortShiftRight128$(OBJ) \
-  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
-  s_shortShiftRightJam64Extra$(OBJ) \
+  s_shortShiftRightJam64Extra$(OBJ) \
-  s_shortShiftRightJam128$(OBJ) \
+  s_shortShiftRightJam128$(OBJ) \
-  s_shortShiftRightJam128Extra$(OBJ) \
+  s_shortShiftRightJam128Extra$(OBJ) \
-  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
-  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
-  s_shiftRightJam64Extra$(OBJ) \
+  s_shiftRightJam64Extra$(OBJ) \
-  s_shiftRightJam128$(OBJ) \
+  s_shiftRightJam128$(OBJ) \
-  s_shiftRightJam128Extra$(OBJ) \
+  s_shiftRightJam128Extra$(OBJ) \
-  s_shiftRightJam256M$(OBJ) \
+  s_shiftRightJam256M$(OBJ) \
-  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
-  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
-  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
-  s_countLeadingZeros64$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
-  s_add128$(OBJ) \
+  s_add128$(OBJ) \
-  s_add256M$(OBJ) \
+  s_add256M$(OBJ) \
-  s_sub128$(OBJ) \
+  s_sub128$(OBJ) \
-  s_sub256M$(OBJ) \
+  s_sub256M$(OBJ) \
-  s_mul64ByShifted32To128$(OBJ) \
+  s_mul64ByShifted32To128$(OBJ) \
-  s_mul64To128$(OBJ) \
+  s_mul64To128$(OBJ) \
-  s_mul128By32$(OBJ) \
+  s_mul128By32$(OBJ) \
-  s_mul128To256M$(OBJ) \
+  s_mul128To256M$(OBJ) \
-  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
-  s_approxRecip32_1$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
-  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
-  s_approxRecipSqrt32_1$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
-
+
-OBJS_SPECIALIZE = \
+OBJS_SPECIALIZE = \
-  softfloat_raiseFlags$(OBJ) \
+  softfloat_raiseFlags$(OBJ) \
-  s_f16UIToCommonNaN$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
-  s_commonNaNToF16UI$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
-  s_propagateNaNF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
-  s_bf16UIToCommonNaN$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
-  s_commonNaNToBF16UI$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
-  s_f32UIToCommonNaN$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
-  s_commonNaNToF32UI$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
-  s_propagateNaNF32UI$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
-  s_f64UIToCommonNaN$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
-  s_commonNaNToF64UI$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
-  s_propagateNaNF64UI$(OBJ) \
+  s_extF80UIToCommonNaN$(OBJ) \
-  extF80M_isSignalingNaN$(OBJ) \
+  s_commonNaNToExtF80UI$(OBJ) \
-  s_extF80UIToCommonNaN$(OBJ) \
+  s_propagateNaNExtF80UI$(OBJ) \
-  s_commonNaNToExtF80UI$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
-  s_propagateNaNExtF80UI$(OBJ) \
+  s_f128UIToCommonNaN$(OBJ) \
-  f128M_isSignalingNaN$(OBJ) \
+  s_commonNaNToF128UI$(OBJ) \
-  s_f128UIToCommonNaN$(OBJ) \
+  s_propagateNaNF128UI$(OBJ) \
-  s_commonNaNToF128UI$(OBJ) \
+
-  s_propagateNaNF128UI$(OBJ) \
+OBJS_OTHERS = \
-
+  s_roundToUI32$(OBJ) \
-OBJS_OTHERS = \
+  s_roundToUI64$(OBJ) \
-  s_roundToUI32$(OBJ) \
+  s_roundToI32$(OBJ) \
-  s_roundToUI64$(OBJ) \
+  s_roundToI64$(OBJ) \
-  s_roundToI32$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
-  s_roundToI64$(OBJ) \
+  s_roundPackToF16$(OBJ) \
-  s_normSubnormalBF16Sig$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
-  s_roundPackToBF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
-  s_normSubnormalF16Sig$(OBJ) \
+  s_subMagsF16$(OBJ) \
-  s_roundPackToF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
-  s_normRoundPackToF16$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
-  s_addMagsF16$(OBJ) \
+  s_roundPackToF32$(OBJ) \
-  s_subMagsF16$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
-  s_mulAddF16$(OBJ) \
+  s_addMagsF32$(OBJ) \
-  s_normSubnormalF32Sig$(OBJ) \
+  s_subMagsF32$(OBJ) \
-  s_roundPackToF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
-  s_normRoundPackToF32$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
-  s_addMagsF32$(OBJ) \
+  s_roundPackToF64$(OBJ) \
-  s_subMagsF32$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
-  s_mulAddF32$(OBJ) \
+  s_addMagsF64$(OBJ) \
-  s_normSubnormalF64Sig$(OBJ) \
+  s_subMagsF64$(OBJ) \
-  s_roundPackToF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
-  s_normRoundPackToF64$(OBJ) \
+  s_normSubnormalExtF80Sig$(OBJ) \
-  s_addMagsF64$(OBJ) \
+  s_roundPackToExtF80$(OBJ) \
-  s_subMagsF64$(OBJ) \
+  s_normRoundPackToExtF80$(OBJ) \
-  s_mulAddF64$(OBJ) \
+  s_addMagsExtF80$(OBJ) \
-  s_normSubnormalExtF80Sig$(OBJ) \
+  s_subMagsExtF80$(OBJ) \
-  s_roundPackToExtF80$(OBJ) \
+  s_normSubnormalF128Sig$(OBJ) \
-  s_normRoundPackToExtF80$(OBJ) \
+  s_roundPackToF128$(OBJ) \
-  s_addMagsExtF80$(OBJ) \
+  s_normRoundPackToF128$(OBJ) \
-  s_subMagsExtF80$(OBJ) \
+  s_addMagsF128$(OBJ) \
-  s_normSubnormalF128Sig$(OBJ) \
+  s_subMagsF128$(OBJ) \
-  s_roundPackToF128$(OBJ) \
+  s_mulAddF128$(OBJ) \
-  s_normRoundPackToF128$(OBJ) \
+  softfloat_state$(OBJ) \
-  s_addMagsF128$(OBJ) \
+  ui32_to_f16$(OBJ) \
-  s_subMagsF128$(OBJ) \
+  ui32_to_f32$(OBJ) \
-  s_mulAddF128$(OBJ) \
+  ui32_to_f64$(OBJ) \
-  softfloat_state$(OBJ) \
+  ui32_to_extF80$(OBJ) \
-  ui32_to_f16$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
-  ui32_to_f32$(OBJ) \
+  ui32_to_f128$(OBJ) \
-  ui32_to_f64$(OBJ) \
+  ui32_to_f128M$(OBJ) \
-  ui32_to_extF80$(OBJ) \
+  ui64_to_f16$(OBJ) \
-  ui32_to_extF80M$(OBJ) \
+  ui64_to_f32$(OBJ) \
-  ui32_to_f128$(OBJ) \
+  ui64_to_f64$(OBJ) \
-  ui32_to_f128M$(OBJ) \
+  ui64_to_extF80$(OBJ) \
-  ui64_to_f16$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
-  ui64_to_f32$(OBJ) \
+  ui64_to_f128$(OBJ) \
-  ui64_to_f64$(OBJ) \
+  ui64_to_f128M$(OBJ) \
-  ui64_to_extF80$(OBJ) \
+  i32_to_f16$(OBJ) \
-  ui64_to_extF80M$(OBJ) \
+  i32_to_f32$(OBJ) \
-  ui64_to_f128$(OBJ) \
+  i32_to_f64$(OBJ) \
-  ui64_to_f128M$(OBJ) \
+  i32_to_extF80$(OBJ) \
-  i32_to_f16$(OBJ) \
+  i32_to_extF80M$(OBJ) \
-  i32_to_f32$(OBJ) \
+  i32_to_f128$(OBJ) \
-  i32_to_f64$(OBJ) \
+  i32_to_f128M$(OBJ) \
-  i32_to_extF80$(OBJ) \
+  i64_to_f16$(OBJ) \
-  i32_to_extF80M$(OBJ) \
+  i64_to_f32$(OBJ) \
-  i32_to_f128$(OBJ) \
+  i64_to_f64$(OBJ) \
-  i32_to_f128M$(OBJ) \
+  i64_to_extF80$(OBJ) \
-  i64_to_f16$(OBJ) \
+  i64_to_extF80M$(OBJ) \
-  i64_to_f32$(OBJ) \
+  i64_to_f128$(OBJ) \
-  i64_to_f64$(OBJ) \
+  i64_to_f128M$(OBJ) \
-  i64_to_extF80$(OBJ) \
+  f16_to_ui32$(OBJ) \
-  i64_to_extF80M$(OBJ) \
+  f16_to_ui64$(OBJ) \
-  i64_to_f128$(OBJ) \
+  f16_to_i32$(OBJ) \
-  i64_to_f128M$(OBJ) \
+  f16_to_i64$(OBJ) \
-  bf16_isSignalingNaN$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
-  bf16_to_f32$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
-  f16_to_ui32$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
-  f16_to_ui64$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
-  f16_to_i32$(OBJ) \
+  f16_to_f32$(OBJ) \
-  f16_to_i64$(OBJ) \
+  f16_to_f64$(OBJ) \
-  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_extF80$(OBJ) \
-  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_extF80M$(OBJ) \
-  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_f128$(OBJ) \
-  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_f128M$(OBJ) \
-  f16_to_f32$(OBJ) \
+  f16_roundToInt$(OBJ) \
-  f16_to_f64$(OBJ) \
+  f16_add$(OBJ) \
-  f16_to_extF80$(OBJ) \
+  f16_sub$(OBJ) \
-  f16_to_extF80M$(OBJ) \
+  f16_mul$(OBJ) \
-  f16_to_f128$(OBJ) \
+  f16_mulAdd$(OBJ) \
-  f16_to_f128M$(OBJ) \
+  f16_div$(OBJ) \
-  f16_roundToInt$(OBJ) \
+  f16_rem$(OBJ) \
-  f16_add$(OBJ) \
+  f16_sqrt$(OBJ) \
-  f16_sub$(OBJ) \
+  f16_eq$(OBJ) \
-  f16_mul$(OBJ) \
+  f16_le$(OBJ) \
-  f16_mulAdd$(OBJ) \
+  f16_lt$(OBJ) \
-  f16_div$(OBJ) \
+  f16_eq_signaling$(OBJ) \
-  f16_rem$(OBJ) \
+  f16_le_quiet$(OBJ) \
-  f16_sqrt$(OBJ) \
+  f16_lt_quiet$(OBJ) \
-  f16_eq$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
-  f16_le$(OBJ) \
+  f32_to_ui32$(OBJ) \
-  f16_lt$(OBJ) \
+  f32_to_ui64$(OBJ) \
-  f16_eq_signaling$(OBJ) \
+  f32_to_i32$(OBJ) \
-  f16_le_quiet$(OBJ) \
+  f32_to_i64$(OBJ) \
-  f16_lt_quiet$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
-  f16_isSignalingNaN$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
-  f32_to_ui32$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
-  f32_to_ui64$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
-  f32_to_i32$(OBJ) \
+  f32_to_f16$(OBJ) \
-  f32_to_i64$(OBJ) \
+  f32_to_f64$(OBJ) \
-  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_extF80$(OBJ) \
-  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_extF80M$(OBJ) \
-  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_f128$(OBJ) \
-  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_f128M$(OBJ) \
-  f32_to_bf16$(OBJ) \
+  f32_roundToInt$(OBJ) \
-  f32_to_f16$(OBJ) \
+  f32_add$(OBJ) \
-  f32_to_f64$(OBJ) \
+  f32_sub$(OBJ) \
-  f32_to_extF80$(OBJ) \
+  f32_mul$(OBJ) \
-  f32_to_extF80M$(OBJ) \
+  f32_mulAdd$(OBJ) \
-  f32_to_f128$(OBJ) \
+  f32_div$(OBJ) \
-  f32_to_f128M$(OBJ) \
+  f32_rem$(OBJ) \
-  f32_roundToInt$(OBJ) \
+  f32_sqrt$(OBJ) \
-  f32_add$(OBJ) \
+  f32_eq$(OBJ) \
-  f32_sub$(OBJ) \
+  f32_le$(OBJ) \
-  f32_mul$(OBJ) \
+  f32_lt$(OBJ) \
-  f32_mulAdd$(OBJ) \
+  f32_eq_signaling$(OBJ) \
-  f32_div$(OBJ) \
+  f32_le_quiet$(OBJ) \
-  f32_rem$(OBJ) \
+  f32_lt_quiet$(OBJ) \
-  f32_sqrt$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
-  f32_eq$(OBJ) \
+  f64_to_ui32$(OBJ) \
-  f32_le$(OBJ) \
+  f64_to_ui64$(OBJ) \
-  f32_lt$(OBJ) \
+  f64_to_i32$(OBJ) \
-  f32_eq_signaling$(OBJ) \
+  f64_to_i64$(OBJ) \
-  f32_le_quiet$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
-  f32_lt_quiet$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
-  f32_isSignalingNaN$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
-  f64_to_ui32$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
-  f64_to_ui64$(OBJ) \
+  f64_to_f16$(OBJ) \
-  f64_to_i32$(OBJ) \
+  f64_to_f32$(OBJ) \
-  f64_to_i64$(OBJ) \
+  f64_to_extF80$(OBJ) \
-  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_extF80M$(OBJ) \
-  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_f128$(OBJ) \
-  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_f128M$(OBJ) \
-  f64_to_i64_r_minMag$(OBJ) \
+  f64_roundToInt$(OBJ) \
-  f64_to_f16$(OBJ) \
+  f64_add$(OBJ) \
-  f64_to_f32$(OBJ) \
+  f64_sub$(OBJ) \
-  f64_to_extF80$(OBJ) \
+  f64_mul$(OBJ) \
-  f64_to_extF80M$(OBJ) \
+  f64_mulAdd$(OBJ) \
-  f64_to_f128$(OBJ) \
+  f64_div$(OBJ) \
-  f64_to_f128M$(OBJ) \
+  f64_rem$(OBJ) \
-  f64_roundToInt$(OBJ) \
+  f64_sqrt$(OBJ) \
-  f64_add$(OBJ) \
+  f64_eq$(OBJ) \
-  f64_sub$(OBJ) \
+  f64_le$(OBJ) \
-  f64_mul$(OBJ) \
+  f64_lt$(OBJ) \
-  f64_mulAdd$(OBJ) \
+  f64_eq_signaling$(OBJ) \
-  f64_div$(OBJ) \
+  f64_le_quiet$(OBJ) \
-  f64_rem$(OBJ) \
+  f64_lt_quiet$(OBJ) \
-  f64_sqrt$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
-  f64_eq$(OBJ) \
+  extF80_to_ui32$(OBJ) \
-  f64_le$(OBJ) \
+  extF80_to_ui64$(OBJ) \
-  f64_lt$(OBJ) \
+  extF80_to_i32$(OBJ) \
-  f64_eq_signaling$(OBJ) \
+  extF80_to_i64$(OBJ) \
-  f64_le_quiet$(OBJ) \
+  extF80_to_ui32_r_minMag$(OBJ) \
-  f64_lt_quiet$(OBJ) \
+  extF80_to_ui64_r_minMag$(OBJ) \
-  f64_isSignalingNaN$(OBJ) \
+  extF80_to_i32_r_minMag$(OBJ) \
-  extF80_to_ui32$(OBJ) \
+  extF80_to_i64_r_minMag$(OBJ) \
-  extF80_to_ui64$(OBJ) \
+  extF80_to_f16$(OBJ) \
-  extF80_to_i32$(OBJ) \
+  extF80_to_f32$(OBJ) \
-  extF80_to_i64$(OBJ) \
+  extF80_to_f64$(OBJ) \
-  extF80_to_ui32_r_minMag$(OBJ) \
+  extF80_to_f128$(OBJ) \
-  extF80_to_ui64_r_minMag$(OBJ) \
+  extF80_roundToInt$(OBJ) \
-  extF80_to_i32_r_minMag$(OBJ) \
+  extF80_add$(OBJ) \
-  extF80_to_i64_r_minMag$(OBJ) \
+  extF80_sub$(OBJ) \
-  extF80_to_f16$(OBJ) \
+  extF80_mul$(OBJ) \
-  extF80_to_f32$(OBJ) \
+  extF80_div$(OBJ) \
-  extF80_to_f64$(OBJ) \
+  extF80_rem$(OBJ) \
-  extF80_to_f128$(OBJ) \
+  extF80_sqrt$(OBJ) \
-  extF80_roundToInt$(OBJ) \
+  extF80_eq$(OBJ) \
-  extF80_add$(OBJ) \
+  extF80_le$(OBJ) \
-  extF80_sub$(OBJ) \
+  extF80_lt$(OBJ) \
-  extF80_mul$(OBJ) \
+  extF80_eq_signaling$(OBJ) \
-  extF80_div$(OBJ) \
+  extF80_le_quiet$(OBJ) \
-  extF80_rem$(OBJ) \
+  extF80_lt_quiet$(OBJ) \
-  extF80_sqrt$(OBJ) \
+  extF80_isSignalingNaN$(OBJ) \
-  extF80_eq$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
-  extF80_le$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
-  extF80_lt$(OBJ) \
+  extF80M_to_i32$(OBJ) \
-  extF80_eq_signaling$(OBJ) \
+  extF80M_to_i64$(OBJ) \
-  extF80_le_quiet$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
-  extF80_lt_quiet$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
-  extF80_isSignalingNaN$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
-  extF80M_to_ui32$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
-  extF80M_to_ui64$(OBJ) \
+  extF80M_to_f16$(OBJ) \
-  extF80M_to_i32$(OBJ) \
+  extF80M_to_f32$(OBJ) \
-  extF80M_to_i64$(OBJ) \
+  extF80M_to_f64$(OBJ) \
-  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
-  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
-  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_add$(OBJ) \
-  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_sub$(OBJ) \
-  extF80M_to_f16$(OBJ) \
+  extF80M_mul$(OBJ) \
-  extF80M_to_f32$(OBJ) \
+  extF80M_div$(OBJ) \
-  extF80M_to_f64$(OBJ) \
+  extF80M_rem$(OBJ) \
-  extF80M_to_f128M$(OBJ) \
+  extF80M_sqrt$(OBJ) \
-  extF80M_roundToInt$(OBJ) \
+  extF80M_eq$(OBJ) \
-  extF80M_add$(OBJ) \
+  extF80M_le$(OBJ) \
-  extF80M_sub$(OBJ) \
+  extF80M_lt$(OBJ) \
-  extF80M_mul$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
-  extF80M_div$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
-  extF80M_rem$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
-  extF80M_sqrt$(OBJ) \
+  f128_to_ui32$(OBJ) \
-  extF80M_eq$(OBJ) \
+  f128_to_ui64$(OBJ) \
-  extF80M_le$(OBJ) \
+  f128_to_i32$(OBJ) \
-  extF80M_lt$(OBJ) \
+  f128_to_i64$(OBJ) \
-  extF80M_eq_signaling$(OBJ) \
+  f128_to_ui32_r_minMag$(OBJ) \
-  extF80M_le_quiet$(OBJ) \
+  f128_to_ui64_r_minMag$(OBJ) \
-  extF80M_lt_quiet$(OBJ) \
+  f128_to_i32_r_minMag$(OBJ) \
-  f128_to_ui32$(OBJ) \
+  f128_to_i64_r_minMag$(OBJ) \
-  f128_to_ui64$(OBJ) \
+  f128_to_f16$(OBJ) \
-  f128_to_i32$(OBJ) \
+  f128_to_f32$(OBJ) \
-  f128_to_i64$(OBJ) \
+  f128_to_extF80$(OBJ) \
-  f128_to_ui32_r_minMag$(OBJ) \
+  f128_to_f64$(OBJ) \
-  f128_to_ui64_r_minMag$(OBJ) \
+  f128_roundToInt$(OBJ) \
-  f128_to_i32_r_minMag$(OBJ) \
+  f128_add$(OBJ) \
-  f128_to_i64_r_minMag$(OBJ) \
+  f128_sub$(OBJ) \
-  f128_to_f16$(OBJ) \
+  f128_mul$(OBJ) \
-  f128_to_f32$(OBJ) \
+  f128_mulAdd$(OBJ) \
-  f128_to_extF80$(OBJ) \
+  f128_div$(OBJ) \
-  f128_to_f64$(OBJ) \
+  f128_rem$(OBJ) \
-  f128_roundToInt$(OBJ) \
+  f128_sqrt$(OBJ) \
-  f128_add$(OBJ) \
+  f128_eq$(OBJ) \
-  f128_sub$(OBJ) \
+  f128_le$(OBJ) \
-  f128_mul$(OBJ) \
+  f128_lt$(OBJ) \
-  f128_mulAdd$(OBJ) \
+  f128_eq_signaling$(OBJ) \
-  f128_div$(OBJ) \
+  f128_le_quiet$(OBJ) \
-  f128_rem$(OBJ) \
+  f128_lt_quiet$(OBJ) \
-  f128_sqrt$(OBJ) \
+  f128_isSignalingNaN$(OBJ) \
-  f128_eq$(OBJ) \
+  f128M_to_ui32$(OBJ) \
-  f128_le$(OBJ) \
+  f128M_to_ui64$(OBJ) \
-  f128_lt$(OBJ) \
+  f128M_to_i32$(OBJ) \
-  f128_eq_signaling$(OBJ) \
+  f128M_to_i64$(OBJ) \
-  f128_le_quiet$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
-  f128_lt_quiet$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
-  f128_isSignalingNaN$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
-  f128M_to_ui32$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
-  f128M_to_ui64$(OBJ) \
+  f128M_to_f16$(OBJ) \
-  f128M_to_i32$(OBJ) \
+  f128M_to_f32$(OBJ) \
-  f128M_to_i64$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
-  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_f64$(OBJ) \
-  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_roundToInt$(OBJ) \
-  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_add$(OBJ) \
-  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_sub$(OBJ) \
-  f128M_to_f16$(OBJ) \
+  f128M_mul$(OBJ) \
-  f128M_to_f32$(OBJ) \
+  f128M_mulAdd$(OBJ) \
-  f128M_to_extF80M$(OBJ) \
+  f128M_div$(OBJ) \
-  f128M_to_f64$(OBJ) \
+  f128M_rem$(OBJ) \
-  f128M_roundToInt$(OBJ) \
+  f128M_sqrt$(OBJ) \
-  f128M_add$(OBJ) \
+  f128M_eq$(OBJ) \
-  f128M_sub$(OBJ) \
+  f128M_le$(OBJ) \
-  f128M_mul$(OBJ) \
+  f128M_lt$(OBJ) \
-  f128M_mulAdd$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
-  f128M_div$(OBJ) \
+  f128M_le_quiet$(OBJ) \
-  f128M_rem$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
-  f128M_sqrt$(OBJ) \
+
-  f128M_eq$(OBJ) \
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
-  f128M_le$(OBJ) \
+
-  f128M_lt$(OBJ) \
+$(OBJS_ALL): \
-  f128M_eq_signaling$(OBJ) \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
-  f128M_le_quiet$(OBJ) \
+  $(SOURCE_DIR)/include/primitives.h
-  f128M_lt_quiet$(OBJ) \
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
-
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
-OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
-
+  $(SOURCE_DIR)/include/softfloat.h
-$(OBJS_ALL): \
+
-  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
-  $(SOURCE_DIR)/include/primitives.h
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
-$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+
-  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
-  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
-  $(SOURCE_DIR)/include/softfloat.h
+
-
+softfloat$(LIB): $(OBJS_ALL)
-$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+	$(DELETE) $@
-	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+	$(MAKELIB) $^
-
+
-$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+.PHONY: clean
-	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+clean:
-
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
-softfloat$(LIB): $(OBJS_ALL)
+
-	$(DELETE) $@
-	$(MAKELIB) $^
-
-.PHONY: clean
-clean:
-	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
-

softfloat/build/Linux-x86_64-GCC/platform.h

@@ -1,56 +1,55 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-University of California.  All rights reserved.
+University of California.  All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
- *----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#define LITTLEENDIAN 1
+#define LITTLEENDIAN 1
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
- *----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#ifdef __GNUC_STDC_INLINE__
+#ifdef __GNUC_STDC_INLINE__
-//#define INLINE inline
+//#define INLINE inline
-#define INLINE static
+#define INLINE static
-#else
+#else
-#define INLINE extern inline
+#define INLINE extern inline
-#endif
+#endif
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
- *----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#ifdef __GNUC__
+#define SOFTFLOAT_BUILTIN_CLZ 1
-#define SOFTFLOAT_BUILTIN_CLZ 1
+#define SOFTFLOAT_INTRINSIC_INT128 1
-#define SOFTFLOAT_INTRINSIC_INT128 1
+#include "opts-GCC.h"
-#endif
+
-#include "opts-GCC.h"

softfloat/build/Win32-MinGW/Makefile

@@ -1,325 +1,325 @@
-
+
-#=============================================================================
+#=============================================================================
-#
+#
-# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
-# Package, Release 3e, by John R. Hauser.
+# Package, Release 3e, by John R. Hauser.
-#
+#
-# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-# University of California.  All rights reserved.
+# University of California.  All rights reserved.
-#
+#
-# Redistribution and use in source and binary forms, with or without
+# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
+# modification, are permitted provided that the following conditions are met:
-#
+#
-#  1. Redistributions of source code must retain the above copyright notice,
+#  1. Redistributions of source code must retain the above copyright notice,
-#     this list of conditions, and the following disclaimer.
+#     this list of conditions, and the following disclaimer.
-#
+#
-#  2. Redistributions in binary form must reproduce the above copyright
+#  2. Redistributions in binary form must reproduce the above copyright
-#     notice, this list of conditions, and the following disclaimer in the
+#     notice, this list of conditions, and the following disclaimer in the
-#     documentation and/or other materials provided with the distribution.
+#     documentation and/or other materials provided with the distribution.
-#
+#
-#  3. Neither the name of the University nor the names of its contributors
+#  3. Neither the name of the University nor the names of its contributors
-#     may be used to endorse or promote products derived from this software
+#     may be used to endorse or promote products derived from this software
-#     without specific prior written permission.
+#     without specific prior written permission.
-#
+#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
+#
-#=============================================================================
+#=============================================================================
-
+
-SOURCE_DIR ?= ../../source
+SOURCE_DIR ?= ../../source
-SPECIALIZE_TYPE ?= 8086
+SPECIALIZE_TYPE ?= 8086
-
+
-SOFTFLOAT_OPTS ?= \
+SOFTFLOAT_OPTS ?= \
-  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-  -DSOFTFLOAT_FAST_DIV64TO32
+  -DSOFTFLOAT_FAST_DIV64TO32
-
+
-DELETE = rm -f
+DELETE = rm -f
-C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
-COMPILE_C = \
+COMPILE_C = \
-  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
+  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
-    $(C_INCLUDES) -O2 -o $@
+    $(C_INCLUDES) -O2 -o $@
-MAKELIB = ar crs $@
+MAKELIB = ar crs $@
-
+
-OBJ = .o
+OBJ = .o
-LIB = .a
+LIB = .a
-
+
-OTHER_HEADERS =
+OTHER_HEADERS =
-
+
-.PHONY: all
+.PHONY: all
-all: softfloat$(LIB)
+all: softfloat$(LIB)
-
+
-OBJS_PRIMITIVES = \
+OBJS_PRIMITIVES = \
-  s_compare96M$(OBJ) \
+  s_compare96M$(OBJ) \
-  s_compare128M$(OBJ) \
+  s_compare128M$(OBJ) \
-  s_shortShiftLeft64To96M$(OBJ) \
+  s_shortShiftLeft64To96M$(OBJ) \
-  s_shortShiftLeftM$(OBJ) \
+  s_shortShiftLeftM$(OBJ) \
-  s_shiftLeftM$(OBJ) \
+  s_shiftLeftM$(OBJ) \
-  s_shortShiftRightM$(OBJ) \
+  s_shortShiftRightM$(OBJ) \
-  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
-  s_shortShiftRightJamM$(OBJ) \
+  s_shortShiftRightJamM$(OBJ) \
-  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
-  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
-  s_shiftRightJamM$(OBJ) \
+  s_shiftRightJamM$(OBJ) \
-  s_shiftRightM$(OBJ) \
+  s_shiftRightM$(OBJ) \
-  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
-  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
-  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
-  s_countLeadingZeros64$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
-  s_addM$(OBJ) \
+  s_addM$(OBJ) \
-  s_addCarryM$(OBJ) \
+  s_addCarryM$(OBJ) \
-  s_addComplCarryM$(OBJ) \
+  s_addComplCarryM$(OBJ) \
-  s_negXM$(OBJ) \
+  s_negXM$(OBJ) \
-  s_sub1XM$(OBJ) \
+  s_sub1XM$(OBJ) \
-  s_subM$(OBJ) \
+  s_subM$(OBJ) \
-  s_mul64To128M$(OBJ) \
+  s_mul64To128M$(OBJ) \
-  s_mul128MTo256M$(OBJ) \
+  s_mul128MTo256M$(OBJ) \
-  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
-  s_approxRecip32_1$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
-  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
-  s_approxRecipSqrt32_1$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
-  s_remStepMBy32$(OBJ) \
+  s_remStepMBy32$(OBJ) \
-
+
-OBJS_SPECIALIZE = \
+OBJS_SPECIALIZE = \
-  softfloat_raiseFlags$(OBJ) \
+  softfloat_raiseFlags$(OBJ) \
-  s_f16UIToCommonNaN$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
-  s_commonNaNToF16UI$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
-  s_propagateNaNF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
-  s_f32UIToCommonNaN$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
-  s_commonNaNToF32UI$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
-  s_propagateNaNF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
-  s_f64UIToCommonNaN$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
-  s_commonNaNToF64UI$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
-  s_propagateNaNF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
-  extF80M_isSignalingNaN$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
-  s_extF80MToCommonNaN$(OBJ) \
+  s_extF80MToCommonNaN$(OBJ) \
-  s_commonNaNToExtF80M$(OBJ) \
+  s_commonNaNToExtF80M$(OBJ) \
-  s_propagateNaNExtF80M$(OBJ) \
+  s_propagateNaNExtF80M$(OBJ) \
-  f128M_isSignalingNaN$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
-  s_f128MToCommonNaN$(OBJ) \
+  s_f128MToCommonNaN$(OBJ) \
-  s_commonNaNToF128M$(OBJ) \
+  s_commonNaNToF128M$(OBJ) \
-  s_propagateNaNF128M$(OBJ) \
+  s_propagateNaNF128M$(OBJ) \
-
+
-OBJS_OTHERS = \
+OBJS_OTHERS = \
-  s_roundToUI32$(OBJ) \
+  s_roundToUI32$(OBJ) \
-  s_roundMToUI64$(OBJ) \
+  s_roundMToUI64$(OBJ) \
-  s_roundToI32$(OBJ) \
+  s_roundToI32$(OBJ) \
-  s_roundMToI64$(OBJ) \
+  s_roundMToI64$(OBJ) \
-  s_normSubnormalF16Sig$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
-  s_roundPackToF16$(OBJ) \
+  s_roundPackToF16$(OBJ) \
-  s_normRoundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
-  s_addMagsF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
-  s_subMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
-  s_mulAddF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
-  s_normSubnormalF32Sig$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
-  s_roundPackToF32$(OBJ) \
+  s_roundPackToF32$(OBJ) \
-  s_normRoundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
-  s_addMagsF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
-  s_subMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
-  s_mulAddF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
-  s_normSubnormalF64Sig$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
-  s_roundPackToF64$(OBJ) \
+  s_roundPackToF64$(OBJ) \
-  s_normRoundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
-  s_addMagsF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
-  s_subMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
-  s_mulAddF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
-  s_tryPropagateNaNExtF80M$(OBJ) \
+  s_tryPropagateNaNExtF80M$(OBJ) \
-  s_invalidExtF80M$(OBJ) \
+  s_invalidExtF80M$(OBJ) \
-  s_normExtF80SigM$(OBJ) \
+  s_normExtF80SigM$(OBJ) \
-  s_roundPackMToExtF80M$(OBJ) \
+  s_roundPackMToExtF80M$(OBJ) \
-  s_normRoundPackMToExtF80M$(OBJ) \
+  s_normRoundPackMToExtF80M$(OBJ) \
-  s_addExtF80M$(OBJ) \
+  s_addExtF80M$(OBJ) \
-  s_compareNonnormExtF80M$(OBJ) \
+  s_compareNonnormExtF80M$(OBJ) \
-  s_isNaNF128M$(OBJ) \
+  s_isNaNF128M$(OBJ) \
-  s_tryPropagateNaNF128M$(OBJ) \
+  s_tryPropagateNaNF128M$(OBJ) \
-  s_invalidF128M$(OBJ) \
+  s_invalidF128M$(OBJ) \
-  s_shiftNormSigF128M$(OBJ) \
+  s_shiftNormSigF128M$(OBJ) \
-  s_roundPackMToF128M$(OBJ) \
+  s_roundPackMToF128M$(OBJ) \
-  s_normRoundPackMToF128M$(OBJ) \
+  s_normRoundPackMToF128M$(OBJ) \
-  s_addF128M$(OBJ) \
+  s_addF128M$(OBJ) \
-  s_mulAddF128M$(OBJ) \
+  s_mulAddF128M$(OBJ) \
-  softfloat_state$(OBJ) \
+  softfloat_state$(OBJ) \
-  ui32_to_f16$(OBJ) \
+  ui32_to_f16$(OBJ) \
-  ui32_to_f32$(OBJ) \
+  ui32_to_f32$(OBJ) \
-  ui32_to_f64$(OBJ) \
+  ui32_to_f64$(OBJ) \
-  ui32_to_extF80M$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
-  ui32_to_f128M$(OBJ) \
+  ui32_to_f128M$(OBJ) \
-  ui64_to_f16$(OBJ) \
+  ui64_to_f16$(OBJ) \
-  ui64_to_f32$(OBJ) \
+  ui64_to_f32$(OBJ) \
-  ui64_to_f64$(OBJ) \
+  ui64_to_f64$(OBJ) \
-  ui64_to_extF80M$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
-  ui64_to_f128M$(OBJ) \
+  ui64_to_f128M$(OBJ) \
-  i32_to_f16$(OBJ) \
+  i32_to_f16$(OBJ) \
-  i32_to_f32$(OBJ) \
+  i32_to_f32$(OBJ) \
-  i32_to_f64$(OBJ) \
+  i32_to_f64$(OBJ) \
-  i32_to_extF80M$(OBJ) \
+  i32_to_extF80M$(OBJ) \
-  i32_to_f128M$(OBJ) \
+  i32_to_f128M$(OBJ) \
-  i64_to_f16$(OBJ) \
+  i64_to_f16$(OBJ) \
-  i64_to_f32$(OBJ) \
+  i64_to_f32$(OBJ) \
-  i64_to_f64$(OBJ) \
+  i64_to_f64$(OBJ) \
-  i64_to_extF80M$(OBJ) \
+  i64_to_extF80M$(OBJ) \
-  i64_to_f128M$(OBJ) \
+  i64_to_f128M$(OBJ) \
-  f16_to_ui32$(OBJ) \
+  f16_to_ui32$(OBJ) \
-  f16_to_ui64$(OBJ) \
+  f16_to_ui64$(OBJ) \
-  f16_to_i32$(OBJ) \
+  f16_to_i32$(OBJ) \
-  f16_to_i64$(OBJ) \
+  f16_to_i64$(OBJ) \
-  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
-  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
-  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
-  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
-  f16_to_f32$(OBJ) \
+  f16_to_f32$(OBJ) \
-  f16_to_f64$(OBJ) \
+  f16_to_f64$(OBJ) \
-  f16_to_extF80M$(OBJ) \
+  f16_to_extF80M$(OBJ) \
-  f16_to_f128M$(OBJ) \
+  f16_to_f128M$(OBJ) \
-  f16_roundToInt$(OBJ) \
+  f16_roundToInt$(OBJ) \
-  f16_add$(OBJ) \
+  f16_add$(OBJ) \
-  f16_sub$(OBJ) \
+  f16_sub$(OBJ) \
-  f16_mul$(OBJ) \
+  f16_mul$(OBJ) \
-  f16_mulAdd$(OBJ) \
+  f16_mulAdd$(OBJ) \
-  f16_div$(OBJ) \
+  f16_div$(OBJ) \
-  f16_rem$(OBJ) \
+  f16_rem$(OBJ) \
-  f16_sqrt$(OBJ) \
+  f16_sqrt$(OBJ) \
-  f16_eq$(OBJ) \
+  f16_eq$(OBJ) \
-  f16_le$(OBJ) \
+  f16_le$(OBJ) \
-  f16_lt$(OBJ) \
+  f16_lt$(OBJ) \
-  f16_eq_signaling$(OBJ) \
+  f16_eq_signaling$(OBJ) \
-  f16_le_quiet$(OBJ) \
+  f16_le_quiet$(OBJ) \
-  f16_lt_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
-  f16_isSignalingNaN$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
-  f32_to_ui32$(OBJ) \
+  f32_to_ui32$(OBJ) \
-  f32_to_ui64$(OBJ) \
+  f32_to_ui64$(OBJ) \
-  f32_to_i32$(OBJ) \
+  f32_to_i32$(OBJ) \
-  f32_to_i64$(OBJ) \
+  f32_to_i64$(OBJ) \
-  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
-  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
-  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
-  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
-  f32_to_f16$(OBJ) \
+  f32_to_f16$(OBJ) \
-  f32_to_f64$(OBJ) \
+  f32_to_f64$(OBJ) \
-  f32_to_extF80M$(OBJ) \
+  f32_to_extF80M$(OBJ) \
-  f32_to_f128M$(OBJ) \
+  f32_to_f128M$(OBJ) \
-  f32_roundToInt$(OBJ) \
+  f32_roundToInt$(OBJ) \
-  f32_add$(OBJ) \
+  f32_add$(OBJ) \
-  f32_sub$(OBJ) \
+  f32_sub$(OBJ) \
-  f32_mul$(OBJ) \
+  f32_mul$(OBJ) \
-  f32_mulAdd$(OBJ) \
+  f32_mulAdd$(OBJ) \
-  f32_div$(OBJ) \
+  f32_div$(OBJ) \
-  f32_rem$(OBJ) \
+  f32_rem$(OBJ) \
-  f32_sqrt$(OBJ) \
+  f32_sqrt$(OBJ) \
-  f32_eq$(OBJ) \
+  f32_eq$(OBJ) \
-  f32_le$(OBJ) \
+  f32_le$(OBJ) \
-  f32_lt$(OBJ) \
+  f32_lt$(OBJ) \
-  f32_eq_signaling$(OBJ) \
+  f32_eq_signaling$(OBJ) \
-  f32_le_quiet$(OBJ) \
+  f32_le_quiet$(OBJ) \
-  f32_lt_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
-  f32_isSignalingNaN$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
-  f64_to_ui32$(OBJ) \
+  f64_to_ui32$(OBJ) \
-  f64_to_ui64$(OBJ) \
+  f64_to_ui64$(OBJ) \
-  f64_to_i32$(OBJ) \
+  f64_to_i32$(OBJ) \
-  f64_to_i64$(OBJ) \
+  f64_to_i64$(OBJ) \
-  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
-  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
-  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
-  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
-  f64_to_f16$(OBJ) \
+  f64_to_f16$(OBJ) \
-  f64_to_f32$(OBJ) \
+  f64_to_f32$(OBJ) \
-  f64_to_extF80M$(OBJ) \
+  f64_to_extF80M$(OBJ) \
-  f64_to_f128M$(OBJ) \
+  f64_to_f128M$(OBJ) \
-  f64_roundToInt$(OBJ) \
+  f64_roundToInt$(OBJ) \
-  f64_add$(OBJ) \
+  f64_add$(OBJ) \
-  f64_sub$(OBJ) \
+  f64_sub$(OBJ) \
-  f64_mul$(OBJ) \
+  f64_mul$(OBJ) \
-  f64_mulAdd$(OBJ) \
+  f64_mulAdd$(OBJ) \
-  f64_div$(OBJ) \
+  f64_div$(OBJ) \
-  f64_rem$(OBJ) \
+  f64_rem$(OBJ) \
-  f64_sqrt$(OBJ) \
+  f64_sqrt$(OBJ) \
-  f64_eq$(OBJ) \
+  f64_eq$(OBJ) \
-  f64_le$(OBJ) \
+  f64_le$(OBJ) \
-  f64_lt$(OBJ) \
+  f64_lt$(OBJ) \
-  f64_eq_signaling$(OBJ) \
+  f64_eq_signaling$(OBJ) \
-  f64_le_quiet$(OBJ) \
+  f64_le_quiet$(OBJ) \
-  f64_lt_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
-  f64_isSignalingNaN$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
-  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
-  extF80M_to_ui64$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
-  extF80M_to_i32$(OBJ) \
+  extF80M_to_i32$(OBJ) \
-  extF80M_to_i64$(OBJ) \
+  extF80M_to_i64$(OBJ) \
-  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
-  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
-  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
-  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
-  extF80M_to_f16$(OBJ) \
+  extF80M_to_f16$(OBJ) \
-  extF80M_to_f32$(OBJ) \
+  extF80M_to_f32$(OBJ) \
-  extF80M_to_f64$(OBJ) \
+  extF80M_to_f64$(OBJ) \
-  extF80M_to_f128M$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
-  extF80M_roundToInt$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
-  extF80M_add$(OBJ) \
+  extF80M_add$(OBJ) \
-  extF80M_sub$(OBJ) \
+  extF80M_sub$(OBJ) \
-  extF80M_mul$(OBJ) \
+  extF80M_mul$(OBJ) \
-  extF80M_div$(OBJ) \
+  extF80M_div$(OBJ) \
-  extF80M_rem$(OBJ) \
+  extF80M_rem$(OBJ) \
-  extF80M_sqrt$(OBJ) \
+  extF80M_sqrt$(OBJ) \
-  extF80M_eq$(OBJ) \
+  extF80M_eq$(OBJ) \
-  extF80M_le$(OBJ) \
+  extF80M_le$(OBJ) \
-  extF80M_lt$(OBJ) \
+  extF80M_lt$(OBJ) \
-  extF80M_eq_signaling$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
-  extF80M_le_quiet$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
-  extF80M_lt_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
-  f128M_to_ui32$(OBJ) \
+  f128M_to_ui32$(OBJ) \
-  f128M_to_ui64$(OBJ) \
+  f128M_to_ui64$(OBJ) \
-  f128M_to_i32$(OBJ) \
+  f128M_to_i32$(OBJ) \
-  f128M_to_i64$(OBJ) \
+  f128M_to_i64$(OBJ) \
-  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
-  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
-  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
-  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
-  f128M_to_f16$(OBJ) \
+  f128M_to_f16$(OBJ) \
-  f128M_to_f32$(OBJ) \
+  f128M_to_f32$(OBJ) \
-  f128M_to_f64$(OBJ) \
+  f128M_to_f64$(OBJ) \
-  f128M_to_extF80M$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
-  f128M_roundToInt$(OBJ) \
+  f128M_roundToInt$(OBJ) \
-  f128M_add$(OBJ) \
+  f128M_add$(OBJ) \
-  f128M_sub$(OBJ) \
+  f128M_sub$(OBJ) \
-  f128M_mul$(OBJ) \
+  f128M_mul$(OBJ) \
-  f128M_mulAdd$(OBJ) \
+  f128M_mulAdd$(OBJ) \
-  f128M_div$(OBJ) \
+  f128M_div$(OBJ) \
-  f128M_rem$(OBJ) \
+  f128M_rem$(OBJ) \
-  f128M_sqrt$(OBJ) \
+  f128M_sqrt$(OBJ) \
-  f128M_eq$(OBJ) \
+  f128M_eq$(OBJ) \
-  f128M_le$(OBJ) \
+  f128M_le$(OBJ) \
-  f128M_lt$(OBJ) \
+  f128M_lt$(OBJ) \
-  f128M_eq_signaling$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
-  f128M_le_quiet$(OBJ) \
+  f128M_le_quiet$(OBJ) \
-  f128M_lt_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
-
+
-OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
-
+
-$(OBJS_ALL): \
+$(OBJS_ALL): \
-  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
-  $(SOURCE_DIR)/include/primitives.h
+  $(SOURCE_DIR)/include/primitives.h
-$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
-  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
-  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
-  $(SOURCE_DIR)/include/softfloat.h
+  $(SOURCE_DIR)/include/softfloat.h
-
+
-$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
-
+
-$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
-
+
-softfloat$(LIB): $(OBJS_ALL)
+softfloat$(LIB): $(OBJS_ALL)
-	$(DELETE) $@
+	$(DELETE) $@
-	$(MAKELIB) $^
+	$(MAKELIB) $^
-
+
-.PHONY: clean
+.PHONY: clean
-clean:
+clean:
-	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
-
+

softfloat/build/Win32-MinGW/platform.h

@@ -1,53 +1,53 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-University of California.  All rights reserved.
+University of California.  All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#define LITTLEENDIAN 1
+#define LITTLEENDIAN 1
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#ifdef __GNUC_STDC_INLINE__
+#ifdef __GNUC_STDC_INLINE__
-#define INLINE inline
+#define INLINE inline
-#else
+#else
-#define INLINE extern inline
+#define INLINE extern inline
-#endif
+#endif
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#define SOFTFLOAT_BUILTIN_CLZ 1
+#define SOFTFLOAT_BUILTIN_CLZ 1
-#include "opts-GCC.h"
+#include "opts-GCC.h"
-
+

softfloat/build/Win32-SSE2-MinGW/Makefile

@@ -1,325 +1,325 @@
-
+
-#=============================================================================
+#=============================================================================
-#
+#
-# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
-# Package, Release 3e, by John R. Hauser.
+# Package, Release 3e, by John R. Hauser.
-#
+#
-# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-# University of California.  All rights reserved.
+# University of California.  All rights reserved.
-#
+#
-# Redistribution and use in source and binary forms, with or without
+# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
+# modification, are permitted provided that the following conditions are met:
-#
+#
-#  1. Redistributions of source code must retain the above copyright notice,
+#  1. Redistributions of source code must retain the above copyright notice,
-#     this list of conditions, and the following disclaimer.
+#     this list of conditions, and the following disclaimer.
-#
+#
-#  2. Redistributions in binary form must reproduce the above copyright
+#  2. Redistributions in binary form must reproduce the above copyright
-#     notice, this list of conditions, and the following disclaimer in the
+#     notice, this list of conditions, and the following disclaimer in the
-#     documentation and/or other materials provided with the distribution.
+#     documentation and/or other materials provided with the distribution.
-#
+#
-#  3. Neither the name of the University nor the names of its contributors
+#  3. Neither the name of the University nor the names of its contributors
-#     may be used to endorse or promote products derived from this software
+#     may be used to endorse or promote products derived from this software
-#     without specific prior written permission.
+#     without specific prior written permission.
-#
+#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
+#
-#=============================================================================
+#=============================================================================
-
+
-SOURCE_DIR ?= ../../source
+SOURCE_DIR ?= ../../source
-SPECIALIZE_TYPE ?= 8086-SSE
+SPECIALIZE_TYPE ?= 8086-SSE
-
+
-SOFTFLOAT_OPTS ?= \
+SOFTFLOAT_OPTS ?= \
-  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-  -DSOFTFLOAT_FAST_DIV64TO32
+  -DSOFTFLOAT_FAST_DIV64TO32
-
+
-DELETE = rm -f
+DELETE = rm -f
-C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
-COMPILE_C = \
+COMPILE_C = \
-  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
+  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
-    $(C_INCLUDES) -O2 -o $@
+    $(C_INCLUDES) -O2 -o $@
-MAKELIB = ar crs $@
+MAKELIB = ar crs $@
-
+
-OBJ = .o
+OBJ = .o
-LIB = .a
+LIB = .a
-
+
-OTHER_HEADERS =
+OTHER_HEADERS =
-
+
-.PHONY: all
+.PHONY: all
-all: softfloat$(LIB)
+all: softfloat$(LIB)
-
+
-OBJS_PRIMITIVES = \
+OBJS_PRIMITIVES = \
-  s_compare96M$(OBJ) \
+  s_compare96M$(OBJ) \
-  s_compare128M$(OBJ) \
+  s_compare128M$(OBJ) \
-  s_shortShiftLeft64To96M$(OBJ) \
+  s_shortShiftLeft64To96M$(OBJ) \
-  s_shortShiftLeftM$(OBJ) \
+  s_shortShiftLeftM$(OBJ) \
-  s_shiftLeftM$(OBJ) \
+  s_shiftLeftM$(OBJ) \
-  s_shortShiftRightM$(OBJ) \
+  s_shortShiftRightM$(OBJ) \
-  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
-  s_shortShiftRightJamM$(OBJ) \
+  s_shortShiftRightJamM$(OBJ) \
-  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
-  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
-  s_shiftRightJamM$(OBJ) \
+  s_shiftRightJamM$(OBJ) \
-  s_shiftRightM$(OBJ) \
+  s_shiftRightM$(OBJ) \
-  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
-  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
-  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
-  s_countLeadingZeros64$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
-  s_addM$(OBJ) \
+  s_addM$(OBJ) \
-  s_addCarryM$(OBJ) \
+  s_addCarryM$(OBJ) \
-  s_addComplCarryM$(OBJ) \
+  s_addComplCarryM$(OBJ) \
-  s_negXM$(OBJ) \
+  s_negXM$(OBJ) \
-  s_sub1XM$(OBJ) \
+  s_sub1XM$(OBJ) \
-  s_subM$(OBJ) \
+  s_subM$(OBJ) \
-  s_mul64To128M$(OBJ) \
+  s_mul64To128M$(OBJ) \
-  s_mul128MTo256M$(OBJ) \
+  s_mul128MTo256M$(OBJ) \
-  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
-  s_approxRecip32_1$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
-  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
-  s_approxRecipSqrt32_1$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
-  s_remStepMBy32$(OBJ) \
+  s_remStepMBy32$(OBJ) \
-
+
-OBJS_SPECIALIZE = \
+OBJS_SPECIALIZE = \
-  softfloat_raiseFlags$(OBJ) \
+  softfloat_raiseFlags$(OBJ) \
-  s_f16UIToCommonNaN$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
-  s_commonNaNToF16UI$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
-  s_propagateNaNF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
-  s_f32UIToCommonNaN$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
-  s_commonNaNToF32UI$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
-  s_propagateNaNF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
-  s_f64UIToCommonNaN$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
-  s_commonNaNToF64UI$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
-  s_propagateNaNF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
-  extF80M_isSignalingNaN$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
-  s_extF80MToCommonNaN$(OBJ) \
+  s_extF80MToCommonNaN$(OBJ) \
-  s_commonNaNToExtF80M$(OBJ) \
+  s_commonNaNToExtF80M$(OBJ) \
-  s_propagateNaNExtF80M$(OBJ) \
+  s_propagateNaNExtF80M$(OBJ) \
-  f128M_isSignalingNaN$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
-  s_f128MToCommonNaN$(OBJ) \
+  s_f128MToCommonNaN$(OBJ) \
-  s_commonNaNToF128M$(OBJ) \
+  s_commonNaNToF128M$(OBJ) \
-  s_propagateNaNF128M$(OBJ) \
+  s_propagateNaNF128M$(OBJ) \
-
+
-OBJS_OTHERS = \
+OBJS_OTHERS = \
-  s_roundToUI32$(OBJ) \
+  s_roundToUI32$(OBJ) \
-  s_roundMToUI64$(OBJ) \
+  s_roundMToUI64$(OBJ) \
-  s_roundToI32$(OBJ) \
+  s_roundToI32$(OBJ) \
-  s_roundMToI64$(OBJ) \
+  s_roundMToI64$(OBJ) \
-  s_normSubnormalF16Sig$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
-  s_roundPackToF16$(OBJ) \
+  s_roundPackToF16$(OBJ) \
-  s_normRoundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
-  s_addMagsF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
-  s_subMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
-  s_mulAddF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
-  s_normSubnormalF32Sig$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
-  s_roundPackToF32$(OBJ) \
+  s_roundPackToF32$(OBJ) \
-  s_normRoundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
-  s_addMagsF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
-  s_subMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
-  s_mulAddF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
-  s_normSubnormalF64Sig$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
-  s_roundPackToF64$(OBJ) \
+  s_roundPackToF64$(OBJ) \
-  s_normRoundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
-  s_addMagsF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
-  s_subMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
-  s_mulAddF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
-  s_tryPropagateNaNExtF80M$(OBJ) \
+  s_tryPropagateNaNExtF80M$(OBJ) \
-  s_invalidExtF80M$(OBJ) \
+  s_invalidExtF80M$(OBJ) \
-  s_normExtF80SigM$(OBJ) \
+  s_normExtF80SigM$(OBJ) \
-  s_roundPackMToExtF80M$(OBJ) \
+  s_roundPackMToExtF80M$(OBJ) \
-  s_normRoundPackMToExtF80M$(OBJ) \
+  s_normRoundPackMToExtF80M$(OBJ) \
-  s_addExtF80M$(OBJ) \
+  s_addExtF80M$(OBJ) \
-  s_compareNonnormExtF80M$(OBJ) \
+  s_compareNonnormExtF80M$(OBJ) \
-  s_isNaNF128M$(OBJ) \
+  s_isNaNF128M$(OBJ) \
-  s_tryPropagateNaNF128M$(OBJ) \
+  s_tryPropagateNaNF128M$(OBJ) \
-  s_invalidF128M$(OBJ) \
+  s_invalidF128M$(OBJ) \
-  s_shiftNormSigF128M$(OBJ) \
+  s_shiftNormSigF128M$(OBJ) \
-  s_roundPackMToF128M$(OBJ) \
+  s_roundPackMToF128M$(OBJ) \
-  s_normRoundPackMToF128M$(OBJ) \
+  s_normRoundPackMToF128M$(OBJ) \
-  s_addF128M$(OBJ) \
+  s_addF128M$(OBJ) \
-  s_mulAddF128M$(OBJ) \
+  s_mulAddF128M$(OBJ) \
-  softfloat_state$(OBJ) \
+  softfloat_state$(OBJ) \
-  ui32_to_f16$(OBJ) \
+  ui32_to_f16$(OBJ) \
-  ui32_to_f32$(OBJ) \
+  ui32_to_f32$(OBJ) \
-  ui32_to_f64$(OBJ) \
+  ui32_to_f64$(OBJ) \
-  ui32_to_extF80M$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
-  ui32_to_f128M$(OBJ) \
+  ui32_to_f128M$(OBJ) \
-  ui64_to_f16$(OBJ) \
+  ui64_to_f16$(OBJ) \
-  ui64_to_f32$(OBJ) \
+  ui64_to_f32$(OBJ) \
-  ui64_to_f64$(OBJ) \
+  ui64_to_f64$(OBJ) \
-  ui64_to_extF80M$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
-  ui64_to_f128M$(OBJ) \
+  ui64_to_f128M$(OBJ) \
-  i32_to_f16$(OBJ) \
+  i32_to_f16$(OBJ) \
-  i32_to_f32$(OBJ) \
+  i32_to_f32$(OBJ) \
-  i32_to_f64$(OBJ) \
+  i32_to_f64$(OBJ) \
-  i32_to_extF80M$(OBJ) \
+  i32_to_extF80M$(OBJ) \
-  i32_to_f128M$(OBJ) \
+  i32_to_f128M$(OBJ) \
-  i64_to_f16$(OBJ) \
+  i64_to_f16$(OBJ) \
-  i64_to_f32$(OBJ) \
+  i64_to_f32$(OBJ) \
-  i64_to_f64$(OBJ) \
+  i64_to_f64$(OBJ) \
-  i64_to_extF80M$(OBJ) \
+  i64_to_extF80M$(OBJ) \
-  i64_to_f128M$(OBJ) \
+  i64_to_f128M$(OBJ) \
-  f16_to_ui32$(OBJ) \
+  f16_to_ui32$(OBJ) \
-  f16_to_ui64$(OBJ) \
+  f16_to_ui64$(OBJ) \
-  f16_to_i32$(OBJ) \
+  f16_to_i32$(OBJ) \
-  f16_to_i64$(OBJ) \
+  f16_to_i64$(OBJ) \
-  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
-  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
-  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
-  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
-  f16_to_f32$(OBJ) \
+  f16_to_f32$(OBJ) \
-  f16_to_f64$(OBJ) \
+  f16_to_f64$(OBJ) \
-  f16_to_extF80M$(OBJ) \
+  f16_to_extF80M$(OBJ) \
-  f16_to_f128M$(OBJ) \
+  f16_to_f128M$(OBJ) \
-  f16_roundToInt$(OBJ) \
+  f16_roundToInt$(OBJ) \
-  f16_add$(OBJ) \
+  f16_add$(OBJ) \
-  f16_sub$(OBJ) \
+  f16_sub$(OBJ) \
-  f16_mul$(OBJ) \
+  f16_mul$(OBJ) \
-  f16_mulAdd$(OBJ) \
+  f16_mulAdd$(OBJ) \
-  f16_div$(OBJ) \
+  f16_div$(OBJ) \
-  f16_rem$(OBJ) \
+  f16_rem$(OBJ) \
-  f16_sqrt$(OBJ) \
+  f16_sqrt$(OBJ) \
-  f16_eq$(OBJ) \
+  f16_eq$(OBJ) \
-  f16_le$(OBJ) \
+  f16_le$(OBJ) \
-  f16_lt$(OBJ) \
+  f16_lt$(OBJ) \
-  f16_eq_signaling$(OBJ) \
+  f16_eq_signaling$(OBJ) \
-  f16_le_quiet$(OBJ) \
+  f16_le_quiet$(OBJ) \
-  f16_lt_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
-  f16_isSignalingNaN$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
-  f32_to_ui32$(OBJ) \
+  f32_to_ui32$(OBJ) \
-  f32_to_ui64$(OBJ) \
+  f32_to_ui64$(OBJ) \
-  f32_to_i32$(OBJ) \
+  f32_to_i32$(OBJ) \
-  f32_to_i64$(OBJ) \
+  f32_to_i64$(OBJ) \
-  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
-  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
-  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
-  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
-  f32_to_f16$(OBJ) \
+  f32_to_f16$(OBJ) \
-  f32_to_f64$(OBJ) \
+  f32_to_f64$(OBJ) \
-  f32_to_extF80M$(OBJ) \
+  f32_to_extF80M$(OBJ) \
-  f32_to_f128M$(OBJ) \
+  f32_to_f128M$(OBJ) \
-  f32_roundToInt$(OBJ) \
+  f32_roundToInt$(OBJ) \
-  f32_add$(OBJ) \
+  f32_add$(OBJ) \
-  f32_sub$(OBJ) \
+  f32_sub$(OBJ) \
-  f32_mul$(OBJ) \
+  f32_mul$(OBJ) \
-  f32_mulAdd$(OBJ) \
+  f32_mulAdd$(OBJ) \
-  f32_div$(OBJ) \
+  f32_div$(OBJ) \
-  f32_rem$(OBJ) \
+  f32_rem$(OBJ) \
-  f32_sqrt$(OBJ) \
+  f32_sqrt$(OBJ) \
-  f32_eq$(OBJ) \
+  f32_eq$(OBJ) \
-  f32_le$(OBJ) \
+  f32_le$(OBJ) \
-  f32_lt$(OBJ) \
+  f32_lt$(OBJ) \
-  f32_eq_signaling$(OBJ) \
+  f32_eq_signaling$(OBJ) \
-  f32_le_quiet$(OBJ) \
+  f32_le_quiet$(OBJ) \
-  f32_lt_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
-  f32_isSignalingNaN$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
-  f64_to_ui32$(OBJ) \
+  f64_to_ui32$(OBJ) \
-  f64_to_ui64$(OBJ) \
+  f64_to_ui64$(OBJ) \
-  f64_to_i32$(OBJ) \
+  f64_to_i32$(OBJ) \
-  f64_to_i64$(OBJ) \
+  f64_to_i64$(OBJ) \
-  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
-  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
-  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
-  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
-  f64_to_f16$(OBJ) \
+  f64_to_f16$(OBJ) \
-  f64_to_f32$(OBJ) \
+  f64_to_f32$(OBJ) \
-  f64_to_extF80M$(OBJ) \
+  f64_to_extF80M$(OBJ) \
-  f64_to_f128M$(OBJ) \
+  f64_to_f128M$(OBJ) \
-  f64_roundToInt$(OBJ) \
+  f64_roundToInt$(OBJ) \
-  f64_add$(OBJ) \
+  f64_add$(OBJ) \
-  f64_sub$(OBJ) \
+  f64_sub$(OBJ) \
-  f64_mul$(OBJ) \
+  f64_mul$(OBJ) \
-  f64_mulAdd$(OBJ) \
+  f64_mulAdd$(OBJ) \
-  f64_div$(OBJ) \
+  f64_div$(OBJ) \
-  f64_rem$(OBJ) \
+  f64_rem$(OBJ) \
-  f64_sqrt$(OBJ) \
+  f64_sqrt$(OBJ) \
-  f64_eq$(OBJ) \
+  f64_eq$(OBJ) \
-  f64_le$(OBJ) \
+  f64_le$(OBJ) \
-  f64_lt$(OBJ) \
+  f64_lt$(OBJ) \
-  f64_eq_signaling$(OBJ) \
+  f64_eq_signaling$(OBJ) \
-  f64_le_quiet$(OBJ) \
+  f64_le_quiet$(OBJ) \
-  f64_lt_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
-  f64_isSignalingNaN$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
-  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
-  extF80M_to_ui64$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
-  extF80M_to_i32$(OBJ) \
+  extF80M_to_i32$(OBJ) \
-  extF80M_to_i64$(OBJ) \
+  extF80M_to_i64$(OBJ) \
-  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
-  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
-  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
-  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
-  extF80M_to_f16$(OBJ) \
+  extF80M_to_f16$(OBJ) \
-  extF80M_to_f32$(OBJ) \
+  extF80M_to_f32$(OBJ) \
-  extF80M_to_f64$(OBJ) \
+  extF80M_to_f64$(OBJ) \
-  extF80M_to_f128M$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
-  extF80M_roundToInt$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
-  extF80M_add$(OBJ) \
+  extF80M_add$(OBJ) \
-  extF80M_sub$(OBJ) \
+  extF80M_sub$(OBJ) \
-  extF80M_mul$(OBJ) \
+  extF80M_mul$(OBJ) \
-  extF80M_div$(OBJ) \
+  extF80M_div$(OBJ) \
-  extF80M_rem$(OBJ) \
+  extF80M_rem$(OBJ) \
-  extF80M_sqrt$(OBJ) \
+  extF80M_sqrt$(OBJ) \
-  extF80M_eq$(OBJ) \
+  extF80M_eq$(OBJ) \
-  extF80M_le$(OBJ) \
+  extF80M_le$(OBJ) \
-  extF80M_lt$(OBJ) \
+  extF80M_lt$(OBJ) \
-  extF80M_eq_signaling$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
-  extF80M_le_quiet$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
-  extF80M_lt_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
-  f128M_to_ui32$(OBJ) \
+  f128M_to_ui32$(OBJ) \
-  f128M_to_ui64$(OBJ) \
+  f128M_to_ui64$(OBJ) \
-  f128M_to_i32$(OBJ) \
+  f128M_to_i32$(OBJ) \
-  f128M_to_i64$(OBJ) \
+  f128M_to_i64$(OBJ) \
-  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
-  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
-  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
-  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
-  f128M_to_f16$(OBJ) \
+  f128M_to_f16$(OBJ) \
-  f128M_to_f32$(OBJ) \
+  f128M_to_f32$(OBJ) \
-  f128M_to_f64$(OBJ) \
+  f128M_to_f64$(OBJ) \
-  f128M_to_extF80M$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
-  f128M_roundToInt$(OBJ) \
+  f128M_roundToInt$(OBJ) \
-  f128M_add$(OBJ) \
+  f128M_add$(OBJ) \
-  f128M_sub$(OBJ) \
+  f128M_sub$(OBJ) \
-  f128M_mul$(OBJ) \
+  f128M_mul$(OBJ) \
-  f128M_mulAdd$(OBJ) \
+  f128M_mulAdd$(OBJ) \
-  f128M_div$(OBJ) \
+  f128M_div$(OBJ) \
-  f128M_rem$(OBJ) \
+  f128M_rem$(OBJ) \
-  f128M_sqrt$(OBJ) \
+  f128M_sqrt$(OBJ) \
-  f128M_eq$(OBJ) \
+  f128M_eq$(OBJ) \
-  f128M_le$(OBJ) \
+  f128M_le$(OBJ) \
-  f128M_lt$(OBJ) \
+  f128M_lt$(OBJ) \
-  f128M_eq_signaling$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
-  f128M_le_quiet$(OBJ) \
+  f128M_le_quiet$(OBJ) \
-  f128M_lt_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
-
+
-OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
-
+
-$(OBJS_ALL): \
+$(OBJS_ALL): \
-  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
-  $(SOURCE_DIR)/include/primitives.h
+  $(SOURCE_DIR)/include/primitives.h
-$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
-  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
-  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
-  $(SOURCE_DIR)/include/softfloat.h
+  $(SOURCE_DIR)/include/softfloat.h
-
+
-$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
-
+
-$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
-
+
-softfloat$(LIB): $(OBJS_ALL)
+softfloat$(LIB): $(OBJS_ALL)
-	$(DELETE) $@
+	$(DELETE) $@
-	$(MAKELIB) $^
+	$(MAKELIB) $^
-
+
-.PHONY: clean
+.PHONY: clean
-clean:
+clean:
-	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
-
+

softfloat/build/Win32-SSE2-MinGW/platform.h

@@ -1,53 +1,53 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-University of California.  All rights reserved.
+University of California.  All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#define LITTLEENDIAN 1
+#define LITTLEENDIAN 1
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#ifdef __GNUC_STDC_INLINE__
+#ifdef __GNUC_STDC_INLINE__
-#define INLINE inline
+#define INLINE inline
-#else
+#else
-#define INLINE extern inline
+#define INLINE extern inline
-#endif
+#endif
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#define SOFTFLOAT_BUILTIN_CLZ 1
+#define SOFTFLOAT_BUILTIN_CLZ 1
-#include "opts-GCC.h"
+#include "opts-GCC.h"
-
+

softfloat/build/Win64-MinGW-w64/Makefile

@@ -1,390 +1,390 @@
-
+
-#=============================================================================
+#=============================================================================
-#
+#
-# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
-# Package, Release 3e, by John R. Hauser.
+# Package, Release 3e, by John R. Hauser.
-#
+#
-# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-# University of California.  All rights reserved.
+# University of California.  All rights reserved.
-#
+#
-# Redistribution and use in source and binary forms, with or without
+# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
+# modification, are permitted provided that the following conditions are met:
-#
+#
-#  1. Redistributions of source code must retain the above copyright notice,
+#  1. Redistributions of source code must retain the above copyright notice,
-#     this list of conditions, and the following disclaimer.
+#     this list of conditions, and the following disclaimer.
-#
+#
-#  2. Redistributions in binary form must reproduce the above copyright
+#  2. Redistributions in binary form must reproduce the above copyright
-#     notice, this list of conditions, and the following disclaimer in the
+#     notice, this list of conditions, and the following disclaimer in the
-#     documentation and/or other materials provided with the distribution.
+#     documentation and/or other materials provided with the distribution.
-#
+#
-#  3. Neither the name of the University nor the names of its contributors
+#  3. Neither the name of the University nor the names of its contributors
-#     may be used to endorse or promote products derived from this software
+#     may be used to endorse or promote products derived from this software
-#     without specific prior written permission.
+#     without specific prior written permission.
-#
+#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
+#
-#=============================================================================
+#=============================================================================
-
+
-SOURCE_DIR ?= ../../source
+SOURCE_DIR ?= ../../source
-SPECIALIZE_TYPE ?= 8086-SSE
+SPECIALIZE_TYPE ?= 8086-SSE
-
+
-SOFTFLOAT_OPTS ?= \
+SOFTFLOAT_OPTS ?= \
-  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-  -DSOFTFLOAT_FAST_DIV64TO32
+  -DSOFTFLOAT_FAST_DIV64TO32
-
+
-DELETE = rm -f
+DELETE = rm -f
-C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
-COMPILE_C = \
+COMPILE_C = \
-  x86_64-w64-mingw32-gcc -c -Werror-implicit-function-declaration \
+  x86_64-w64-mingw32-gcc -c -Werror-implicit-function-declaration \
-    -DSOFTFLOAT_FAST_INT64 $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
+    -DSOFTFLOAT_FAST_INT64 $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
-MAKELIB = x86_64-w64-mingw32-ar crs $@
+MAKELIB = x86_64-w64-mingw32-ar crs $@
-
+
-OBJ = .o
+OBJ = .o
-LIB = .a
+LIB = .a
-
+
-OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h
+OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h
-
+
-.PHONY: all
+.PHONY: all
-all: softfloat$(LIB)
+all: softfloat$(LIB)
-
+
-OBJS_PRIMITIVES = \
+OBJS_PRIMITIVES = \
-  s_eq128$(OBJ) \
+  s_eq128$(OBJ) \
-  s_le128$(OBJ) \
+  s_le128$(OBJ) \
-  s_lt128$(OBJ) \
+  s_lt128$(OBJ) \
-  s_shortShiftLeft128$(OBJ) \
+  s_shortShiftLeft128$(OBJ) \
-  s_shortShiftRight128$(OBJ) \
+  s_shortShiftRight128$(OBJ) \
-  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
-  s_shortShiftRightJam64Extra$(OBJ) \
+  s_shortShiftRightJam64Extra$(OBJ) \
-  s_shortShiftRightJam128$(OBJ) \
+  s_shortShiftRightJam128$(OBJ) \
-  s_shortShiftRightJam128Extra$(OBJ) \
+  s_shortShiftRightJam128Extra$(OBJ) \
-  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
-  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
-  s_shiftRightJam64Extra$(OBJ) \
+  s_shiftRightJam64Extra$(OBJ) \
-  s_shiftRightJam128$(OBJ) \
+  s_shiftRightJam128$(OBJ) \
-  s_shiftRightJam128Extra$(OBJ) \
+  s_shiftRightJam128Extra$(OBJ) \
-  s_shiftRightJam256M$(OBJ) \
+  s_shiftRightJam256M$(OBJ) \
-  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
-  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
-  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
-  s_countLeadingZeros64$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
-  s_add128$(OBJ) \
+  s_add128$(OBJ) \
-  s_add256M$(OBJ) \
+  s_add256M$(OBJ) \
-  s_sub128$(OBJ) \
+  s_sub128$(OBJ) \
-  s_sub256M$(OBJ) \
+  s_sub256M$(OBJ) \
-  s_mul64ByShifted32To128$(OBJ) \
+  s_mul64ByShifted32To128$(OBJ) \
-  s_mul64To128$(OBJ) \
+  s_mul64To128$(OBJ) \
-  s_mul128By32$(OBJ) \
+  s_mul128By32$(OBJ) \
-  s_mul128To256M$(OBJ) \
+  s_mul128To256M$(OBJ) \
-  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
-  s_approxRecip32_1$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
-  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
-  s_approxRecipSqrt32_1$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
-
+
-OBJS_SPECIALIZE = \
+OBJS_SPECIALIZE = \
-  softfloat_raiseFlags$(OBJ) \
+  softfloat_raiseFlags$(OBJ) \
-  s_f16UIToCommonNaN$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
-  s_commonNaNToF16UI$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
-  s_propagateNaNF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
-  s_f32UIToCommonNaN$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
-  s_commonNaNToF32UI$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
-  s_propagateNaNF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
-  s_f64UIToCommonNaN$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
-  s_commonNaNToF64UI$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
-  s_propagateNaNF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
-  extF80M_isSignalingNaN$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
-  s_extF80UIToCommonNaN$(OBJ) \
+  s_extF80UIToCommonNaN$(OBJ) \
-  s_commonNaNToExtF80UI$(OBJ) \
+  s_commonNaNToExtF80UI$(OBJ) \
-  s_propagateNaNExtF80UI$(OBJ) \
+  s_propagateNaNExtF80UI$(OBJ) \
-  f128M_isSignalingNaN$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
-  s_f128UIToCommonNaN$(OBJ) \
+  s_f128UIToCommonNaN$(OBJ) \
-  s_commonNaNToF128UI$(OBJ) \
+  s_commonNaNToF128UI$(OBJ) \
-  s_propagateNaNF128UI$(OBJ) \
+  s_propagateNaNF128UI$(OBJ) \
-
+
-OBJS_OTHERS = \
+OBJS_OTHERS = \
-  s_roundToUI32$(OBJ) \
+  s_roundToUI32$(OBJ) \
-  s_roundToUI64$(OBJ) \
+  s_roundToUI64$(OBJ) \
-  s_roundToI32$(OBJ) \
+  s_roundToI32$(OBJ) \
-  s_roundToI64$(OBJ) \
+  s_roundToI64$(OBJ) \
-  s_normSubnormalF16Sig$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
-  s_roundPackToF16$(OBJ) \
+  s_roundPackToF16$(OBJ) \
-  s_normRoundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
-  s_addMagsF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
-  s_subMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
-  s_mulAddF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
-  s_normSubnormalF32Sig$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
-  s_roundPackToF32$(OBJ) \
+  s_roundPackToF32$(OBJ) \
-  s_normRoundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
-  s_addMagsF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
-  s_subMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
-  s_mulAddF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
-  s_normSubnormalF64Sig$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
-  s_roundPackToF64$(OBJ) \
+  s_roundPackToF64$(OBJ) \
-  s_normRoundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
-  s_addMagsF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
-  s_subMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
-  s_mulAddF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
-  s_normSubnormalExtF80Sig$(OBJ) \
+  s_normSubnormalExtF80Sig$(OBJ) \
-  s_roundPackToExtF80$(OBJ) \
+  s_roundPackToExtF80$(OBJ) \
-  s_normRoundPackToExtF80$(OBJ) \
+  s_normRoundPackToExtF80$(OBJ) \
-  s_addMagsExtF80$(OBJ) \
+  s_addMagsExtF80$(OBJ) \
-  s_subMagsExtF80$(OBJ) \
+  s_subMagsExtF80$(OBJ) \
-  s_normSubnormalF128Sig$(OBJ) \
+  s_normSubnormalF128Sig$(OBJ) \
-  s_roundPackToF128$(OBJ) \
+  s_roundPackToF128$(OBJ) \
-  s_normRoundPackToF128$(OBJ) \
+  s_normRoundPackToF128$(OBJ) \
-  s_addMagsF128$(OBJ) \
+  s_addMagsF128$(OBJ) \
-  s_subMagsF128$(OBJ) \
+  s_subMagsF128$(OBJ) \
-  s_mulAddF128$(OBJ) \
+  s_mulAddF128$(OBJ) \
-  softfloat_state$(OBJ) \
+  softfloat_state$(OBJ) \
-  ui32_to_f16$(OBJ) \
+  ui32_to_f16$(OBJ) \
-  ui32_to_f32$(OBJ) \
+  ui32_to_f32$(OBJ) \
-  ui32_to_f64$(OBJ) \
+  ui32_to_f64$(OBJ) \
-  ui32_to_extF80$(OBJ) \
+  ui32_to_extF80$(OBJ) \
-  ui32_to_extF80M$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
-  ui32_to_f128$(OBJ) \
+  ui32_to_f128$(OBJ) \
-  ui32_to_f128M$(OBJ) \
+  ui32_to_f128M$(OBJ) \
-  ui64_to_f16$(OBJ) \
+  ui64_to_f16$(OBJ) \
-  ui64_to_f32$(OBJ) \
+  ui64_to_f32$(OBJ) \
-  ui64_to_f64$(OBJ) \
+  ui64_to_f64$(OBJ) \
-  ui64_to_extF80$(OBJ) \
+  ui64_to_extF80$(OBJ) \
-  ui64_to_extF80M$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
-  ui64_to_f128$(OBJ) \
+  ui64_to_f128$(OBJ) \
-  ui64_to_f128M$(OBJ) \
+  ui64_to_f128M$(OBJ) \
-  i32_to_f16$(OBJ) \
+  i32_to_f16$(OBJ) \
-  i32_to_f32$(OBJ) \
+  i32_to_f32$(OBJ) \
-  i32_to_f64$(OBJ) \
+  i32_to_f64$(OBJ) \
-  i32_to_extF80$(OBJ) \
+  i32_to_extF80$(OBJ) \
-  i32_to_extF80M$(OBJ) \
+  i32_to_extF80M$(OBJ) \
-  i32_to_f128$(OBJ) \
+  i32_to_f128$(OBJ) \
-  i32_to_f128M$(OBJ) \
+  i32_to_f128M$(OBJ) \
-  i64_to_f16$(OBJ) \
+  i64_to_f16$(OBJ) \
-  i64_to_f32$(OBJ) \
+  i64_to_f32$(OBJ) \
-  i64_to_f64$(OBJ) \
+  i64_to_f64$(OBJ) \
-  i64_to_extF80$(OBJ) \
+  i64_to_extF80$(OBJ) \
-  i64_to_extF80M$(OBJ) \
+  i64_to_extF80M$(OBJ) \
-  i64_to_f128$(OBJ) \
+  i64_to_f128$(OBJ) \
-  i64_to_f128M$(OBJ) \
+  i64_to_f128M$(OBJ) \
-  f16_to_ui32$(OBJ) \
+  f16_to_ui32$(OBJ) \
-  f16_to_ui64$(OBJ) \
+  f16_to_ui64$(OBJ) \
-  f16_to_i32$(OBJ) \
+  f16_to_i32$(OBJ) \
-  f16_to_i64$(OBJ) \
+  f16_to_i64$(OBJ) \
-  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
-  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
-  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
-  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
-  f16_to_f32$(OBJ) \
+  f16_to_f32$(OBJ) \
-  f16_to_f64$(OBJ) \
+  f16_to_f64$(OBJ) \
-  f16_to_extF80$(OBJ) \
+  f16_to_extF80$(OBJ) \
-  f16_to_extF80M$(OBJ) \
+  f16_to_extF80M$(OBJ) \
-  f16_to_f128$(OBJ) \
+  f16_to_f128$(OBJ) \
-  f16_to_f128M$(OBJ) \
+  f16_to_f128M$(OBJ) \
-  f16_roundToInt$(OBJ) \
+  f16_roundToInt$(OBJ) \
-  f16_add$(OBJ) \
+  f16_add$(OBJ) \
-  f16_sub$(OBJ) \
+  f16_sub$(OBJ) \
-  f16_mul$(OBJ) \
+  f16_mul$(OBJ) \
-  f16_mulAdd$(OBJ) \
+  f16_mulAdd$(OBJ) \
-  f16_div$(OBJ) \
+  f16_div$(OBJ) \
-  f16_rem$(OBJ) \
+  f16_rem$(OBJ) \
-  f16_sqrt$(OBJ) \
+  f16_sqrt$(OBJ) \
-  f16_eq$(OBJ) \
+  f16_eq$(OBJ) \
-  f16_le$(OBJ) \
+  f16_le$(OBJ) \
-  f16_lt$(OBJ) \
+  f16_lt$(OBJ) \
-  f16_eq_signaling$(OBJ) \
+  f16_eq_signaling$(OBJ) \
-  f16_le_quiet$(OBJ) \
+  f16_le_quiet$(OBJ) \
-  f16_lt_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
-  f16_isSignalingNaN$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
-  f32_to_ui32$(OBJ) \
+  f32_to_ui32$(OBJ) \
-  f32_to_ui64$(OBJ) \
+  f32_to_ui64$(OBJ) \
-  f32_to_i32$(OBJ) \
+  f32_to_i32$(OBJ) \
-  f32_to_i64$(OBJ) \
+  f32_to_i64$(OBJ) \
-  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
-  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
-  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
-  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
-  f32_to_f16$(OBJ) \
+  f32_to_f16$(OBJ) \
-  f32_to_f64$(OBJ) \
+  f32_to_f64$(OBJ) \
-  f32_to_extF80$(OBJ) \
+  f32_to_extF80$(OBJ) \
-  f32_to_extF80M$(OBJ) \
+  f32_to_extF80M$(OBJ) \
-  f32_to_f128$(OBJ) \
+  f32_to_f128$(OBJ) \
-  f32_to_f128M$(OBJ) \
+  f32_to_f128M$(OBJ) \
-  f32_roundToInt$(OBJ) \
+  f32_roundToInt$(OBJ) \
-  f32_add$(OBJ) \
+  f32_add$(OBJ) \
-  f32_sub$(OBJ) \
+  f32_sub$(OBJ) \
-  f32_mul$(OBJ) \
+  f32_mul$(OBJ) \
-  f32_mulAdd$(OBJ) \
+  f32_mulAdd$(OBJ) \
-  f32_div$(OBJ) \
+  f32_div$(OBJ) \
-  f32_rem$(OBJ) \
+  f32_rem$(OBJ) \
-  f32_sqrt$(OBJ) \
+  f32_sqrt$(OBJ) \
-  f32_eq$(OBJ) \
+  f32_eq$(OBJ) \
-  f32_le$(OBJ) \
+  f32_le$(OBJ) \
-  f32_lt$(OBJ) \
+  f32_lt$(OBJ) \
-  f32_eq_signaling$(OBJ) \
+  f32_eq_signaling$(OBJ) \
-  f32_le_quiet$(OBJ) \
+  f32_le_quiet$(OBJ) \
-  f32_lt_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
-  f32_isSignalingNaN$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
-  f64_to_ui32$(OBJ) \
+  f64_to_ui32$(OBJ) \
-  f64_to_ui64$(OBJ) \
+  f64_to_ui64$(OBJ) \
-  f64_to_i32$(OBJ) \
+  f64_to_i32$(OBJ) \
-  f64_to_i64$(OBJ) \
+  f64_to_i64$(OBJ) \
-  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
-  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
-  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
-  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
-  f64_to_f16$(OBJ) \
+  f64_to_f16$(OBJ) \
-  f64_to_f32$(OBJ) \
+  f64_to_f32$(OBJ) \
-  f64_to_extF80$(OBJ) \
+  f64_to_extF80$(OBJ) \
-  f64_to_extF80M$(OBJ) \
+  f64_to_extF80M$(OBJ) \
-  f64_to_f128$(OBJ) \
+  f64_to_f128$(OBJ) \
-  f64_to_f128M$(OBJ) \
+  f64_to_f128M$(OBJ) \
-  f64_roundToInt$(OBJ) \
+  f64_roundToInt$(OBJ) \
-  f64_add$(OBJ) \
+  f64_add$(OBJ) \
-  f64_sub$(OBJ) \
+  f64_sub$(OBJ) \
-  f64_mul$(OBJ) \
+  f64_mul$(OBJ) \
-  f64_mulAdd$(OBJ) \
+  f64_mulAdd$(OBJ) \
-  f64_div$(OBJ) \
+  f64_div$(OBJ) \
-  f64_rem$(OBJ) \
+  f64_rem$(OBJ) \
-  f64_sqrt$(OBJ) \
+  f64_sqrt$(OBJ) \
-  f64_eq$(OBJ) \
+  f64_eq$(OBJ) \
-  f64_le$(OBJ) \
+  f64_le$(OBJ) \
-  f64_lt$(OBJ) \
+  f64_lt$(OBJ) \
-  f64_eq_signaling$(OBJ) \
+  f64_eq_signaling$(OBJ) \
-  f64_le_quiet$(OBJ) \
+  f64_le_quiet$(OBJ) \
-  f64_lt_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
-  f64_isSignalingNaN$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
-  extF80_to_ui32$(OBJ) \
+  extF80_to_ui32$(OBJ) \
-  extF80_to_ui64$(OBJ) \
+  extF80_to_ui64$(OBJ) \
-  extF80_to_i32$(OBJ) \
+  extF80_to_i32$(OBJ) \
-  extF80_to_i64$(OBJ) \
+  extF80_to_i64$(OBJ) \
-  extF80_to_ui32_r_minMag$(OBJ) \
+  extF80_to_ui32_r_minMag$(OBJ) \
-  extF80_to_ui64_r_minMag$(OBJ) \
+  extF80_to_ui64_r_minMag$(OBJ) \
-  extF80_to_i32_r_minMag$(OBJ) \
+  extF80_to_i32_r_minMag$(OBJ) \
-  extF80_to_i64_r_minMag$(OBJ) \
+  extF80_to_i64_r_minMag$(OBJ) \
-  extF80_to_f16$(OBJ) \
+  extF80_to_f16$(OBJ) \
-  extF80_to_f32$(OBJ) \
+  extF80_to_f32$(OBJ) \
-  extF80_to_f64$(OBJ) \
+  extF80_to_f64$(OBJ) \
-  extF80_to_f128$(OBJ) \
+  extF80_to_f128$(OBJ) \
-  extF80_roundToInt$(OBJ) \
+  extF80_roundToInt$(OBJ) \
-  extF80_add$(OBJ) \
+  extF80_add$(OBJ) \
-  extF80_sub$(OBJ) \
+  extF80_sub$(OBJ) \
-  extF80_mul$(OBJ) \
+  extF80_mul$(OBJ) \
-  extF80_div$(OBJ) \
+  extF80_div$(OBJ) \
-  extF80_rem$(OBJ) \
+  extF80_rem$(OBJ) \
-  extF80_sqrt$(OBJ) \
+  extF80_sqrt$(OBJ) \
-  extF80_eq$(OBJ) \
+  extF80_eq$(OBJ) \
-  extF80_le$(OBJ) \
+  extF80_le$(OBJ) \
-  extF80_lt$(OBJ) \
+  extF80_lt$(OBJ) \
-  extF80_eq_signaling$(OBJ) \
+  extF80_eq_signaling$(OBJ) \
-  extF80_le_quiet$(OBJ) \
+  extF80_le_quiet$(OBJ) \
-  extF80_lt_quiet$(OBJ) \
+  extF80_lt_quiet$(OBJ) \
-  extF80_isSignalingNaN$(OBJ) \
+  extF80_isSignalingNaN$(OBJ) \
-  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
-  extF80M_to_ui64$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
-  extF80M_to_i32$(OBJ) \
+  extF80M_to_i32$(OBJ) \
-  extF80M_to_i64$(OBJ) \
+  extF80M_to_i64$(OBJ) \
-  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
-  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
-  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
-  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
-  extF80M_to_f16$(OBJ) \
+  extF80M_to_f16$(OBJ) \
-  extF80M_to_f32$(OBJ) \
+  extF80M_to_f32$(OBJ) \
-  extF80M_to_f64$(OBJ) \
+  extF80M_to_f64$(OBJ) \
-  extF80M_to_f128M$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
-  extF80M_roundToInt$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
-  extF80M_add$(OBJ) \
+  extF80M_add$(OBJ) \
-  extF80M_sub$(OBJ) \
+  extF80M_sub$(OBJ) \
-  extF80M_mul$(OBJ) \
+  extF80M_mul$(OBJ) \
-  extF80M_div$(OBJ) \
+  extF80M_div$(OBJ) \
-  extF80M_rem$(OBJ) \
+  extF80M_rem$(OBJ) \
-  extF80M_sqrt$(OBJ) \
+  extF80M_sqrt$(OBJ) \
-  extF80M_eq$(OBJ) \
+  extF80M_eq$(OBJ) \
-  extF80M_le$(OBJ) \
+  extF80M_le$(OBJ) \
-  extF80M_lt$(OBJ) \
+  extF80M_lt$(OBJ) \
-  extF80M_eq_signaling$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
-  extF80M_le_quiet$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
-  extF80M_lt_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
-  f128_to_ui32$(OBJ) \
+  f128_to_ui32$(OBJ) \
-  f128_to_ui64$(OBJ) \
+  f128_to_ui64$(OBJ) \
-  f128_to_i32$(OBJ) \
+  f128_to_i32$(OBJ) \
-  f128_to_i64$(OBJ) \
+  f128_to_i64$(OBJ) \
-  f128_to_ui32_r_minMag$(OBJ) \
+  f128_to_ui32_r_minMag$(OBJ) \
-  f128_to_ui64_r_minMag$(OBJ) \
+  f128_to_ui64_r_minMag$(OBJ) \
-  f128_to_i32_r_minMag$(OBJ) \
+  f128_to_i32_r_minMag$(OBJ) \
-  f128_to_i64_r_minMag$(OBJ) \
+  f128_to_i64_r_minMag$(OBJ) \
-  f128_to_f16$(OBJ) \
+  f128_to_f16$(OBJ) \
-  f128_to_f32$(OBJ) \
+  f128_to_f32$(OBJ) \
-  f128_to_extF80$(OBJ) \
+  f128_to_extF80$(OBJ) \
-  f128_to_f64$(OBJ) \
+  f128_to_f64$(OBJ) \
-  f128_roundToInt$(OBJ) \
+  f128_roundToInt$(OBJ) \
-  f128_add$(OBJ) \
+  f128_add$(OBJ) \
-  f128_sub$(OBJ) \
+  f128_sub$(OBJ) \
-  f128_mul$(OBJ) \
+  f128_mul$(OBJ) \
-  f128_mulAdd$(OBJ) \
+  f128_mulAdd$(OBJ) \
-  f128_div$(OBJ) \
+  f128_div$(OBJ) \
-  f128_rem$(OBJ) \
+  f128_rem$(OBJ) \
-  f128_sqrt$(OBJ) \
+  f128_sqrt$(OBJ) \
-  f128_eq$(OBJ) \
+  f128_eq$(OBJ) \
-  f128_le$(OBJ) \
+  f128_le$(OBJ) \
-  f128_lt$(OBJ) \
+  f128_lt$(OBJ) \
-  f128_eq_signaling$(OBJ) \
+  f128_eq_signaling$(OBJ) \
-  f128_le_quiet$(OBJ) \
+  f128_le_quiet$(OBJ) \
-  f128_lt_quiet$(OBJ) \
+  f128_lt_quiet$(OBJ) \
-  f128_isSignalingNaN$(OBJ) \
+  f128_isSignalingNaN$(OBJ) \
-  f128M_to_ui32$(OBJ) \
+  f128M_to_ui32$(OBJ) \
-  f128M_to_ui64$(OBJ) \
+  f128M_to_ui64$(OBJ) \
-  f128M_to_i32$(OBJ) \
+  f128M_to_i32$(OBJ) \
-  f128M_to_i64$(OBJ) \
+  f128M_to_i64$(OBJ) \
-  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
-  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
-  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
-  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
-  f128M_to_f16$(OBJ) \
+  f128M_to_f16$(OBJ) \
-  f128M_to_f32$(OBJ) \
+  f128M_to_f32$(OBJ) \
-  f128M_to_extF80M$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
-  f128M_to_f64$(OBJ) \
+  f128M_to_f64$(OBJ) \
-  f128M_roundToInt$(OBJ) \
+  f128M_roundToInt$(OBJ) \
-  f128M_add$(OBJ) \
+  f128M_add$(OBJ) \
-  f128M_sub$(OBJ) \
+  f128M_sub$(OBJ) \
-  f128M_mul$(OBJ) \
+  f128M_mul$(OBJ) \
-  f128M_mulAdd$(OBJ) \
+  f128M_mulAdd$(OBJ) \
-  f128M_div$(OBJ) \
+  f128M_div$(OBJ) \
-  f128M_rem$(OBJ) \
+  f128M_rem$(OBJ) \
-  f128M_sqrt$(OBJ) \
+  f128M_sqrt$(OBJ) \
-  f128M_eq$(OBJ) \
+  f128M_eq$(OBJ) \
-  f128M_le$(OBJ) \
+  f128M_le$(OBJ) \
-  f128M_lt$(OBJ) \
+  f128M_lt$(OBJ) \
-  f128M_eq_signaling$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
-  f128M_le_quiet$(OBJ) \
+  f128M_le_quiet$(OBJ) \
-  f128M_lt_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
-
+
-OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
-
+
-$(OBJS_ALL): \
+$(OBJS_ALL): \
-  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
-  $(SOURCE_DIR)/include/primitives.h
+  $(SOURCE_DIR)/include/primitives.h
-$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
-  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
-  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
-  $(SOURCE_DIR)/include/softfloat.h
+  $(SOURCE_DIR)/include/softfloat.h
-
+
-$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
-
+
-$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
-
+
-softfloat$(LIB): $(OBJS_ALL)
+softfloat$(LIB): $(OBJS_ALL)
-	$(DELETE) $@
+	$(DELETE) $@
-	$(MAKELIB) $^
+	$(MAKELIB) $^
-
+
-.PHONY: clean
+.PHONY: clean
-clean:
+clean:
-	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
-
+

softfloat/build/Win64-MinGW-w64/platform.h

@@ -1,54 +1,54 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-University of California.  All rights reserved.
+University of California.  All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#define LITTLEENDIAN 1
+#define LITTLEENDIAN 1
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#ifdef __GNUC_STDC_INLINE__
+#ifdef __GNUC_STDC_INLINE__
-#define INLINE inline
+#define INLINE inline
-#else
+#else
-#define INLINE extern inline
+#define INLINE extern inline
-#endif
+#endif
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-#define SOFTFLOAT_BUILTIN_CLZ 1
+#define SOFTFLOAT_BUILTIN_CLZ 1
-#define SOFTFLOAT_INTRINSIC_INT128 1
+#define SOFTFLOAT_INTRINSIC_INT128 1
-#include "opts-GCC.h"
+#include "opts-GCC.h"
-
+

softfloat/build/template-FAST_INT64/Makefile

@@ -1,396 +1,391 @@
-
+
-#=============================================================================
+#=============================================================================
-#
+#
-# This Makefile template is part of the SoftFloat IEEE Floating-Point
+# This Makefile template is part of the SoftFloat IEEE Floating-Point
-# Arithmetic Package, Release 3e, by John R. Hauser.
+# Arithmetic Package, Release 3e, by John R. Hauser.
-#
+#
-# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-# University of California.  All rights reserved.
+# University of California.  All rights reserved.
-#
+#
-# Redistribution and use in source and binary forms, with or without
+# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
+# modification, are permitted provided that the following conditions are met:
-#
+#
-#  1. Redistributions of source code must retain the above copyright notice,
+#  1. Redistributions of source code must retain the above copyright notice,
-#     this list of conditions, and the following disclaimer.
+#     this list of conditions, and the following disclaimer.
-#
+#
-#  2. Redistributions in binary form must reproduce the above copyright
+#  2. Redistributions in binary form must reproduce the above copyright
-#     notice, this list of conditions, and the following disclaimer in the
+#     notice, this list of conditions, and the following disclaimer in the
-#     documentation and/or other materials provided with the distribution.
+#     documentation and/or other materials provided with the distribution.
-#
+#
-#  3. Neither the name of the University nor the names of its contributors
+#  3. Neither the name of the University nor the names of its contributors
-#     may be used to endorse or promote products derived from this software
+#     may be used to endorse or promote products derived from this software
-#     without specific prior written permission.
+#     without specific prior written permission.
-#
+#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
+#
-#=============================================================================
+#=============================================================================
-
+
-# Edit lines marked with `==>'.  See "SoftFloat-source.html".
+# Edit lines marked with `==>'.  See "SoftFloat-source.html".
-
+
-==> SOURCE_DIR ?= ../../source
+==> SOURCE_DIR ?= ../../source
-==> SPECIALIZE_TYPE ?= 8086
+==> SPECIALIZE_TYPE ?= 8086
-
+
-==> SOFTFLOAT_OPTS ?= \
+==> SOFTFLOAT_OPTS ?= \
-==>   -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+==>   -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-==>   -DSOFTFLOAT_FAST_DIV64TO32
+==>   -DSOFTFLOAT_FAST_DIV64TO32
-
+
-==> DELETE = rm -f
+==> DELETE = rm -f
-==> C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+==> C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
-==> COMPILE_C = \
+==> COMPILE_C = \
-==>   cc -c -DSOFTFLOAT_FAST_INT64 $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
+==>   cc -c -DSOFTFLOAT_FAST_INT64 $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
-==> MAKELIB = ar crs $@
+==> MAKELIB = ar crs $@
-
+
-==> OBJ = .o
+==> OBJ = .o
-==> LIB = .a
+==> LIB = .a
-
+
-==> OTHER_HEADERS =
+==> OTHER_HEADERS =
-
+
-.PHONY: all
+.PHONY: all
-all: softfloat$(LIB)
+all: softfloat$(LIB)
-
+
-OBJS_PRIMITIVES = \
+OBJS_PRIMITIVES = \
-  s_eq128$(OBJ) \
+  s_eq128$(OBJ) \
-  s_le128$(OBJ) \
+  s_le128$(OBJ) \
-  s_lt128$(OBJ) \
+  s_lt128$(OBJ) \
-  s_shortShiftLeft128$(OBJ) \
+  s_shortShiftLeft128$(OBJ) \
-  s_shortShiftRight128$(OBJ) \
+  s_shortShiftRight128$(OBJ) \
-  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
-  s_shortShiftRightJam64Extra$(OBJ) \
+  s_shortShiftRightJam64Extra$(OBJ) \
-  s_shortShiftRightJam128$(OBJ) \
+  s_shortShiftRightJam128$(OBJ) \
-  s_shortShiftRightJam128Extra$(OBJ) \
+  s_shortShiftRightJam128Extra$(OBJ) \
-  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
-  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
-  s_shiftRightJam64Extra$(OBJ) \
+  s_shiftRightJam64Extra$(OBJ) \
-  s_shiftRightJam128$(OBJ) \
+  s_shiftRightJam128$(OBJ) \
-  s_shiftRightJam128Extra$(OBJ) \
+  s_shiftRightJam128Extra$(OBJ) \
-  s_shiftRightJam256M$(OBJ) \
+  s_shiftRightJam256M$(OBJ) \
-  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
-  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
-  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
-  s_countLeadingZeros64$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
-  s_add128$(OBJ) \
+  s_add128$(OBJ) \
-  s_add256M$(OBJ) \
+  s_add256M$(OBJ) \
-  s_sub128$(OBJ) \
+  s_sub128$(OBJ) \
-  s_sub256M$(OBJ) \
+  s_sub256M$(OBJ) \
-  s_mul64ByShifted32To128$(OBJ) \
+  s_mul64ByShifted32To128$(OBJ) \
-  s_mul64To128$(OBJ) \
+  s_mul64To128$(OBJ) \
-  s_mul128By32$(OBJ) \
+  s_mul128By32$(OBJ) \
-  s_mul128To256M$(OBJ) \
+  s_mul128To256M$(OBJ) \
-  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
-  s_approxRecip32_1$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
-  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
-  s_approxRecipSqrt32_1$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
-
+
-OBJS_SPECIALIZE = \
+OBJS_SPECIALIZE = \
-  softfloat_raiseFlags$(OBJ) \
+  softfloat_raiseFlags$(OBJ) \
-  s_f16UIToCommonNaN$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
-  s_commonNaNToF16UI$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
-  s_propagateNaNF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
-  s_f32UIToCommonNaN$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
-  s_commonNaNToF32UI$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
-  s_propagateNaNF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
-  s_f64UIToCommonNaN$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
-  s_commonNaNToF64UI$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
-  s_propagateNaNF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
-  extF80M_isSignalingNaN$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
-  s_extF80UIToCommonNaN$(OBJ) \
+  s_extF80UIToCommonNaN$(OBJ) \
-  s_commonNaNToExtF80UI$(OBJ) \
+  s_commonNaNToExtF80UI$(OBJ) \
-  s_propagateNaNExtF80UI$(OBJ) \
+  s_propagateNaNExtF80UI$(OBJ) \
-  f128M_isSignalingNaN$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
-  s_f128UIToCommonNaN$(OBJ) \
+  s_f128UIToCommonNaN$(OBJ) \
-  s_commonNaNToF128UI$(OBJ) \
+  s_commonNaNToF128UI$(OBJ) \
-  s_propagateNaNF128UI$(OBJ) \
+  s_propagateNaNF128UI$(OBJ) \
-
+
-OBJS_OTHERS = \
+OBJS_OTHERS = \
-  s_roundToUI32$(OBJ) \
+  s_roundToUI32$(OBJ) \
-  s_roundToUI64$(OBJ) \
+  s_roundToUI64$(OBJ) \
-  s_roundToI32$(OBJ) \
+  s_roundToI32$(OBJ) \
-  s_roundToI64$(OBJ) \
+  s_roundToI64$(OBJ) \
-  s_normSubnormalBF16Sig$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
-  s_roundPackToBF16$(OBJ) \
+  s_roundPackToF16$(OBJ) \
-  s_normSubnormalF16Sig$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
-  s_roundPackToF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
-  s_normRoundPackToF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
-  s_addMagsF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
-  s_subMagsF16$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
-  s_mulAddF16$(OBJ) \
+  s_roundPackToF32$(OBJ) \
-  s_normSubnormalF32Sig$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
-  s_roundPackToF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
-  s_normRoundPackToF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
-  s_addMagsF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
-  s_subMagsF32$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
-  s_mulAddF32$(OBJ) \
+  s_roundPackToF64$(OBJ) \
-  s_normSubnormalF64Sig$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
-  s_roundPackToF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
-  s_normRoundPackToF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
-  s_addMagsF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
-  s_subMagsF64$(OBJ) \
+  s_normSubnormalExtF80Sig$(OBJ) \
-  s_mulAddF64$(OBJ) \
+  s_roundPackToExtF80$(OBJ) \
-  s_normSubnormalExtF80Sig$(OBJ) \
+  s_normRoundPackToExtF80$(OBJ) \
-  s_roundPackToExtF80$(OBJ) \
+  s_addMagsExtF80$(OBJ) \
-  s_normRoundPackToExtF80$(OBJ) \
+  s_subMagsExtF80$(OBJ) \
-  s_addMagsExtF80$(OBJ) \
+  s_normSubnormalF128Sig$(OBJ) \
-  s_subMagsExtF80$(OBJ) \
+  s_roundPackToF128$(OBJ) \
-  s_normSubnormalF128Sig$(OBJ) \
+  s_normRoundPackToF128$(OBJ) \
-  s_roundPackToF128$(OBJ) \
+  s_addMagsF128$(OBJ) \
-  s_normRoundPackToF128$(OBJ) \
+  s_subMagsF128$(OBJ) \
-  s_addMagsF128$(OBJ) \
+  s_mulAddF128$(OBJ) \
-  s_subMagsF128$(OBJ) \
+  softfloat_state$(OBJ) \
-  s_mulAddF128$(OBJ) \
+  ui32_to_f16$(OBJ) \
-  softfloat_state$(OBJ) \
+  ui32_to_f32$(OBJ) \
-  ui32_to_f16$(OBJ) \
+  ui32_to_f64$(OBJ) \
-  ui32_to_f32$(OBJ) \
+  ui32_to_extF80$(OBJ) \
-  ui32_to_f64$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
-  ui32_to_extF80$(OBJ) \
+  ui32_to_f128$(OBJ) \
-  ui32_to_extF80M$(OBJ) \
+  ui32_to_f128M$(OBJ) \
-  ui32_to_f128$(OBJ) \
+  ui64_to_f16$(OBJ) \
-  ui32_to_f128M$(OBJ) \
+  ui64_to_f32$(OBJ) \
-  ui64_to_f16$(OBJ) \
+  ui64_to_f64$(OBJ) \
-  ui64_to_f32$(OBJ) \
+  ui64_to_extF80$(OBJ) \
-  ui64_to_f64$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
-  ui64_to_extF80$(OBJ) \
+  ui64_to_f128$(OBJ) \
-  ui64_to_extF80M$(OBJ) \
+  ui64_to_f128M$(OBJ) \
-  ui64_to_f128$(OBJ) \
+  i32_to_f16$(OBJ) \
-  ui64_to_f128M$(OBJ) \
+  i32_to_f32$(OBJ) \
-  i32_to_f16$(OBJ) \
+  i32_to_f64$(OBJ) \
-  i32_to_f32$(OBJ) \
+  i32_to_extF80$(OBJ) \
-  i32_to_f64$(OBJ) \
+  i32_to_extF80M$(OBJ) \
-  i32_to_extF80$(OBJ) \
+  i32_to_f128$(OBJ) \
-  i32_to_extF80M$(OBJ) \
+  i32_to_f128M$(OBJ) \
-  i32_to_f128$(OBJ) \
+  i64_to_f16$(OBJ) \
-  i32_to_f128M$(OBJ) \
+  i64_to_f32$(OBJ) \
-  i64_to_f16$(OBJ) \
+  i64_to_f64$(OBJ) \
-  i64_to_f32$(OBJ) \
+  i64_to_extF80$(OBJ) \
-  i64_to_f64$(OBJ) \
+  i64_to_extF80M$(OBJ) \
-  i64_to_extF80$(OBJ) \
+  i64_to_f128$(OBJ) \
-  i64_to_extF80M$(OBJ) \
+  i64_to_f128M$(OBJ) \
-  i64_to_f128$(OBJ) \
+  f16_to_ui32$(OBJ) \
-  i64_to_f128M$(OBJ) \
+  f16_to_ui64$(OBJ) \
-  bf16_isSignalingNaN$(OBJ) \
+  f16_to_i32$(OBJ) \
-  bf16_to_f32$(OBJ) \
+  f16_to_i64$(OBJ) \
-  f16_to_ui32$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
-  f16_to_ui64$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
-  f16_to_i32$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
-  f16_to_i64$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
-  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_f32$(OBJ) \
-  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_f64$(OBJ) \
-  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_extF80$(OBJ) \
-  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_extF80M$(OBJ) \
-  f16_to_f32$(OBJ) \
+  f16_to_f128$(OBJ) \
-  f16_to_f64$(OBJ) \
+  f16_to_f128M$(OBJ) \
-  f16_to_extF80$(OBJ) \
+  f16_roundToInt$(OBJ) \
-  f16_to_extF80M$(OBJ) \
+  f16_add$(OBJ) \
-  f16_to_f128$(OBJ) \
+  f16_sub$(OBJ) \
-  f16_to_f128M$(OBJ) \
+  f16_mul$(OBJ) \
-  f16_roundToInt$(OBJ) \
+  f16_mulAdd$(OBJ) \
-  f16_add$(OBJ) \
+  f16_div$(OBJ) \
-  f16_sub$(OBJ) \
+  f16_rem$(OBJ) \
-  f16_mul$(OBJ) \
+  f16_sqrt$(OBJ) \
-  f16_mulAdd$(OBJ) \
+  f16_eq$(OBJ) \
-  f16_div$(OBJ) \
+  f16_le$(OBJ) \
-  f16_rem$(OBJ) \
+  f16_lt$(OBJ) \
-  f16_sqrt$(OBJ) \
+  f16_eq_signaling$(OBJ) \
-  f16_eq$(OBJ) \
+  f16_le_quiet$(OBJ) \
-  f16_le$(OBJ) \
+  f16_lt_quiet$(OBJ) \
-  f16_lt$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
-  f16_eq_signaling$(OBJ) \
+  f32_to_ui32$(OBJ) \
-  f16_le_quiet$(OBJ) \
+  f32_to_ui64$(OBJ) \
-  f16_lt_quiet$(OBJ) \
+  f32_to_i32$(OBJ) \
-  f16_isSignalingNaN$(OBJ) \
+  f32_to_i64$(OBJ) \
-  f32_to_ui32$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
-  f32_to_ui64$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
-  f32_to_i32$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
-  f32_to_i64$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
-  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_f16$(OBJ) \
-  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_f64$(OBJ) \
-  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_extF80$(OBJ) \
-  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_extF80M$(OBJ) \
-  f32_to_bf16$(OBJ) \
+  f32_to_f128$(OBJ) \
-  f32_to_f16$(OBJ) \
+  f32_to_f128M$(OBJ) \
-  f32_to_f64$(OBJ) \
+  f32_roundToInt$(OBJ) \
-  f32_to_extF80$(OBJ) \
+  f32_add$(OBJ) \
-  f32_to_extF80M$(OBJ) \
+  f32_sub$(OBJ) \
-  f32_to_f128$(OBJ) \
+  f32_mul$(OBJ) \
-  f32_to_f128M$(OBJ) \
+  f32_mulAdd$(OBJ) \
-  f32_roundToInt$(OBJ) \
+  f32_div$(OBJ) \
-  f32_add$(OBJ) \
+  f32_rem$(OBJ) \
-  f32_sub$(OBJ) \
+  f32_sqrt$(OBJ) \
-  f32_mul$(OBJ) \
+  f32_eq$(OBJ) \
-  f32_mulAdd$(OBJ) \
+  f32_le$(OBJ) \
-  f32_div$(OBJ) \
+  f32_lt$(OBJ) \
-  f32_rem$(OBJ) \
+  f32_eq_signaling$(OBJ) \
-  f32_sqrt$(OBJ) \
+  f32_le_quiet$(OBJ) \
-  f32_eq$(OBJ) \
+  f32_lt_quiet$(OBJ) \
-  f32_le$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
-  f32_lt$(OBJ) \
+  f64_to_ui32$(OBJ) \
-  f32_eq_signaling$(OBJ) \
+  f64_to_ui64$(OBJ) \
-  f32_le_quiet$(OBJ) \
+  f64_to_i32$(OBJ) \
-  f32_lt_quiet$(OBJ) \
+  f64_to_i64$(OBJ) \
-  f32_isSignalingNaN$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
-  f64_to_ui32$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
-  f64_to_ui64$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
-  f64_to_i32$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
-  f64_to_i64$(OBJ) \
+  f64_to_f16$(OBJ) \
-  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_f32$(OBJ) \
-  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_extF80$(OBJ) \
-  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_extF80M$(OBJ) \
-  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_f128$(OBJ) \
-  f64_to_f16$(OBJ) \
+  f64_to_f128M$(OBJ) \
-  f64_to_f32$(OBJ) \
+  f64_roundToInt$(OBJ) \
-  f64_to_extF80$(OBJ) \
+  f64_add$(OBJ) \
-  f64_to_extF80M$(OBJ) \
+  f64_sub$(OBJ) \
-  f64_to_f128$(OBJ) \
+  f64_mul$(OBJ) \
-  f64_to_f128M$(OBJ) \
+  f64_mulAdd$(OBJ) \
-  f64_roundToInt$(OBJ) \
+  f64_div$(OBJ) \
-  f64_add$(OBJ) \
+  f64_rem$(OBJ) \
-  f64_sub$(OBJ) \
+  f64_sqrt$(OBJ) \
-  f64_mul$(OBJ) \
+  f64_eq$(OBJ) \
-  f64_mulAdd$(OBJ) \
+  f64_le$(OBJ) \
-  f64_div$(OBJ) \
+  f64_lt$(OBJ) \
-  f64_rem$(OBJ) \
+  f64_eq_signaling$(OBJ) \
-  f64_sqrt$(OBJ) \
+  f64_le_quiet$(OBJ) \
-  f64_eq$(OBJ) \
+  f64_lt_quiet$(OBJ) \
-  f64_le$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
-  f64_lt$(OBJ) \
+  extF80_to_ui32$(OBJ) \
-  f64_eq_signaling$(OBJ) \
+  extF80_to_ui64$(OBJ) \
-  f64_le_quiet$(OBJ) \
+  extF80_to_i32$(OBJ) \
-  f64_lt_quiet$(OBJ) \
+  extF80_to_i64$(OBJ) \
-  f64_isSignalingNaN$(OBJ) \
+  extF80_to_ui32_r_minMag$(OBJ) \
-  extF80_to_ui32$(OBJ) \
+  extF80_to_ui64_r_minMag$(OBJ) \
-  extF80_to_ui64$(OBJ) \
+  extF80_to_i32_r_minMag$(OBJ) \
-  extF80_to_i32$(OBJ) \
+  extF80_to_i64_r_minMag$(OBJ) \
-  extF80_to_i64$(OBJ) \
+  extF80_to_f16$(OBJ) \
-  extF80_to_ui32_r_minMag$(OBJ) \
+  extF80_to_f32$(OBJ) \
-  extF80_to_ui64_r_minMag$(OBJ) \
+  extF80_to_f64$(OBJ) \
-  extF80_to_i32_r_minMag$(OBJ) \
+  extF80_to_f128$(OBJ) \
-  extF80_to_i64_r_minMag$(OBJ) \
+  extF80_roundToInt$(OBJ) \
-  extF80_to_f16$(OBJ) \
+  extF80_add$(OBJ) \
-  extF80_to_f32$(OBJ) \
+  extF80_sub$(OBJ) \
-  extF80_to_f64$(OBJ) \
+  extF80_mul$(OBJ) \
-  extF80_to_f128$(OBJ) \
+  extF80_div$(OBJ) \
-  extF80_roundToInt$(OBJ) \
+  extF80_rem$(OBJ) \
-  extF80_add$(OBJ) \
+  extF80_sqrt$(OBJ) \
-  extF80_sub$(OBJ) \
+  extF80_eq$(OBJ) \
-  extF80_mul$(OBJ) \
+  extF80_le$(OBJ) \
-  extF80_div$(OBJ) \
+  extF80_lt$(OBJ) \
-  extF80_rem$(OBJ) \
+  extF80_eq_signaling$(OBJ) \
-  extF80_sqrt$(OBJ) \
+  extF80_le_quiet$(OBJ) \
-  extF80_eq$(OBJ) \
+  extF80_lt_quiet$(OBJ) \
-  extF80_le$(OBJ) \
+  extF80_isSignalingNaN$(OBJ) \
-  extF80_lt$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
-  extF80_eq_signaling$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
-  extF80_le_quiet$(OBJ) \
+  extF80M_to_i32$(OBJ) \
-  extF80_lt_quiet$(OBJ) \
+  extF80M_to_i64$(OBJ) \
-  extF80_isSignalingNaN$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
-  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
-  extF80M_to_ui64$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
-  extF80M_to_i32$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
-  extF80M_to_i64$(OBJ) \
+  extF80M_to_f16$(OBJ) \
-  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_f32$(OBJ) \
-  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_f64$(OBJ) \
-  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
-  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
-  extF80M_to_f16$(OBJ) \
+  extF80M_add$(OBJ) \
-  extF80M_to_f32$(OBJ) \
+  extF80M_sub$(OBJ) \
-  extF80M_to_f64$(OBJ) \
+  extF80M_mul$(OBJ) \
-  extF80M_to_f128M$(OBJ) \
+  extF80M_div$(OBJ) \
-  extF80M_roundToInt$(OBJ) \
+  extF80M_rem$(OBJ) \
-  extF80M_add$(OBJ) \
+  extF80M_sqrt$(OBJ) \
-  extF80M_sub$(OBJ) \
+  extF80M_eq$(OBJ) \
-  extF80M_mul$(OBJ) \
+  extF80M_le$(OBJ) \
-  extF80M_div$(OBJ) \
+  extF80M_lt$(OBJ) \
-  extF80M_rem$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
-  extF80M_sqrt$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
-  extF80M_eq$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
-  extF80M_le$(OBJ) \
+  f128_to_ui32$(OBJ) \
-  extF80M_lt$(OBJ) \
+  f128_to_ui64$(OBJ) \
-  extF80M_eq_signaling$(OBJ) \
+  f128_to_i32$(OBJ) \
-  extF80M_le_quiet$(OBJ) \
+  f128_to_i64$(OBJ) \
-  extF80M_lt_quiet$(OBJ) \
+  f128_to_ui32_r_minMag$(OBJ) \
-  f128_to_ui32$(OBJ) \
+  f128_to_ui64_r_minMag$(OBJ) \
-  f128_to_ui64$(OBJ) \
+  f128_to_i32_r_minMag$(OBJ) \
-  f128_to_i32$(OBJ) \
+  f128_to_i64_r_minMag$(OBJ) \
-  f128_to_i64$(OBJ) \
+  f128_to_f16$(OBJ) \
-  f128_to_ui32_r_minMag$(OBJ) \
+  f128_to_f32$(OBJ) \
-  f128_to_ui64_r_minMag$(OBJ) \
+  f128_to_extF80$(OBJ) \
-  f128_to_i32_r_minMag$(OBJ) \
+  f128_to_f64$(OBJ) \
-  f128_to_i64_r_minMag$(OBJ) \
+  f128_roundToInt$(OBJ) \
-  f128_to_f16$(OBJ) \
+  f128_add$(OBJ) \
-  f128_to_f32$(OBJ) \
+  f128_sub$(OBJ) \
-  f128_to_extF80$(OBJ) \
+  f128_mul$(OBJ) \
-  f128_to_f64$(OBJ) \
+  f128_mulAdd$(OBJ) \
-  f128_roundToInt$(OBJ) \
+  f128_div$(OBJ) \
-  f128_add$(OBJ) \
+  f128_rem$(OBJ) \
-  f128_sub$(OBJ) \
+  f128_sqrt$(OBJ) \
-  f128_mul$(OBJ) \
+  f128_eq$(OBJ) \
-  f128_mulAdd$(OBJ) \
+  f128_le$(OBJ) \
-  f128_div$(OBJ) \
+  f128_lt$(OBJ) \
-  f128_rem$(OBJ) \
+  f128_eq_signaling$(OBJ) \
-  f128_sqrt$(OBJ) \
+  f128_le_quiet$(OBJ) \
-  f128_eq$(OBJ) \
+  f128_lt_quiet$(OBJ) \
-  f128_le$(OBJ) \
+  f128_isSignalingNaN$(OBJ) \
-  f128_lt$(OBJ) \
+  f128M_to_ui32$(OBJ) \
-  f128_eq_signaling$(OBJ) \
+  f128M_to_ui64$(OBJ) \
-  f128_le_quiet$(OBJ) \
+  f128M_to_i32$(OBJ) \
-  f128_lt_quiet$(OBJ) \
+  f128M_to_i64$(OBJ) \
-  f128_isSignalingNaN$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
-  f128M_to_ui32$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
-  f128M_to_ui64$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
-  f128M_to_i32$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
-  f128M_to_i64$(OBJ) \
+  f128M_to_f16$(OBJ) \
-  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_f32$(OBJ) \
-  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
-  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_f64$(OBJ) \
-  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_roundToInt$(OBJ) \
-  f128M_to_f16$(OBJ) \
+  f128M_add$(OBJ) \
-  f128M_to_f32$(OBJ) \
+  f128M_sub$(OBJ) \
-  f128M_to_extF80M$(OBJ) \
+  f128M_mul$(OBJ) \
-  f128M_to_f64$(OBJ) \
+  f128M_mulAdd$(OBJ) \
-  f128M_roundToInt$(OBJ) \
+  f128M_div$(OBJ) \
-  f128M_add$(OBJ) \
+  f128M_rem$(OBJ) \
-  f128M_sub$(OBJ) \
+  f128M_sqrt$(OBJ) \
-  f128M_mul$(OBJ) \
+  f128M_eq$(OBJ) \
-  f128M_mulAdd$(OBJ) \
+  f128M_le$(OBJ) \
-  f128M_div$(OBJ) \
+  f128M_lt$(OBJ) \
-  f128M_rem$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
-  f128M_sqrt$(OBJ) \
+  f128M_le_quiet$(OBJ) \
-  f128M_eq$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
-  f128M_le$(OBJ) \
+
-  f128M_lt$(OBJ) \
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
-  f128M_eq_signaling$(OBJ) \
+
-  f128M_le_quiet$(OBJ) \
+$(OBJS_ALL): \
-  f128M_lt_quiet$(OBJ) \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
-
+  $(SOURCE_DIR)/include/primitives.h
-OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
-
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
-$(OBJS_ALL): \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
-  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(SOURCE_DIR)/include/softfloat.h
-  $(SOURCE_DIR)/include/primitives.h
+
-$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
-  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
-  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+
-  $(SOURCE_DIR)/include/softfloat.h
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
-
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
-$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+
-	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+softfloat$(LIB): $(OBJS_ALL)
-
+	$(DELETE) $@
-$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+	$(MAKELIB) $^
-	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+
-
+.PHONY: clean
-softfloat$(LIB): $(OBJS_ALL)
+clean:
-	$(DELETE) $@
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
-	$(MAKELIB) $^
+
-
-.PHONY: clean
-clean:
-	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
-

softfloat/build/template-FAST_INT64/platform.h

@@ -1,50 +1,50 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C header template is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C header template is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
-California.  All rights reserved.
+California.  All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-// Edit lines marked with `==>'.  See "SoftFloat-source.html".
+// Edit lines marked with `==>'.  See "SoftFloat-source.html".
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-==> #define LITTLEENDIAN 1
+==> #define LITTLEENDIAN 1
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-==> #define INLINE inline
+==> #define INLINE inline
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-==> #define THREAD_LOCAL _Thread_local
+==> #define THREAD_LOCAL _Thread_local
-
+

softfloat/build/template-not-FAST_INT64/Makefile

@@ -1,325 +1,325 @@
-
+
-#=============================================================================
+#=============================================================================
-#
+#
-# This Makefile template is part of the SoftFloat IEEE Floating-Point
+# This Makefile template is part of the SoftFloat IEEE Floating-Point
-# Arithmetic Package, Release 3e, by John R. Hauser.
+# Arithmetic Package, Release 3e, by John R. Hauser.
-#
+#
-# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
-# University of California.  All rights reserved.
+# University of California.  All rights reserved.
-#
+#
-# Redistribution and use in source and binary forms, with or without
+# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
+# modification, are permitted provided that the following conditions are met:
-#
+#
-#  1. Redistributions of source code must retain the above copyright notice,
+#  1. Redistributions of source code must retain the above copyright notice,
-#     this list of conditions, and the following disclaimer.
+#     this list of conditions, and the following disclaimer.
-#
+#
-#  2. Redistributions in binary form must reproduce the above copyright
+#  2. Redistributions in binary form must reproduce the above copyright
-#     notice, this list of conditions, and the following disclaimer in the
+#     notice, this list of conditions, and the following disclaimer in the
-#     documentation and/or other materials provided with the distribution.
+#     documentation and/or other materials provided with the distribution.
-#
+#
-#  3. Neither the name of the University nor the names of its contributors
+#  3. Neither the name of the University nor the names of its contributors
-#     may be used to endorse or promote products derived from this software
+#     may be used to endorse or promote products derived from this software
-#     without specific prior written permission.
+#     without specific prior written permission.
-#
+#
-# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
+#
-#=============================================================================
+#=============================================================================
-
+
-# Edit lines marked with `==>'.  See "SoftFloat-source.html".
+# Edit lines marked with `==>'.  See "SoftFloat-source.html".
-
+
-==> SOURCE_DIR ?= ../../source
+==> SOURCE_DIR ?= ../../source
-==> SPECIALIZE_TYPE ?= 8086
+==> SPECIALIZE_TYPE ?= 8086
-
+
-==> SOFTFLOAT_OPTS ?= \
+==> SOFTFLOAT_OPTS ?= \
-==>   -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+==>   -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
-==>   -DSOFTFLOAT_FAST_DIV64TO32
+==>   -DSOFTFLOAT_FAST_DIV64TO32
-
+
-==> DELETE = rm -f
+==> DELETE = rm -f
-==> C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+==> C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
-==> COMPILE_C = cc -c $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
+==> COMPILE_C = cc -c $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
-==> MAKELIB = ar crs $@
+==> MAKELIB = ar crs $@
-
+
-==> OBJ = .o
+==> OBJ = .o
-==> LIB = .a
+==> LIB = .a
-
+
-==> OTHER_HEADERS =
+==> OTHER_HEADERS =
-
+
-.PHONY: all
+.PHONY: all
-all: softfloat$(LIB)
+all: softfloat$(LIB)
-
+
-OBJS_PRIMITIVES = \
+OBJS_PRIMITIVES = \
-  s_compare96M$(OBJ) \
+  s_compare96M$(OBJ) \
-  s_compare128M$(OBJ) \
+  s_compare128M$(OBJ) \
-  s_shortShiftLeft64To96M$(OBJ) \
+  s_shortShiftLeft64To96M$(OBJ) \
-  s_shortShiftLeftM$(OBJ) \
+  s_shortShiftLeftM$(OBJ) \
-  s_shiftLeftM$(OBJ) \
+  s_shiftLeftM$(OBJ) \
-  s_shortShiftRightM$(OBJ) \
+  s_shortShiftRightM$(OBJ) \
-  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
-  s_shortShiftRightJamM$(OBJ) \
+  s_shortShiftRightJamM$(OBJ) \
-  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
-  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
-  s_shiftRightJamM$(OBJ) \
+  s_shiftRightJamM$(OBJ) \
-  s_shiftRightM$(OBJ) \
+  s_shiftRightM$(OBJ) \
-  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
-  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
-  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
-  s_countLeadingZeros64$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
-  s_addM$(OBJ) \
+  s_addM$(OBJ) \
-  s_addCarryM$(OBJ) \
+  s_addCarryM$(OBJ) \
-  s_addComplCarryM$(OBJ) \
+  s_addComplCarryM$(OBJ) \
-  s_negXM$(OBJ) \
+  s_negXM$(OBJ) \
-  s_sub1XM$(OBJ) \
+  s_sub1XM$(OBJ) \
-  s_subM$(OBJ) \
+  s_subM$(OBJ) \
-  s_mul64To128M$(OBJ) \
+  s_mul64To128M$(OBJ) \
-  s_mul128MTo256M$(OBJ) \
+  s_mul128MTo256M$(OBJ) \
-  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
-  s_approxRecip32_1$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
-  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
-  s_approxRecipSqrt32_1$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
-  s_remStepMBy32$(OBJ) \
+  s_remStepMBy32$(OBJ) \
-
+
-OBJS_SPECIALIZE = \
+OBJS_SPECIALIZE = \
-  softfloat_raiseFlags$(OBJ) \
+  softfloat_raiseFlags$(OBJ) \
-  s_f16UIToCommonNaN$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
-  s_commonNaNToF16UI$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
-  s_propagateNaNF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
-  s_f32UIToCommonNaN$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
-  s_commonNaNToF32UI$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
-  s_propagateNaNF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
-  s_f64UIToCommonNaN$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
-  s_commonNaNToF64UI$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
-  s_propagateNaNF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
-  extF80M_isSignalingNaN$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
-  s_extF80MToCommonNaN$(OBJ) \
+  s_extF80MToCommonNaN$(OBJ) \
-  s_commonNaNToExtF80M$(OBJ) \
+  s_commonNaNToExtF80M$(OBJ) \
-  s_propagateNaNExtF80M$(OBJ) \
+  s_propagateNaNExtF80M$(OBJ) \
-  f128M_isSignalingNaN$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
-  s_f128MToCommonNaN$(OBJ) \
+  s_f128MToCommonNaN$(OBJ) \
-  s_commonNaNToF128M$(OBJ) \
+  s_commonNaNToF128M$(OBJ) \
-  s_propagateNaNF128M$(OBJ) \
+  s_propagateNaNF128M$(OBJ) \
-
+
-OBJS_OTHERS = \
+OBJS_OTHERS = \
-  s_roundToUI32$(OBJ) \
+  s_roundToUI32$(OBJ) \
-  s_roundMToUI64$(OBJ) \
+  s_roundMToUI64$(OBJ) \
-  s_roundToI32$(OBJ) \
+  s_roundToI32$(OBJ) \
-  s_roundMToI64$(OBJ) \
+  s_roundMToI64$(OBJ) \
-  s_normSubnormalF16Sig$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
-  s_roundPackToF16$(OBJ) \
+  s_roundPackToF16$(OBJ) \
-  s_normRoundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
-  s_addMagsF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
-  s_subMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
-  s_mulAddF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
-  s_normSubnormalF32Sig$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
-  s_roundPackToF32$(OBJ) \
+  s_roundPackToF32$(OBJ) \
-  s_normRoundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
-  s_addMagsF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
-  s_subMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
-  s_mulAddF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
-  s_normSubnormalF64Sig$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
-  s_roundPackToF64$(OBJ) \
+  s_roundPackToF64$(OBJ) \
-  s_normRoundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
-  s_addMagsF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
-  s_subMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
-  s_mulAddF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
-  s_tryPropagateNaNExtF80M$(OBJ) \
+  s_tryPropagateNaNExtF80M$(OBJ) \
-  s_invalidExtF80M$(OBJ) \
+  s_invalidExtF80M$(OBJ) \
-  s_normExtF80SigM$(OBJ) \
+  s_normExtF80SigM$(OBJ) \
-  s_roundPackMToExtF80M$(OBJ) \
+  s_roundPackMToExtF80M$(OBJ) \
-  s_normRoundPackMToExtF80M$(OBJ) \
+  s_normRoundPackMToExtF80M$(OBJ) \
-  s_addExtF80M$(OBJ) \
+  s_addExtF80M$(OBJ) \
-  s_compareNonnormExtF80M$(OBJ) \
+  s_compareNonnormExtF80M$(OBJ) \
-  s_isNaNF128M$(OBJ) \
+  s_isNaNF128M$(OBJ) \
-  s_tryPropagateNaNF128M$(OBJ) \
+  s_tryPropagateNaNF128M$(OBJ) \
-  s_invalidF128M$(OBJ) \
+  s_invalidF128M$(OBJ) \
-  s_shiftNormSigF128M$(OBJ) \
+  s_shiftNormSigF128M$(OBJ) \
-  s_roundPackMToF128M$(OBJ) \
+  s_roundPackMToF128M$(OBJ) \
-  s_normRoundPackMToF128M$(OBJ) \
+  s_normRoundPackMToF128M$(OBJ) \
-  s_addF128M$(OBJ) \
+  s_addF128M$(OBJ) \
-  s_mulAddF128M$(OBJ) \
+  s_mulAddF128M$(OBJ) \
-  softfloat_state$(OBJ) \
+  softfloat_state$(OBJ) \
-  ui32_to_f16$(OBJ) \
+  ui32_to_f16$(OBJ) \
-  ui32_to_f32$(OBJ) \
+  ui32_to_f32$(OBJ) \
-  ui32_to_f64$(OBJ) \
+  ui32_to_f64$(OBJ) \
-  ui32_to_extF80M$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
-  ui32_to_f128M$(OBJ) \
+  ui32_to_f128M$(OBJ) \
-  ui64_to_f16$(OBJ) \
+  ui64_to_f16$(OBJ) \
-  ui64_to_f32$(OBJ) \
+  ui64_to_f32$(OBJ) \
-  ui64_to_f64$(OBJ) \
+  ui64_to_f64$(OBJ) \
-  ui64_to_extF80M$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
-  ui64_to_f128M$(OBJ) \
+  ui64_to_f128M$(OBJ) \
-  i32_to_f16$(OBJ) \
+  i32_to_f16$(OBJ) \
-  i32_to_f32$(OBJ) \
+  i32_to_f32$(OBJ) \
-  i32_to_f64$(OBJ) \
+  i32_to_f64$(OBJ) \
-  i32_to_extF80M$(OBJ) \
+  i32_to_extF80M$(OBJ) \
-  i32_to_f128M$(OBJ) \
+  i32_to_f128M$(OBJ) \
-  i64_to_f16$(OBJ) \
+  i64_to_f16$(OBJ) \
-  i64_to_f32$(OBJ) \
+  i64_to_f32$(OBJ) \
-  i64_to_f64$(OBJ) \
+  i64_to_f64$(OBJ) \
-  i64_to_extF80M$(OBJ) \
+  i64_to_extF80M$(OBJ) \
-  i64_to_f128M$(OBJ) \
+  i64_to_f128M$(OBJ) \
-  f16_to_ui32$(OBJ) \
+  f16_to_ui32$(OBJ) \
-  f16_to_ui64$(OBJ) \
+  f16_to_ui64$(OBJ) \
-  f16_to_i32$(OBJ) \
+  f16_to_i32$(OBJ) \
-  f16_to_i64$(OBJ) \
+  f16_to_i64$(OBJ) \
-  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
-  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
-  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
-  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
-  f16_to_f32$(OBJ) \
+  f16_to_f32$(OBJ) \
-  f16_to_f64$(OBJ) \
+  f16_to_f64$(OBJ) \
-  f16_to_extF80M$(OBJ) \
+  f16_to_extF80M$(OBJ) \
-  f16_to_f128M$(OBJ) \
+  f16_to_f128M$(OBJ) \
-  f16_roundToInt$(OBJ) \
+  f16_roundToInt$(OBJ) \
-  f16_add$(OBJ) \
+  f16_add$(OBJ) \
-  f16_sub$(OBJ) \
+  f16_sub$(OBJ) \
-  f16_mul$(OBJ) \
+  f16_mul$(OBJ) \
-  f16_mulAdd$(OBJ) \
+  f16_mulAdd$(OBJ) \
-  f16_div$(OBJ) \
+  f16_div$(OBJ) \
-  f16_rem$(OBJ) \
+  f16_rem$(OBJ) \
-  f16_sqrt$(OBJ) \
+  f16_sqrt$(OBJ) \
-  f16_eq$(OBJ) \
+  f16_eq$(OBJ) \
-  f16_le$(OBJ) \
+  f16_le$(OBJ) \
-  f16_lt$(OBJ) \
+  f16_lt$(OBJ) \
-  f16_eq_signaling$(OBJ) \
+  f16_eq_signaling$(OBJ) \
-  f16_le_quiet$(OBJ) \
+  f16_le_quiet$(OBJ) \
-  f16_lt_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
-  f16_isSignalingNaN$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
-  f32_to_ui32$(OBJ) \
+  f32_to_ui32$(OBJ) \
-  f32_to_ui64$(OBJ) \
+  f32_to_ui64$(OBJ) \
-  f32_to_i32$(OBJ) \
+  f32_to_i32$(OBJ) \
-  f32_to_i64$(OBJ) \
+  f32_to_i64$(OBJ) \
-  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
-  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
-  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
-  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
-  f32_to_f16$(OBJ) \
+  f32_to_f16$(OBJ) \
-  f32_to_f64$(OBJ) \
+  f32_to_f64$(OBJ) \
-  f32_to_extF80M$(OBJ) \
+  f32_to_extF80M$(OBJ) \
-  f32_to_f128M$(OBJ) \
+  f32_to_f128M$(OBJ) \
-  f32_roundToInt$(OBJ) \
+  f32_roundToInt$(OBJ) \
-  f32_add$(OBJ) \
+  f32_add$(OBJ) \
-  f32_sub$(OBJ) \
+  f32_sub$(OBJ) \
-  f32_mul$(OBJ) \
+  f32_mul$(OBJ) \
-  f32_mulAdd$(OBJ) \
+  f32_mulAdd$(OBJ) \
-  f32_div$(OBJ) \
+  f32_div$(OBJ) \
-  f32_rem$(OBJ) \
+  f32_rem$(OBJ) \
-  f32_sqrt$(OBJ) \
+  f32_sqrt$(OBJ) \
-  f32_eq$(OBJ) \
+  f32_eq$(OBJ) \
-  f32_le$(OBJ) \
+  f32_le$(OBJ) \
-  f32_lt$(OBJ) \
+  f32_lt$(OBJ) \
-  f32_eq_signaling$(OBJ) \
+  f32_eq_signaling$(OBJ) \
-  f32_le_quiet$(OBJ) \
+  f32_le_quiet$(OBJ) \
-  f32_lt_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
-  f32_isSignalingNaN$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
-  f64_to_ui32$(OBJ) \
+  f64_to_ui32$(OBJ) \
-  f64_to_ui64$(OBJ) \
+  f64_to_ui64$(OBJ) \
-  f64_to_i32$(OBJ) \
+  f64_to_i32$(OBJ) \
-  f64_to_i64$(OBJ) \
+  f64_to_i64$(OBJ) \
-  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
-  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
-  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
-  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
-  f64_to_f16$(OBJ) \
+  f64_to_f16$(OBJ) \
-  f64_to_f32$(OBJ) \
+  f64_to_f32$(OBJ) \
-  f64_to_extF80M$(OBJ) \
+  f64_to_extF80M$(OBJ) \
-  f64_to_f128M$(OBJ) \
+  f64_to_f128M$(OBJ) \
-  f64_roundToInt$(OBJ) \
+  f64_roundToInt$(OBJ) \
-  f64_add$(OBJ) \
+  f64_add$(OBJ) \
-  f64_sub$(OBJ) \
+  f64_sub$(OBJ) \
-  f64_mul$(OBJ) \
+  f64_mul$(OBJ) \
-  f64_mulAdd$(OBJ) \
+  f64_mulAdd$(OBJ) \
-  f64_div$(OBJ) \
+  f64_div$(OBJ) \
-  f64_rem$(OBJ) \
+  f64_rem$(OBJ) \
-  f64_sqrt$(OBJ) \
+  f64_sqrt$(OBJ) \
-  f64_eq$(OBJ) \
+  f64_eq$(OBJ) \
-  f64_le$(OBJ) \
+  f64_le$(OBJ) \
-  f64_lt$(OBJ) \
+  f64_lt$(OBJ) \
-  f64_eq_signaling$(OBJ) \
+  f64_eq_signaling$(OBJ) \
-  f64_le_quiet$(OBJ) \
+  f64_le_quiet$(OBJ) \
-  f64_lt_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
-  f64_isSignalingNaN$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
-  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
-  extF80M_to_ui64$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
-  extF80M_to_i32$(OBJ) \
+  extF80M_to_i32$(OBJ) \
-  extF80M_to_i64$(OBJ) \
+  extF80M_to_i64$(OBJ) \
-  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
-  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
-  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
-  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
-  extF80M_to_f16$(OBJ) \
+  extF80M_to_f16$(OBJ) \
-  extF80M_to_f32$(OBJ) \
+  extF80M_to_f32$(OBJ) \
-  extF80M_to_f64$(OBJ) \
+  extF80M_to_f64$(OBJ) \
-  extF80M_to_f128M$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
-  extF80M_roundToInt$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
-  extF80M_add$(OBJ) \
+  extF80M_add$(OBJ) \
-  extF80M_sub$(OBJ) \
+  extF80M_sub$(OBJ) \
-  extF80M_mul$(OBJ) \
+  extF80M_mul$(OBJ) \
-  extF80M_div$(OBJ) \
+  extF80M_div$(OBJ) \
-  extF80M_rem$(OBJ) \
+  extF80M_rem$(OBJ) \
-  extF80M_sqrt$(OBJ) \
+  extF80M_sqrt$(OBJ) \
-  extF80M_eq$(OBJ) \
+  extF80M_eq$(OBJ) \
-  extF80M_le$(OBJ) \
+  extF80M_le$(OBJ) \
-  extF80M_lt$(OBJ) \
+  extF80M_lt$(OBJ) \
-  extF80M_eq_signaling$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
-  extF80M_le_quiet$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
-  extF80M_lt_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
-  f128M_to_ui32$(OBJ) \
+  f128M_to_ui32$(OBJ) \
-  f128M_to_ui64$(OBJ) \
+  f128M_to_ui64$(OBJ) \
-  f128M_to_i32$(OBJ) \
+  f128M_to_i32$(OBJ) \
-  f128M_to_i64$(OBJ) \
+  f128M_to_i64$(OBJ) \
-  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
-  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
-  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
-  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
-  f128M_to_f16$(OBJ) \
+  f128M_to_f16$(OBJ) \
-  f128M_to_f32$(OBJ) \
+  f128M_to_f32$(OBJ) \
-  f128M_to_f64$(OBJ) \
+  f128M_to_f64$(OBJ) \
-  f128M_to_extF80M$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
-  f128M_roundToInt$(OBJ) \
+  f128M_roundToInt$(OBJ) \
-  f128M_add$(OBJ) \
+  f128M_add$(OBJ) \
-  f128M_sub$(OBJ) \
+  f128M_sub$(OBJ) \
-  f128M_mul$(OBJ) \
+  f128M_mul$(OBJ) \
-  f128M_mulAdd$(OBJ) \
+  f128M_mulAdd$(OBJ) \
-  f128M_div$(OBJ) \
+  f128M_div$(OBJ) \
-  f128M_rem$(OBJ) \
+  f128M_rem$(OBJ) \
-  f128M_sqrt$(OBJ) \
+  f128M_sqrt$(OBJ) \
-  f128M_eq$(OBJ) \
+  f128M_eq$(OBJ) \
-  f128M_le$(OBJ) \
+  f128M_le$(OBJ) \
-  f128M_lt$(OBJ) \
+  f128M_lt$(OBJ) \
-  f128M_eq_signaling$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
-  f128M_le_quiet$(OBJ) \
+  f128M_le_quiet$(OBJ) \
-  f128M_lt_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
-
+
-OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
-
+
-$(OBJS_ALL): \
+$(OBJS_ALL): \
-  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
-  $(SOURCE_DIR)/include/primitives.h
+  $(SOURCE_DIR)/include/primitives.h
-$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
-  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
-  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
-  $(SOURCE_DIR)/include/softfloat.h
+  $(SOURCE_DIR)/include/softfloat.h
-
+
-$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
-
+
-$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
-	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
-
+
-softfloat$(LIB): $(OBJS_ALL)
+softfloat$(LIB): $(OBJS_ALL)
-	$(DELETE) $@
+	$(DELETE) $@
-	$(MAKELIB) $^
+	$(MAKELIB) $^
-
+
-.PHONY: clean
+.PHONY: clean
-clean:
+clean:
-	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
-
+

softfloat/build/template-not-FAST_INT64/platform.h

@@ -1,50 +1,50 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C header template is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C header template is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
-California.  All rights reserved.
+California.  All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-// Edit lines marked with `==>'.  See "SoftFloat-source.html".
+// Edit lines marked with `==>'.  See "SoftFloat-source.html".
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-==> #define LITTLEENDIAN 1
+==> #define LITTLEENDIAN 1
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-==> #define INLINE inline
+==> #define INLINE inline
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-==> #define THREAD_LOCAL _Thread_local
+==> #define THREAD_LOCAL _Thread_local
-
+

softfloat/doc/SoftFloat-history.html

@@ -1,258 +1,258 @@
-
+
-<HTML>
+<HTML>
-
+
-<HEAD>
+<HEAD>
-<TITLE>Berkeley SoftFloat History</TITLE>
+<TITLE>Berkeley SoftFloat History</TITLE>
-</HEAD>
+</HEAD>
-
+
-<BODY>
+<BODY>
-
+
-<H1>History of Berkeley SoftFloat, to Release 3e</H1>
+<H1>History of Berkeley SoftFloat, to Release 3e</H1>
-
+
-<P>
+<P>
-John R. Hauser<BR>
+John R. Hauser<BR>
-2018 January 20<BR>
+2018 January 20<BR>
-</P>
+</P>
-
+
-
+
-<H3>Release 3e (2018 January)</H3>
+<H3>Release 3e (2018 January)</H3>
-
+
-<UL>
+<UL>
-
+
-<LI>
+<LI>
-Changed the default numeric code for optional rounding mode <CODE>odd</CODE>
+Changed the default numeric code for optional rounding mode <CODE>odd</CODE>
-(round to odd, also known as <EM>jamming</EM>) from 5 to 6.
+(round to odd, also known as <EM>jamming</EM>) from 5 to 6.
-
+
-<LI>
+<LI>
-Modified the behavior of rounding mode <CODE>odd</CODE> when rounding to an
+Modified the behavior of rounding mode <CODE>odd</CODE> when rounding to an
-integer value (either conversion to an integer format or a
+integer value (either conversion to an integer format or a
-&lsquo;<CODE>roundToInt</CODE>&rsquo; function).
+&lsquo;<CODE>roundToInt</CODE>&rsquo; function).
-Previously, for those cases only, rounding mode <CODE>odd</CODE> acted the same
+Previously, for those cases only, rounding mode <CODE>odd</CODE> acted the same
-as rounding to minimum magnitude.
+as rounding to minimum magnitude.
-Now all operations are rounded consistently.
+Now all operations are rounded consistently.
-
+
-<LI>
+<LI>
-Fixed some errors in the specialization code modeling Intel x86 floating-point,
+Fixed some errors in the specialization code modeling Intel x86 floating-point,
-specifically the integers returned on invalid operations and the propagation of
+specifically the integers returned on invalid operations and the propagation of
-NaN payloads in a few rare cases.
+NaN payloads in a few rare cases.
-
+
-<LI>
+<LI>
-Added specialization code modeling ARM floating-point, conforming to VFPv2 or
+Added specialization code modeling ARM floating-point, conforming to VFPv2 or
-later.
+later.
-
+
-<LI>
+<LI>
-Added an example target for ARM processors.
+Added an example target for ARM processors.
-
+
-<LI>
+<LI>
-Fixed a minor bug whereby function <CODE>f16_to_ui64</CODE> might return a
+Fixed a minor bug whereby function <CODE>f16_to_ui64</CODE> might return a
-different integer than expected in the case that the floating-point operand is
+different integer than expected in the case that the floating-point operand is
-negative.
+negative.
-
+
-<LI>
+<LI>
-Added example target-specific optimization for GCC, employing GCC instrinsics
+Added example target-specific optimization for GCC, employing GCC instrinsics
-and support for <NOBR>128-bit</NOBR> integer arithmetic.
+and support for <NOBR>128-bit</NOBR> integer arithmetic.
-
+
-<LI>
+<LI>
-Made other minor improvements.
+Made other minor improvements.
-
+
-</UL>
+</UL>
-
+
-
+
-<H3>Release 3d (2017 August)</H3>
+<H3>Release 3d (2017 August)</H3>
-
+
-<UL>
+<UL>
-
+
-<LI>
+<LI>
-Fixed bugs in the square root functions for <NOBR>64-bit</NOBR>
+Fixed bugs in the square root functions for <NOBR>64-bit</NOBR>
-double-precision, <NOBR>80-bit</NOBR> double-extended-precision, and
+double-precision, <NOBR>80-bit</NOBR> double-extended-precision, and
-<NOBR>128-bit</NOBR> quadruple-precision.
+<NOBR>128-bit</NOBR> quadruple-precision.
-For <NOBR>64-bit</NOBR> double-precision (<CODE>f64_sqrt</CODE>), the result
+For <NOBR>64-bit</NOBR> double-precision (<CODE>f64_sqrt</CODE>), the result
-could sometimes be off by <NOBR>1 unit</NOBR> in the last place
+could sometimes be off by <NOBR>1 unit</NOBR> in the last place
-(<NOBR>1 ulp</NOBR>) from what it should be.
+(<NOBR>1 ulp</NOBR>) from what it should be.
-For the larger formats, the square root could be wrong in a large portion of
+For the larger formats, the square root could be wrong in a large portion of
-the less-significant bits.
+the less-significant bits.
-(A bug in <CODE>f128_sqrt</CODE> was first reported by Alexei Sibidanov.)
+(A bug in <CODE>f128_sqrt</CODE> was first reported by Alexei Sibidanov.)
-
+
-</UL>
+</UL>
-
+
-
+
-<H3>Release 3c (2017 February)</H3>
+<H3>Release 3c (2017 February)</H3>
-
+
-<UL>
+<UL>
-
+
-<LI>
+<LI>
-Added optional rounding mode <CODE>odd</CODE> (round to odd, also known as
+Added optional rounding mode <CODE>odd</CODE> (round to odd, also known as
-<EM>jamming</EM>).
+<EM>jamming</EM>).
-
+
-<LI>
+<LI>
-Corrected the documentation concerning non-canonical representations in
+Corrected the documentation concerning non-canonical representations in
-<NOBR>80-bit</NOBR> double-extended-precision.
+<NOBR>80-bit</NOBR> double-extended-precision.
-
+
-</UL>
+</UL>
-
+
-
+
-<H3>Release 3b (2016 July)</H3>
+<H3>Release 3b (2016 July)</H3>
-
+
-<UL>
+<UL>
-
+
-<LI>
+<LI>
-Implemented the common <NOBR>16-bit</NOBR> &ldquo;half-precision&rdquo;
+Implemented the common <NOBR>16-bit</NOBR> &ldquo;half-precision&rdquo;
-floating-point format (<CODE>float16_t</CODE>).
+floating-point format (<CODE>float16_t</CODE>).
-
+
-<LI>
+<LI>
-Made the integer values returned on invalid conversions to integer formats
+Made the integer values returned on invalid conversions to integer formats
-be determined by the port-specific specialization instead of being the same for
+be determined by the port-specific specialization instead of being the same for
-all ports.
+all ports.
-
+
-<LI>
+<LI>
-Added preprocessor macro <CODE>THREAD_LOCAL</CODE> to allow the floating-point
+Added preprocessor macro <CODE>THREAD_LOCAL</CODE> to allow the floating-point
-state (modes and exception flags) to be made per-thread.
+state (modes and exception flags) to be made per-thread.
-
+
-<LI>
+<LI>
-Modified the provided Makefiles to allow some options to be overridden from the
+Modified the provided Makefiles to allow some options to be overridden from the
-<CODE>make</CODE> command.
+<CODE>make</CODE> command.
-
+
-<LI>
+<LI>
-Made other minor improvements.
+Made other minor improvements.
-
+
-</UL>
+</UL>
-
+
-
+
-<H3>Release 3a (2015 October)</H3>
+<H3>Release 3a (2015 October)</H3>
-
+
-<UL>
+<UL>
-
+
-<LI>
+<LI>
-Replaced the license text supplied by the University of California, Berkeley.
+Replaced the license text supplied by the University of California, Berkeley.
-
+
-</UL>
+</UL>
-
+
-
+
-<H3>Release 3 (2015 February)</H3>
+<H3>Release 3 (2015 February)</H3>
-
+
-<UL>
+<UL>
-
+
-<LI>
+<LI>
-Complete rewrite, funded by the University of California, Berkeley, and
+Complete rewrite, funded by the University of California, Berkeley, and
-consequently having a different use license than earlier releases.
+consequently having a different use license than earlier releases.
-Major changes included renaming most types and functions, upgrading some
+Major changes included renaming most types and functions, upgrading some
-algorithms, restructuring the source files, and making SoftFloat into a true
+algorithms, restructuring the source files, and making SoftFloat into a true
-library.
+library.
-
+
-<LI>
+<LI>
-Added functions to convert between floating-point and unsigned integers, both
+Added functions to convert between floating-point and unsigned integers, both
-<NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR> (<CODE>uint32_t</CODE> and
+<NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR> (<CODE>uint32_t</CODE> and
-<CODE>uint64_t</CODE>).
+<CODE>uint64_t</CODE>).
-
+
-<LI>
+<LI>
-Added functions for fused multiply-add, for all supported floating-point
+Added functions for fused multiply-add, for all supported floating-point
-formats except <NOBR>80-bit</NOBR> double-extended-precision.
+formats except <NOBR>80-bit</NOBR> double-extended-precision.
-
+
-<LI>
+<LI>
-Added support for a fifth rounding mode, <CODE>near_maxMag</CODE> (round to
+Added support for a fifth rounding mode, <CODE>near_maxMag</CODE> (round to
-nearest, with ties to maximum magnitude, away from zero).
+nearest, with ties to maximum magnitude, away from zero).
-
+
-<LI>
+<LI>
-Dropped the <CODE>timesoftfloat</CODE> program (now part of the Berkeley
+Dropped the <CODE>timesoftfloat</CODE> program (now part of the Berkeley
-TestFloat package).
+TestFloat package).
-
+
-</UL>
+</UL>
-
+
-
+
-<H3>Release 2c (2015 January)</H3>
+<H3>Release 2c (2015 January)</H3>
-
+
-<UL>
+<UL>
-
+
-<LI>
+<LI>
-Fixed mistakes affecting some <NOBR>64-bit</NOBR> processors.
+Fixed mistakes affecting some <NOBR>64-bit</NOBR> processors.
-
+
-<LI>
+<LI>
-Further improved the documentation and the wording for the legal restrictions
+Further improved the documentation and the wording for the legal restrictions
-on using SoftFloat releases <NOBR>through 2c</NOBR> (not applicable to
+on using SoftFloat releases <NOBR>through 2c</NOBR> (not applicable to
-<NOBR>Release 3</NOBR> or later).
+<NOBR>Release 3</NOBR> or later).
-
+
-</UL>
+</UL>
-
+
-
+
-<H3>Release 2b (2002 May)</H3>
+<H3>Release 2b (2002 May)</H3>
-
+
-<UL>
+<UL>
-
+
-<LI>
+<LI>
-Made minor updates to the documentation, including improved wording for the
+Made minor updates to the documentation, including improved wording for the
-legal restrictions on using SoftFloat.
+legal restrictions on using SoftFloat.
-
+
-</UL>
+</UL>
-
+
-
+
-<H3>Release 2a (1998 December)</H3>
+<H3>Release 2a (1998 December)</H3>
-
+
-<UL>
+<UL>
-
+
-<LI>
+<LI>
-Added functions to convert between <NOBR>64-bit</NOBR> integers
+Added functions to convert between <NOBR>64-bit</NOBR> integers
-(<CODE>int64</CODE>) and all supported floating-point formats.
+(<CODE>int64</CODE>) and all supported floating-point formats.
-
+
-<LI>
+<LI>
-Fixed a bug in all <NOBR>64-bit</NOBR>-version square root functions except
+Fixed a bug in all <NOBR>64-bit</NOBR>-version square root functions except
-<CODE>float32_sqrt</CODE> that caused the result sometimes to be off by
+<CODE>float32_sqrt</CODE> that caused the result sometimes to be off by
-<NOBR>1 unit</NOBR> in the last place (<NOBR>1 ulp</NOBR>) from what it should
+<NOBR>1 unit</NOBR> in the last place (<NOBR>1 ulp</NOBR>) from what it should
-be.
+be.
-(Bug discovered by Paul Donahue.)
+(Bug discovered by Paul Donahue.)
-
+
-<LI>
+<LI>
-Improved the Makefiles.
+Improved the Makefiles.
-</UL>
+</UL>
-
+
-
+
-<H3>Release 2 (1997 June)</H3>
+<H3>Release 2 (1997 June)</H3>
-
+
-<UL>
+<UL>
-
+
-<LI>
+<LI>
-Created the <NOBR>64-bit</NOBR> (<CODE>bits64</CODE>) version, adding the
+Created the <NOBR>64-bit</NOBR> (<CODE>bits64</CODE>) version, adding the
-<CODE>floatx80</CODE> and <CODE>float128</CODE> formats.
+<CODE>floatx80</CODE> and <CODE>float128</CODE> formats.
-
+
-<LI>
+<LI>
-Changed the source directory structure, splitting the sources into a
+Changed the source directory structure, splitting the sources into a
-<CODE>bits32</CODE> and a <CODE>bits64</CODE> version.
+<CODE>bits32</CODE> and a <CODE>bits64</CODE> version.
-Renamed <CODE>environment.h</CODE> to <CODE>milieu.h</CODE> to avoid confusion
+Renamed <CODE>environment.h</CODE> to <CODE>milieu.h</CODE> to avoid confusion
-with environment variables.
+with environment variables.
-
+
-<LI>
+<LI>
-Fixed a small error that caused <CODE>float64_round_to_int</CODE> often to
+Fixed a small error that caused <CODE>float64_round_to_int</CODE> often to
-round the wrong way in nearest/even mode when the operand was between
+round the wrong way in nearest/even mode when the operand was between
-2<SUP>20</SUP> and 2<SUP>21</SUP> and halfway between two integers.
+2<SUP>20</SUP> and 2<SUP>21</SUP> and halfway between two integers.
-
+
-</UL>
+</UL>
-
+
-
+
-<H3>Release 1a (1996 July)</H3>
+<H3>Release 1a (1996 July)</H3>
-
+
-<UL>
+<UL>
-
+
-<LI>
+<LI>
-Corrected a mistake that caused borderline underflow cases not to raise the
+Corrected a mistake that caused borderline underflow cases not to raise the
-underflow flag when they should have.
+underflow flag when they should have.
-(Problem reported by Doug Priest.)
+(Problem reported by Doug Priest.)
-
+
-<LI>
+<LI>
-Added the <CODE>float_detect_tininess</CODE> variable to control whether
+Added the <CODE>float_detect_tininess</CODE> variable to control whether
-tininess is detected before or after rounding.
+tininess is detected before or after rounding.
-
+
-</UL>
+</UL>
-
+
-
+
-<H3>Release 1 (1996 July)</H3>
+<H3>Release 1 (1996 July)</H3>
-
+
-<UL>
+<UL>
-
+
-<LI>
+<LI>
-Original release, based on work done for the International Computer Science
+Original release, based on work done for the International Computer Science
-Institute (ICSI) in Berkeley, California.
+Institute (ICSI) in Berkeley, California.
-
+
-</UL>
+</UL>
-
+
-
+
-</BODY>
+</BODY>
-
+

softfloat/source/8086-SSE/extF80M_isSignalingNaN.c

@@ -1,57 +1,57 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdbool.h>
+#include <stdbool.h>
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "softfloat.h"
+#include "softfloat.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-bool extF80M_isSignalingNaN( const extFloat80_t *aPtr )
+bool extF80M_isSignalingNaN( const extFloat80_t *aPtr )
-{
+{
-    const struct extFloat80M *aSPtr;
+    const struct extFloat80M *aSPtr;
-    uint64_t uiA0;
+    uint64_t uiA0;
-
+
-    aSPtr = (const struct extFloat80M *) aPtr;
+    aSPtr = (const struct extFloat80M *) aPtr;
-    if ( (aSPtr->signExp & 0x7FFF) != 0x7FFF ) return false;
+    if ( (aSPtr->signExp & 0x7FFF) != 0x7FFF ) return false;
-    uiA0 = aSPtr->signif;
+    uiA0 = aSPtr->signif;
-    return
+    return
-        ! (uiA0 & UINT64_C( 0x4000000000000000 ))
+        ! (uiA0 & UINT64_C( 0x4000000000000000 ))
-            && (uiA0 & UINT64_C( 0x3FFFFFFFFFFFFFFF));
+            && (uiA0 & UINT64_C( 0x3FFFFFFFFFFFFFFF));
-
+
-}
+}
-
+

softfloat/source/8086-SSE/f128M_isSignalingNaN.c

@@ -1,60 +1,60 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdbool.h>
+#include <stdbool.h>
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "primitives.h"
+#include "primitives.h"
-#include "softfloat.h"
+#include "softfloat.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-bool f128M_isSignalingNaN( const float128_t *aPtr )
+bool f128M_isSignalingNaN( const float128_t *aPtr )
-{
+{
-    const uint32_t *aWPtr;
+    const uint32_t *aWPtr;
-    uint32_t uiA96;
+    uint32_t uiA96;
-
+
-    aWPtr = (const uint32_t *) aPtr;
+    aWPtr = (const uint32_t *) aPtr;
-    uiA96 = aWPtr[indexWordHi( 4 )];
+    uiA96 = aWPtr[indexWordHi( 4 )];
-    if ( (uiA96 & 0x7FFF8000) != 0x7FFF0000 ) return false;
+    if ( (uiA96 & 0x7FFF8000) != 0x7FFF0000 ) return false;
-    return
+    return
-        ((uiA96 & 0x00007FFF) != 0)
+        ((uiA96 & 0x00007FFF) != 0)
-            || ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
+            || ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
-                     | aWPtr[indexWord( 4, 0 )])
+                     | aWPtr[indexWord( 4, 0 )])
-                    != 0);
+                    != 0);
-
+
-}
+}
-
+

softfloat/source/8086-SSE/s_bf16UIToCommonNaN.c

@@ -1,59 +0,0 @@
-
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-/*----------------------------------------------------------------------------
-| Assuming `uiA' has the bit pattern of a BF16 NaN, converts
-| this NaN to the common NaN form, and stores the resulting common NaN at the
-| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
-| exception is raised.
-*----------------------------------------------------------------------------*/
-void softfloat_bf16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr )
-{
-
-    if ( softfloat_isSigNaNBF16UI( uiA ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
-    zPtr->sign = uiA>>15;
-    zPtr->v64  = (uint_fast64_t) uiA<<56;
-    zPtr->v0   = 0;
-
-}
-

softfloat/source/8086-SSE/s_commonNaNToBF16UI.c

@@ -1,51 +0,0 @@
-
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-
-/*----------------------------------------------------------------------------
-| Converts the common NaN pointed to by `aPtr' into a BF16 NaN, and 
-| returns the bit pattern of this value as an unsigned integer.
-*----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_commonNaNToBF16UI( const struct commonNaN *aPtr )
-{
-
-    return (uint_fast16_t) aPtr->sign<<15 | 0x7FC0 | aPtr->v64>>56;
-
-}
-

softfloat/source/8086-SSE/s_commonNaNToExtF80M.c

@@ -1,56 +1,56 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "internals.h"
+#include "internals.h"
-#include "specialize.h"
+#include "specialize.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-| Converts the common NaN pointed to by `aPtr' into an 80-bit extended
+| Converts the common NaN pointed to by `aPtr' into an 80-bit extended
-| floating-point NaN, and stores this NaN at the location pointed to by
+| floating-point NaN, and stores this NaN at the location pointed to by
-| `zSPtr'.
+| `zSPtr'.
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-void
+void
- softfloat_commonNaNToExtF80M(
+ softfloat_commonNaNToExtF80M(
-     const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
-{
+{
-
+
-    zSPtr->signExp = packToExtF80UI64( aPtr->sign, 0x7FFF );
+    zSPtr->signExp = packToExtF80UI64( aPtr->sign, 0x7FFF );
-    zSPtr->signif = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
+    zSPtr->signif = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
-
+
-}
+}
-
+

softfloat/source/8086-SSE/s_commonNaNToExtF80UI.c

@@ -1,56 +1,56 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "primitives.h"
+#include "primitives.h"
-#include "specialize.h"
+#include "specialize.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-| Converts the common NaN pointed to by `aPtr' into an 80-bit extended
+| Converts the common NaN pointed to by `aPtr' into an 80-bit extended
-| floating-point NaN, and returns the bit pattern of this value as an unsigned
+| floating-point NaN, and returns the bit pattern of this value as an unsigned
-| integer.
+| integer.
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
+struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
-{
+{
-    struct uint128 uiZ;
+    struct uint128 uiZ;
-
+
-    uiZ.v64 = (uint_fast16_t) aPtr->sign<<15 | 0x7FFF;
+    uiZ.v64 = (uint_fast16_t) aPtr->sign<<15 | 0x7FFF;
-    uiZ.v0 = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
+    uiZ.v0 = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
-    return uiZ;
+    return uiZ;
-
+
-}
+}
-
+

softfloat/source/8086-SSE/s_commonNaNToF128M.c

@@ -1,56 +1,56 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "primitives.h"
+#include "primitives.h"
-#include "specialize.h"
+#include "specialize.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point
+| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point
-| NaN, and stores this NaN at the location pointed to by `zWPtr'.  Argument
+| NaN, and stores this NaN at the location pointed to by `zWPtr'.  Argument
-| `zWPtr' points to an array of four 32-bit elements that concatenate in the
+| `zWPtr' points to an array of four 32-bit elements that concatenate in the
-| platform's normal endian order to form a 128-bit floating-point value.
+| platform's normal endian order to form a 128-bit floating-point value.
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-void
+void
- softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
-{
+{
-
+
-    softfloat_shortShiftRight128M( (const uint32_t *) &aPtr->v0, 16, zWPtr );
+    softfloat_shortShiftRight128M( (const uint32_t *) &aPtr->v0, 16, zWPtr );
-    zWPtr[indexWordHi( 4 )] |= (uint32_t) aPtr->sign<<31 | 0x7FFF8000;
+    zWPtr[indexWordHi( 4 )] |= (uint32_t) aPtr->sign<<31 | 0x7FFF8000;
-
+
-}
+}
-
+

softfloat/source/8086-SSE/s_commonNaNToF128UI.c

@@ -1,55 +1,55 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "primitives.h"
+#include "primitives.h"
-#include "specialize.h"
+#include "specialize.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point
+| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point
-| NaN, and returns the bit pattern of this value as an unsigned integer.
+| NaN, and returns the bit pattern of this value as an unsigned integer.
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
+struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
-{
+{
-    struct uint128 uiZ;
+    struct uint128 uiZ;
-
+
-    uiZ = softfloat_shortShiftRight128( aPtr->v64, aPtr->v0, 16 );
+    uiZ = softfloat_shortShiftRight128( aPtr->v64, aPtr->v0, 16 );
-    uiZ.v64 |= (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FFF800000000000 );
+    uiZ.v64 |= (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FFF800000000000 );
-    return uiZ;
+    return uiZ;
-
+
-}
+}
-
+

softfloat/source/8086-SSE/s_commonNaNToF16UI.c

@@ -1,51 +1,51 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
-California.  All rights reserved.
+California.  All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "specialize.h"
+#include "specialize.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-| Converts the common NaN pointed to by `aPtr' into a 16-bit floating-point
+| Converts the common NaN pointed to by `aPtr' into a 16-bit floating-point
-| NaN, and returns the bit pattern of this value as an unsigned integer.
+| NaN, and returns the bit pattern of this value as an unsigned integer.
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr )
+uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr )
-{
+{
-
+
-    return (uint_fast16_t) aPtr->sign<<15 | 0x7E00 | aPtr->v64>>54;
+    return (uint_fast16_t) aPtr->sign<<15 | 0x7E00 | aPtr->v64>>54;
-
+
-}
+}
-
+

softfloat/source/8086-SSE/s_commonNaNToF32UI.c

@@ -1,51 +1,51 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "specialize.h"
+#include "specialize.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-| Converts the common NaN pointed to by `aPtr' into a 32-bit floating-point
+| Converts the common NaN pointed to by `aPtr' into a 32-bit floating-point
-| NaN, and returns the bit pattern of this value as an unsigned integer.
+| NaN, and returns the bit pattern of this value as an unsigned integer.
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr )
+uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr )
-{
+{
-
+
-    return (uint_fast32_t) aPtr->sign<<31 | 0x7FC00000 | aPtr->v64>>41;
+    return (uint_fast32_t) aPtr->sign<<31 | 0x7FC00000 | aPtr->v64>>41;
-
+
-}
+}
-
+

softfloat/source/8086-SSE/s_commonNaNToF64UI.c

@@ -1,53 +1,53 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "specialize.h"
+#include "specialize.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-| Converts the common NaN pointed to by `aPtr' into a 64-bit floating-point
+| Converts the common NaN pointed to by `aPtr' into a 64-bit floating-point
-| NaN, and returns the bit pattern of this value as an unsigned integer.
+| NaN, and returns the bit pattern of this value as an unsigned integer.
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr )
+uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr )
-{
+{
-
+
-    return
+    return
-        (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FF8000000000000 )
+        (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FF8000000000000 )
-            | aPtr->v64>>12;
+            | aPtr->v64>>12;
-
+
-}
+}
-
+

softfloat/source/8086-SSE/s_extF80MToCommonNaN.c

@@ -1,62 +1,62 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "internals.h"
+#include "internals.h"
-#include "specialize.h"
+#include "specialize.h"
-#include "softfloat.h"
+#include "softfloat.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-| Assuming the 80-bit extended floating-point value pointed to by `aSPtr' is
+| Assuming the 80-bit extended floating-point value pointed to by `aSPtr' is
-| a NaN, converts this NaN to the common NaN form, and stores the resulting
+| a NaN, converts this NaN to the common NaN form, and stores the resulting
-| common NaN at the location pointed to by `zPtr'.  If the NaN is a signaling
+| common NaN at the location pointed to by `zPtr'.  If the NaN is a signaling
-| NaN, the invalid exception is raised.
+| NaN, the invalid exception is raised.
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-void
+void
- softfloat_extF80MToCommonNaN(
+ softfloat_extF80MToCommonNaN(
-     const struct extFloat80M *aSPtr, struct commonNaN *zPtr )
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr )
-{
+{
-
+
-    if ( extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr ) ) {
+    if ( extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
+    }
-    zPtr->sign = signExtF80UI64( aSPtr->signExp );
+    zPtr->sign = signExtF80UI64( aSPtr->signExp );
-    zPtr->v64 = aSPtr->signif<<1;
+    zPtr->v64 = aSPtr->signif<<1;
-    zPtr->v0  = 0;
+    zPtr->v0  = 0;
-
+
-}
+}
-
+

softfloat/source/8086-SSE/s_extF80UIToCommonNaN.c

@@ -1,62 +1,62 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "specialize.h"
+#include "specialize.h"
-#include "softfloat.h"
+#include "softfloat.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0'
+| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0'
-| has the bit pattern of an 80-bit extended floating-point NaN, converts
+| has the bit pattern of an 80-bit extended floating-point NaN, converts
-| this NaN to the common NaN form, and stores the resulting common NaN at the
+| this NaN to the common NaN form, and stores the resulting common NaN at the
-| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
-| exception is raised.
+| exception is raised.
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-void
+void
- softfloat_extF80UIToCommonNaN(
+ softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
-{
+{
-
+
-    if ( softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ) {
+    if ( softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
+    }
-    zPtr->sign = uiA64>>15;
+    zPtr->sign = uiA64>>15;
-    zPtr->v64  = uiA0<<1;
+    zPtr->v64  = uiA0<<1;
-    zPtr->v0   = 0;
+    zPtr->v0   = 0;
-
+
-}
+}
-
+

softfloat/source/8086-SSE/s_f128MToCommonNaN.c

@@ -1,62 +1,62 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "primitives.h"
+#include "primitives.h"
-#include "specialize.h"
+#include "specialize.h"
-#include "softfloat.h"
+#include "softfloat.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-| Assuming the 128-bit floating-point value pointed to by `aWPtr' is a NaN,
+| Assuming the 128-bit floating-point value pointed to by `aWPtr' is a NaN,
-| converts this NaN to the common NaN form, and stores the resulting common
+| converts this NaN to the common NaN form, and stores the resulting common
-| NaN at the location pointed to by `zPtr'.  If the NaN is a signaling NaN,
+| NaN at the location pointed to by `zPtr'.  If the NaN is a signaling NaN,
-| the invalid exception is raised.  Argument `aWPtr' points to an array of
+| the invalid exception is raised.  Argument `aWPtr' points to an array of
-| four 32-bit elements that concatenate in the platform's normal endian order
+| four 32-bit elements that concatenate in the platform's normal endian order
-| to form a 128-bit floating-point value.
+| to form a 128-bit floating-point value.
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-void
+void
- softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr )
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr )
-{
+{
-
+
-    if ( f128M_isSignalingNaN( (const float128_t *) aWPtr ) ) {
+    if ( f128M_isSignalingNaN( (const float128_t *) aWPtr ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
+    }
-    zPtr->sign = aWPtr[indexWordHi( 4 )]>>31;
+    zPtr->sign = aWPtr[indexWordHi( 4 )]>>31;
-    softfloat_shortShiftLeft128M( aWPtr, 16, (uint32_t *) &zPtr->v0 );
+    softfloat_shortShiftLeft128M( aWPtr, 16, (uint32_t *) &zPtr->v0 );
-
+
-}
+}
-
+

softfloat/source/8086-SSE/s_f128UIToCommonNaN.c

@@ -1,65 +1,65 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "primitives.h"
+#include "primitives.h"
-#include "specialize.h"
+#include "specialize.h"
-#include "softfloat.h"
+#include "softfloat.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0'
+| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0'
-| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to
+| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to
-| the common NaN form, and stores the resulting common NaN at the location
+| the common NaN form, and stores the resulting common NaN at the location
-| pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid exception
+| pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid exception
-| is raised.
+| is raised.
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-void
+void
- softfloat_f128UIToCommonNaN(
+ softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
-{
+{
-    struct uint128 NaNSig;
+    struct uint128 NaNSig;
-
+
-    if ( softfloat_isSigNaNF128UI( uiA64, uiA0 ) ) {
+    if ( softfloat_isSigNaNF128UI( uiA64, uiA0 ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
+    }
-    NaNSig = softfloat_shortShiftLeft128( uiA64, uiA0, 16 );
+    NaNSig = softfloat_shortShiftLeft128( uiA64, uiA0, 16 );
-    zPtr->sign = uiA64>>63;
+    zPtr->sign = uiA64>>63;
-    zPtr->v64  = NaNSig.v64;
+    zPtr->v64  = NaNSig.v64;
-    zPtr->v0   = NaNSig.v0;
+    zPtr->v0   = NaNSig.v0;
-
+
-}
+}
-
+

softfloat/source/8086-SSE/s_f16UIToCommonNaN.c

@@ -1,59 +1,59 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
-California.  All rights reserved.
+California.  All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "specialize.h"
+#include "specialize.h"
-#include "softfloat.h"
+#include "softfloat.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-| Assuming `uiA' has the bit pattern of a 16-bit floating-point NaN, converts
+| Assuming `uiA' has the bit pattern of a 16-bit floating-point NaN, converts
-| this NaN to the common NaN form, and stores the resulting common NaN at the
+| this NaN to the common NaN form, and stores the resulting common NaN at the
-| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
-| exception is raised.
+| exception is raised.
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr )
+void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr )
-{
+{
-
+
-    if ( softfloat_isSigNaNF16UI( uiA ) ) {
+    if ( softfloat_isSigNaNF16UI( uiA ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
+    }
-    zPtr->sign = uiA>>15;
+    zPtr->sign = uiA>>15;
-    zPtr->v64  = (uint_fast64_t) uiA<<54;
+    zPtr->v64  = (uint_fast64_t) uiA<<54;
-    zPtr->v0   = 0;
+    zPtr->v0   = 0;
-
+
-}
+}
-
+

softfloat/source/8086-SSE/s_f32UIToCommonNaN.c

@@ -1,59 +1,59 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "specialize.h"
+#include "specialize.h"
-#include "softfloat.h"
+#include "softfloat.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-| Assuming `uiA' has the bit pattern of a 32-bit floating-point NaN, converts
+| Assuming `uiA' has the bit pattern of a 32-bit floating-point NaN, converts
-| this NaN to the common NaN form, and stores the resulting common NaN at the
+| this NaN to the common NaN form, and stores the resulting common NaN at the
-| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
-| exception is raised.
+| exception is raised.
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr )
+void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr )
-{
+{
-
+
-    if ( softfloat_isSigNaNF32UI( uiA ) ) {
+    if ( softfloat_isSigNaNF32UI( uiA ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
+    }
-    zPtr->sign = uiA>>31;
+    zPtr->sign = uiA>>31;
-    zPtr->v64  = (uint_fast64_t) uiA<<41;
+    zPtr->v64  = (uint_fast64_t) uiA<<41;
-    zPtr->v0   = 0;
+    zPtr->v0   = 0;
-
+
-}
+}
-
+

softfloat/source/8086-SSE/s_f64UIToCommonNaN.c

@@ -1,59 +1,59 @@
-
+
-/*============================================================================
+/*============================================================================
-
+
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
+Package, Release 3e, by John R. Hauser.
-
+
-Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
-All rights reserved.
+All rights reserved.
-
+
-Redistribution and use in source and binary forms, with or without
+Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
+modification, are permitted provided that the following conditions are met:
-
+
- 1. Redistributions of source code must retain the above copyright notice,
+ 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
+    this list of conditions, and the following disclaimer.
-
+
- 2. Redistributions in binary form must reproduce the above copyright notice,
+ 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
+    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
+    and/or other materials provided with the distribution.
-
+
- 3. Neither the name of the University nor the names of its contributors may
+ 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
+    be used to endorse or promote products derived from this software without
-    specific prior written permission.
+    specific prior written permission.
-
+
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+
-=============================================================================*/
+=============================================================================*/
-
+
-#include <stdint.h>
+#include <stdint.h>
-#include "platform.h"
+#include "platform.h"
-#include "specialize.h"
+#include "specialize.h"
-#include "softfloat.h"
+#include "softfloat.h"
-
+
-/*----------------------------------------------------------------------------
+/*----------------------------------------------------------------------------
-| Assuming `uiA' has the bit pattern of a 64-bit floating-point NaN, converts
+| Assuming `uiA' has the bit pattern of a 64-bit floating-point NaN, converts
-| this NaN to the common NaN form, and stores the resulting common NaN at the
+| this NaN to the common NaN form, and stores the resulting common NaN at the
-| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
-| exception is raised.
+| exception is raised.
-*----------------------------------------------------------------------------*/
+*----------------------------------------------------------------------------*/
-void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr )
+void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr )
-{
+{
-
+
-    if ( softfloat_isSigNaNF64UI( uiA ) ) {
+    if ( softfloat_isSigNaNF64UI( uiA ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
+    }
-    zPtr->sign = uiA>>63;
+    zPtr->sign = uiA>>63;
-    zPtr->v64  = uiA<<12;
+    zPtr->v64  = uiA<<12;
-    zPtr->v0   = 0;
+    zPtr->v0   = 0;
-
+
-}
+}
-
+