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4aa26b85a0
...
hotfix/lat
| Author | SHA1 | Date | |
|---|---|---|---|
| 66dc28c239 | |||
| 40470445f4 | |||
| ea3ff3c0cd | |||
| c941890901 | |||
| b7c0fb2b1c |
@ -1,6 +1,6 @@
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cmake_minimum_required(VERSION 3.12)
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project("tgfs" VERSION 1.0.0)
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project("riscv" VERSION 1.0.0)
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include(GNUInstallDirs)
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@ -28,7 +28,7 @@ add_subdirectory(softfloat)
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# library files
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FILE(GLOB RiscVSCHeaders ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*.h ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*/*.h)
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set(LIB_HEADERS tgfscVSCHeaders} )
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set(LIB_HEADERS ${RiscVSCHeaders} )
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set(LIB_SOURCES
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src/iss/tgf_b.cpp
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src/iss/tgf_c.cpp
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@ -49,58 +49,56 @@ set(LIB_SOURCES ${LIB_SOURCES}
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endif()
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# Define the library
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add_library(tgfs SHARED ${LIB_SOURCES})
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# list code gen dependencies
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add_dependencies(tgfs TGF_C_src)
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target_compile_options(tgfs PRIVATE -Wno-shift-count-overflow)
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target_include_directories(tgfs PUBLIC incl)
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target_link_libraries(tgfs PUBLIC softfloat scc-util)
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target_link_libraries(tgfs PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
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target_link_libraries(tgfs PUBLIC ${Boost_LIBRARIES} )
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set_target_properties(tgfs PROPERTIES
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add_library(riscv SHARED ${LIB_SOURCES})
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target_compile_options(riscv PRIVATE -Wno-shift-count-overflow)
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target_include_directories(riscv PUBLIC incl ../external/elfio)
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target_link_libraries(riscv PUBLIC softfloat scc-util jsoncpp)
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target_link_libraries(riscv PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
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set_target_properties(riscv PROPERTIES
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VERSION ${PROJECT_VERSION}
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FRAMEWORK FALSE
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PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
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)
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if(SystemC_FOUND)
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add_library(tgfs_sc src/sysc/core_complex.cpp)
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target_compile_definitions(tgfs_sc PUBLIC WITH_SYSTEMC)
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target_include_directories(tgfs_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
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add_library(riscv_sc src/sysc/core_complex.cpp)
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target_compile_definitions(riscv_sc PUBLIC WITH_SYSTEMC)
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target_include_directories(riscv_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
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if(SCV_FOUND)
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target_compile_definitions(tgfs_sc PUBLIC WITH_SCV)
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target_include_directories(tgfs_sc PUBLIC ${SCV_INCLUDE_DIRS})
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target_compile_definitions(riscv_sc PUBLIC WITH_SCV)
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target_include_directories(riscv_sc PUBLIC ${SCV_INCLUDE_DIRS})
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endif()
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target_link_libraries(tgfs_sc PUBLIC tgfs scc )
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target_link_libraries(riscv_sc PUBLIC riscv scc )
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if(WITH_LLVM)
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target_link_libraries(tgfs_sc PUBLIC ${llvm_libs})
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target_link_libraries(riscv_sc PUBLIC ${llvm_libs})
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endif()
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set_target_properties(tgfs_sc PROPERTIES
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target_link_libraries(riscv_sc PUBLIC ${Boost_LIBRARIES} )
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set_target_properties(riscv_sc PROPERTIES
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VERSION ${PROJECT_VERSION}
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FRAMEWORK FALSE
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PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
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)
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endif()
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project("tgfs-sim")
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add_executable(tgfs-sim src/main.cpp)
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project("riscv-sim")
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add_executable(riscv-sim src/main.cpp)
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# This sets the include directory for the reference project. This is the -I flag in gcc.
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target_include_directories(riscv-sim PRIVATE ../external/libGIS)
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if(WITH_LLVM)
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target_compile_definitions(tgfs-sim PRIVATE WITH_LLVM)
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target_link_libraries(tgfs-sim PUBLIC ${llvm_libs})
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target_compile_definitions(riscv-sim PRIVATE WITH_LLVM)
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target_link_libraries(riscv-sim PUBLIC ${llvm_libs})
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endif()
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# Links the target exe against the libraries
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target_link_libraries(tgfs-sim tgfs)
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target_link_libraries(tgfs-sim jsoncpp)
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target_link_libraries(tgfs-sim ${Boost_LIBRARIES} )
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target_link_libraries(riscv-sim riscv)
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target_link_libraries(riscv-sim jsoncpp)
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target_link_libraries(riscv-sim external)
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target_link_libraries(riscv-sim ${Boost_LIBRARIES} )
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if (Tcmalloc_FOUND)
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target_link_libraries(tgfs-sim ${Tcmalloc_LIBRARIES})
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target_link_libraries(riscv-sim ${Tcmalloc_LIBRARIES})
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endif(Tcmalloc_FOUND)
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install(TARGETS tgfs tgfs-sim
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install(TARGETS riscv riscv-sim
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EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
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ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # static lib
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RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} COMPONENT libs # binaries
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@ -122,4 +120,4 @@ install(TARGETS tgfs tgfs-sim
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# CMAKE PACKAGING (for other CMake projects to use this one easily)
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# _____________________________________________________________________________
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#include(PackageConfigurator)
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#include(PackageConfigurator)
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Submodule gen_input/CoreDSL-Instruction-Set-Description updated: 89763fcb97...3bb3763e92
@ -3,25 +3,26 @@ import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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Core TGF_B provides RV32I {
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architectural_state {
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unsigned XLEN=32;
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unsigned PCLEN=32;
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constants {
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XLEN:=32;
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PCLEN:=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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unsigned MISA_VAL=0b01000000000000000000000100000000;
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unsigned PGSIZE = 0x1000; //1 << 12;
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unsigned PGMASK = 0xfff; //PGSIZE-1
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MISA_VAL:=0b01000000000000000000000100000000;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core TGF_C provides RV32I, RV32M, RV32IC {
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architectural_state {
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unsigned XLEN=32;
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unsigned PCLEN=32;
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constants {
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XLEN:=32;
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PCLEN:=32;
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MUL_LEN:=64;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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unsigned MISA_VAL=0b01000000000000000001000100000100;
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unsigned PGSIZE = 0x1000; //1 << 12;
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unsigned PGMASK = 0xfff; //PGSIZE-1
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MISA_VAL:=0b01000000000000000001000100000100;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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}
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74
gen_input/minres_rv.core_desc
Normal file
74
gen_input/minres_rv.core_desc
Normal file
@ -0,0 +1,74 @@
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import "RV32I.core_desc"
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import "RV64I.core_desc"
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import "RVM.core_desc"
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import "RVA.core_desc"
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import "RVC.core_desc"
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import "RVF.core_desc"
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import "RVD.core_desc"
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Core MNRV32 provides RV32I, RV32IC {
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constants {
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XLEN:=32;
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PCLEN:=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100000101;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
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constants {
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XLEN:=32;
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PCLEN:=32;
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MUL_LEN:=64;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100000101;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core RV32GC provides RV32I, RV32M, RV32A, RV32F, RV32D, RV32IC, RV32FC, RV32DC {
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constants {
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XLEN:=32;
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FLEN:=64;
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PCLEN:=32;
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MUL_LEN:=64;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100101101;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core RV64I provides RV64I {
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constants {
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XLEN:=64;
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PCLEN:=64;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b10000000000001000000000100000000;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV32FC, RV32DC, RV64IC {
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constants {
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XLEN:=64;
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FLEN:=64;
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PCLEN:=64;
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MUL_LEN:=128;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100101101;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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@ -1,5 +1,5 @@
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/*******************************************************************************
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* Copyright (C) 2017 - 2021 MINRES Technologies GmbH
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -29,30 +29,47 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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<%
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def nativeTypeSize(int size){
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if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
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<%
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import com.minres.coredsl.coreDsl.Register
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import com.minres.coredsl.coreDsl.RegisterFile
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import com.minres.coredsl.coreDsl.RegisterAlias
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def getTypeSize(size){
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if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
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}
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def getRegisterSizes(){
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def regs = registers.collect{nativeTypeSize(it.size)}
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regs+=[32,32, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT
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return regs
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}
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def getRegisterOffsets(){
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def offset = 0
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def offsets = []
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getRegisterSizes().each { size ->
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offsets<<offset
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offset+=size/8
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def getOriginalName(reg){
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if( reg.original instanceof RegisterFile) {
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if( reg.index != null ) {
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return reg.original.name+generator.generateHostCode(reg.index)
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} else {
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return reg.original.name
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}
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} else if(reg.original instanceof Register){
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return reg.original.name
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}
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return offsets
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}
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def byteSize(int size){
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if(size<=8) return 8;
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if(size<=16) return 16;
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if(size<=32) return 32;
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if(size<=64) return 64;
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return 128;
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def getRegisterNames(){
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def regNames = []
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allRegs.each { reg ->
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if( reg instanceof RegisterFile) {
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(reg.range.right..reg.range.left).each{
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regNames+=reg.name.toLowerCase()+it
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}
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} else if(reg instanceof Register){
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regNames+=reg.name.toLowerCase()
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}
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}
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return regNames
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}
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def getRegisterAliasNames(){
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def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
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return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
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if( reg instanceof RegisterFile) {
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return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
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} else if(reg instanceof Register){
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regMap[reg.name]?:reg.name.toLowerCase()
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}
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}.flatten()
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}
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%>
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#ifndef _${coreDef.name.toUpperCase()}_H_
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@ -70,26 +87,43 @@ struct ${coreDef.name.toLowerCase()};
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|
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template <> struct traits<${coreDef.name.toLowerCase()}> {
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|
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constexpr static char const* const core_type = "${coreDef.name}";
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constexpr static char const* const core_type = "${coreDef.name}";
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static constexpr std::array<const char*, ${registers.size}> reg_names{
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{"${registers.collect{it.name}.join('", "')}"}};
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static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
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{"${getRegisterNames().join("\", \"")}"}};
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|
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static constexpr std::array<const char*, ${registers.size}> reg_aliases{
|
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{"${registers.collect{it.alias}.join('", "')}"}};
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static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
|
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{"${getRegisterAliasNames().join("\", \"")}"}};
|
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|
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enum constants {${constants.collect{c -> c.name+"="+c.value}.join(', ')}};
|
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enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
|
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|
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constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
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constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
|
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|
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enum reg_e {
|
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${registers.collect{it.name}.join(', ')}, NUM_REGS,
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TRAP_STATE=NUM_REGS,
|
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enum reg_e {<%
|
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allRegs.each { reg ->
|
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if( reg instanceof RegisterFile) {
|
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(reg.range.right..reg.range.left).each{%>
|
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${reg.name}${it},<%
|
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}
|
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} else if(reg instanceof Register){ %>
|
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${reg.name},<%
|
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}
|
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}%>
|
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NUM_REGS,
|
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NEXT_${pc.name}=NUM_REGS,
|
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TRAP_STATE,
|
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PENDING_TRAP,
|
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ICOUNT
|
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MACHINE_STATE,
|
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LAST_BRANCH,
|
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ICOUNT<%
|
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allRegs.each { reg ->
|
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if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
|
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${reg.name} = ${aliasname}<%
|
||||
}
|
||||
}%>
|
||||
};
|
||||
|
||||
using reg_t = uint${addrDataWidth}_t;
|
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using reg_t = uint${regDataWidth}_t;
|
||||
|
||||
using addr_t = uint${addrDataWidth}_t;
|
||||
|
||||
@ -99,22 +133,17 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
|
||||
|
||||
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||
|
||||
static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
|
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{${getRegisterSizes().join(',')}}};
|
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static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
|
||||
{${regSizes.join(",")}}};
|
||||
|
||||
static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
|
||||
{${getRegisterOffsets().join(',')}}};
|
||||
static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
|
||||
{${regOffsets.join(",")}}};
|
||||
|
||||
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||
|
||||
enum sreg_flag_e { FLAGS };
|
||||
|
||||
enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
|
||||
|
||||
enum class opcode_e : unsigned short {<%instructions.eachWithIndex{instr, index -> %>
|
||||
${instr.instruction.name} = ${index},<%}%>
|
||||
MAX_OPCODE
|
||||
};
|
||||
enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
|
||||
};
|
||||
|
||||
struct ${coreDef.name.toLowerCase()}: public arch_if {
|
||||
@ -161,9 +190,16 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
|
||||
|
||||
protected:
|
||||
struct ${coreDef.name}_regs {<%
|
||||
registers.each { reg -> if(reg.size>0) {%>
|
||||
uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
|
||||
}}%>
|
||||
allRegs.each { reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
(reg.range.right..reg.range.left).each{%>
|
||||
uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
|
||||
}
|
||||
} else if(reg instanceof Register){ %>
|
||||
uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
|
||||
}
|
||||
}%>
|
||||
uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
|
||||
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
|
||||
uint64_t icount = 0;
|
||||
} reg;
|
||||
@ -172,13 +208,13 @@ protected:
|
||||
|
||||
uint64_t interrupt_sim=0;
|
||||
<%
|
||||
def fcsr = registers.find {it.name=='FCSR'}
|
||||
def fcsr = allRegs.find {it.name=='FCSR'}
|
||||
if(fcsr != null) {%>
|
||||
uint${fcsr.size}_t get_fcsr(){return reg.FCSR;}
|
||||
void set_fcsr(uint${fcsr.size}_t val){reg.FCSR = val;}
|
||||
uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
|
||||
void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}
|
||||
<%} else { %>
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
<%}%>
|
||||
};
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -29,12 +29,43 @@
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
<%
|
||||
def getRegisterSizes(){
|
||||
def regs = registers.collect{it.size}
|
||||
regs[-1]=64 // correct for NEXT_PC
|
||||
regs+=[32, 32, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT
|
||||
return regs
|
||||
<%
|
||||
import com.minres.coredsl.coreDsl.Register
|
||||
import com.minres.coredsl.coreDsl.RegisterFile
|
||||
import com.minres.coredsl.coreDsl.RegisterAlias
|
||||
def getOriginalName(reg){
|
||||
if( reg.original instanceof RegisterFile) {
|
||||
if( reg.index != null ) {
|
||||
return reg.original.name+generator.generateHostCode(reg.index)
|
||||
} else {
|
||||
return reg.original.name
|
||||
}
|
||||
} else if(reg.original instanceof Register){
|
||||
return reg.original.name
|
||||
}
|
||||
}
|
||||
def getRegisterNames(){
|
||||
def regNames = []
|
||||
allRegs.each { reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
(reg.range.right..reg.range.left).each{
|
||||
regNames+=reg.name.toLowerCase()+it
|
||||
}
|
||||
} else if(reg instanceof Register){
|
||||
regNames+=reg.name.toLowerCase()
|
||||
}
|
||||
}
|
||||
return regNames
|
||||
}
|
||||
def getRegisterAliasNames(){
|
||||
def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
|
||||
return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
|
||||
} else if(reg instanceof Register){
|
||||
regMap[reg.name]?:reg.name.toLowerCase()
|
||||
}
|
||||
}.flatten()
|
||||
}
|
||||
%>
|
||||
#include "util/ities.h"
|
||||
@ -46,10 +77,10 @@ def getRegisterSizes(){
|
||||
|
||||
using namespace iss::arch;
|
||||
|
||||
constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
|
||||
constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
|
||||
constexpr std::array<const char*, ${getRegisterNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
|
||||
constexpr std::array<const char*, ${getRegisterAliasNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
|
||||
|
||||
${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
|
||||
reg.icount = 0;
|
||||
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2021 MINRES Technologies GmbH
|
||||
* Copyright (C) 2020 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -56,14 +56,13 @@ using namespace iss::debugger;
|
||||
|
||||
template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
|
||||
public:
|
||||
using traits = arch::traits<ARCH>;
|
||||
using super = typename iss::interp::vm_base<ARCH>;
|
||||
using super = typename iss::interp::vm_base<ARCH>;
|
||||
using virt_addr_t = typename super::virt_addr_t;
|
||||
using phys_addr_t = typename super::phys_addr_t;
|
||||
using code_word_t = typename super::code_word_t;
|
||||
using addr_t = typename super::addr_t;
|
||||
using reg_t = typename traits::reg_t;
|
||||
using mem_type_e = typename traits::mem_type_e;
|
||||
using addr_t = typename super::addr_t;
|
||||
using reg_t = typename traits<ARCH>::reg_t;
|
||||
using iss::interp::vm_base<ARCH>::get_reg;
|
||||
|
||||
vm_impl();
|
||||
|
||||
@ -83,7 +82,7 @@ protected:
|
||||
using compile_ret_t = virt_addr_t;
|
||||
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
|
||||
|
||||
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
|
||||
inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
|
||||
|
||||
virt_addr_t execute_inst(virt_addr_t start, std::function<bool(void)> pred) override;
|
||||
|
||||
@ -139,32 +138,23 @@ protected:
|
||||
return lut_val;
|
||||
}
|
||||
|
||||
void raise(uint16_t trap_id, uint16_t cause){
|
||||
void raise_trap(uint16_t trap_id, uint16_t cause){
|
||||
auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
|
||||
this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val;
|
||||
this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
|
||||
this->template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE) = trap_val;
|
||||
this->template get_reg<uint32_t>(arch::traits<ARCH>::NEXT_PC) = std::numeric_limits<uint32_t>::max();
|
||||
}
|
||||
|
||||
void leave(unsigned lvl){
|
||||
void leave_trap(unsigned lvl){
|
||||
this->core.leave_trap(lvl);
|
||||
auto pc_val = super::template read_mem<reg_t>(traits::CSR, (lvl << 8) + 0x41);
|
||||
this->template get_reg<reg_t>(traits::NEXT_PC) = pc_val;
|
||||
auto pc_val = super::template read_mem<reg_t>(traits<ARCH>::CSR, (lvl << 8) + 0x41);
|
||||
this->template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc_val;
|
||||
this->template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
|
||||
}
|
||||
|
||||
void wait(unsigned type){
|
||||
this->core.wait_until(type);
|
||||
}
|
||||
|
||||
template<typename T>
|
||||
T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
|
||||
inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint8_t>(space, addr);}
|
||||
inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint16_t>(space, addr);}
|
||||
inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint32_t>(space, addr);}
|
||||
inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint64_t>(space, addr);}
|
||||
inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){super::write_mem(space, addr, data);}
|
||||
inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){super::write_mem(space, addr, data);}
|
||||
inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){super::write_mem(space, addr, data);}
|
||||
inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){super::write_mem(space, addr, data);}
|
||||
|
||||
private:
|
||||
/****************************************************************************
|
||||
@ -180,36 +170,13 @@ private:
|
||||
const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
|
||||
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
|
||||
/* instruction ${instr.instruction.name} */
|
||||
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
|
||||
{${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
|
||||
}};
|
||||
|
||||
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
|
||||
/* instruction ${idx}: ${instr.name} */
|
||||
compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
|
||||
// pre execution stuff
|
||||
this->do_sync(PRE_SYNC, ${idx});
|
||||
<%instr.fields.eachLine{%>${it}
|
||||
<%}%>if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
<%instr.disass.eachLine{%>${it}
|
||||
<%}%>
|
||||
}
|
||||
// prepare execution
|
||||
uint${addrDataWidth}_t* X = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
||||
uint${addrDataWidth}_t* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
||||
uint${addrDataWidth}_t* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
||||
*NEXT_PC = *PC + ${instr.length/8};
|
||||
// execute instruction
|
||||
<%instr.behavior.eachLine{%>${it}
|
||||
<%}%>// post execution stuff
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
|
||||
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
|
||||
// trap check
|
||||
if(trap_state!=0){
|
||||
super::core.enter_trap(trap_state, pc.val);
|
||||
}
|
||||
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
|
||||
return pc;
|
||||
compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){<%instr.code.eachLine{%>
|
||||
${it}<%}%>
|
||||
}
|
||||
<%}%>
|
||||
/****************************************************************************
|
||||
@ -245,7 +212,7 @@ template <typename ARCH>
|
||||
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t start, std::function<bool(void)> pred) {
|
||||
// we fetch at max 4 byte, alignment is 2
|
||||
enum {TRAP_ID=1<<16};
|
||||
const typename traits::addr_t upper_bits = ~traits::PGMASK;
|
||||
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
|
||||
code_word_t insn = 0;
|
||||
auto *const data = (uint8_t *)&insn;
|
||||
auto pc=start;
|
||||
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2021 MINRES Technologies GmbH
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -30,6 +30,7 @@
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifndef _TGF_B_H_
|
||||
#define _TGF_B_H_
|
||||
|
||||
@ -45,23 +46,91 @@ struct tgf_b;
|
||||
|
||||
template <> struct traits<tgf_b> {
|
||||
|
||||
constexpr static char const* const core_type = "TGF_B";
|
||||
constexpr static char const* const core_type = "TGF_B";
|
||||
|
||||
static constexpr std::array<const char*, 35> reg_names{
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
|
||||
static constexpr std::array<const char*, 33> reg_names{
|
||||
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
|
||||
|
||||
static constexpr std::array<const char*, 35> reg_aliases{
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
|
||||
static constexpr std::array<const char*, 33> reg_aliases{
|
||||
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
|
||||
|
||||
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000000000100000000, PGSIZE=0x1000, PGMASK=0xfff, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3};
|
||||
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000000000100000000, PGSIZE=0x1000, PGMASK=0xfff};
|
||||
|
||||
constexpr static unsigned FP_REGS_SIZE = 0;
|
||||
|
||||
enum reg_e {
|
||||
X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, NUM_REGS,
|
||||
TRAP_STATE=NUM_REGS,
|
||||
X0,
|
||||
X1,
|
||||
X2,
|
||||
X3,
|
||||
X4,
|
||||
X5,
|
||||
X6,
|
||||
X7,
|
||||
X8,
|
||||
X9,
|
||||
X10,
|
||||
X11,
|
||||
X12,
|
||||
X13,
|
||||
X14,
|
||||
X15,
|
||||
X16,
|
||||
X17,
|
||||
X18,
|
||||
X19,
|
||||
X20,
|
||||
X21,
|
||||
X22,
|
||||
X23,
|
||||
X24,
|
||||
X25,
|
||||
X26,
|
||||
X27,
|
||||
X28,
|
||||
X29,
|
||||
X30,
|
||||
X31,
|
||||
PC,
|
||||
NUM_REGS,
|
||||
NEXT_PC=NUM_REGS,
|
||||
TRAP_STATE,
|
||||
PENDING_TRAP,
|
||||
ICOUNT
|
||||
MACHINE_STATE,
|
||||
LAST_BRANCH,
|
||||
ICOUNT,
|
||||
ZERO = X0,
|
||||
RA = X1,
|
||||
SP = X2,
|
||||
GP = X3,
|
||||
TP = X4,
|
||||
T0 = X5,
|
||||
T1 = X6,
|
||||
T2 = X7,
|
||||
S0 = X8,
|
||||
S1 = X9,
|
||||
A0 = X10,
|
||||
A1 = X11,
|
||||
A2 = X12,
|
||||
A3 = X13,
|
||||
A4 = X14,
|
||||
A5 = X15,
|
||||
A6 = X16,
|
||||
A7 = X17,
|
||||
S2 = X18,
|
||||
S3 = X19,
|
||||
S4 = X20,
|
||||
S5 = X21,
|
||||
S6 = X22,
|
||||
S7 = X23,
|
||||
S8 = X24,
|
||||
S9 = X25,
|
||||
S10 = X26,
|
||||
S11 = X27,
|
||||
T3 = X28,
|
||||
T4 = X29,
|
||||
T5 = X30,
|
||||
T6 = X31
|
||||
};
|
||||
|
||||
using reg_t = uint32_t;
|
||||
@ -74,73 +143,17 @@ template <> struct traits<tgf_b> {
|
||||
|
||||
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||
|
||||
static constexpr std::array<const uint32_t, 38> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64}};
|
||||
static constexpr std::array<const uint32_t, 39> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
|
||||
|
||||
static constexpr std::array<const uint32_t, 38> reg_byte_offsets{
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145}};
|
||||
static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
|
||||
|
||||
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||
|
||||
enum sreg_flag_e { FLAGS };
|
||||
|
||||
enum mem_type_e { MEM, CSR, FENCE, RES };
|
||||
|
||||
enum class opcode_e : unsigned short {
|
||||
LUI = 0,
|
||||
AUIPC = 1,
|
||||
JAL = 2,
|
||||
JALR = 3,
|
||||
BEQ = 4,
|
||||
BNE = 5,
|
||||
BLT = 6,
|
||||
BGE = 7,
|
||||
BLTU = 8,
|
||||
BGEU = 9,
|
||||
LB = 10,
|
||||
LH = 11,
|
||||
LW = 12,
|
||||
LBU = 13,
|
||||
LHU = 14,
|
||||
SB = 15,
|
||||
SH = 16,
|
||||
SW = 17,
|
||||
ADDI = 18,
|
||||
SLTI = 19,
|
||||
SLTIU = 20,
|
||||
XORI = 21,
|
||||
ORI = 22,
|
||||
ANDI = 23,
|
||||
SLLI = 24,
|
||||
SRLI = 25,
|
||||
SRAI = 26,
|
||||
ADD = 27,
|
||||
SUB = 28,
|
||||
SLL = 29,
|
||||
SLT = 30,
|
||||
SLTU = 31,
|
||||
XOR = 32,
|
||||
SRL = 33,
|
||||
SRA = 34,
|
||||
OR = 35,
|
||||
AND = 36,
|
||||
FENCE = 37,
|
||||
FENCE_I = 38,
|
||||
ECALL = 39,
|
||||
EBREAK = 40,
|
||||
URET = 41,
|
||||
SRET = 42,
|
||||
MRET = 43,
|
||||
WFI = 44,
|
||||
SFENCE_VMA = 45,
|
||||
CSRRW = 46,
|
||||
CSRRS = 47,
|
||||
CSRRC = 48,
|
||||
CSRRWI = 49,
|
||||
CSRRSI = 50,
|
||||
CSRRCI = 51,
|
||||
MAX_OPCODE
|
||||
};
|
||||
};
|
||||
|
||||
struct tgf_b: public arch_if {
|
||||
@ -186,42 +199,41 @@ struct tgf_b: public arch_if {
|
||||
inline uint32_t get_last_branch() { return reg.last_branch; }
|
||||
|
||||
protected:
|
||||
struct TGF_B_regs {
|
||||
uint32_t X0 = 0;
|
||||
uint32_t X1 = 0;
|
||||
uint32_t X2 = 0;
|
||||
uint32_t X3 = 0;
|
||||
uint32_t X4 = 0;
|
||||
uint32_t X5 = 0;
|
||||
uint32_t X6 = 0;
|
||||
uint32_t X7 = 0;
|
||||
uint32_t X8 = 0;
|
||||
uint32_t X9 = 0;
|
||||
uint32_t X10 = 0;
|
||||
uint32_t X11 = 0;
|
||||
uint32_t X12 = 0;
|
||||
uint32_t X13 = 0;
|
||||
uint32_t X14 = 0;
|
||||
uint32_t X15 = 0;
|
||||
uint32_t X16 = 0;
|
||||
uint32_t X17 = 0;
|
||||
uint32_t X18 = 0;
|
||||
uint32_t X19 = 0;
|
||||
uint32_t X20 = 0;
|
||||
uint32_t X21 = 0;
|
||||
uint32_t X22 = 0;
|
||||
uint32_t X23 = 0;
|
||||
uint32_t X24 = 0;
|
||||
uint32_t X25 = 0;
|
||||
uint32_t X26 = 0;
|
||||
uint32_t X27 = 0;
|
||||
uint32_t X28 = 0;
|
||||
uint32_t X29 = 0;
|
||||
uint32_t X30 = 0;
|
||||
uint32_t X31 = 0;
|
||||
uint32_t PC = 0;
|
||||
uint32_t NEXT_PC = 0;
|
||||
uint8_t PRIV = 0;
|
||||
struct TGF_B_regs {
|
||||
uint32_t X0 = 0;
|
||||
uint32_t X1 = 0;
|
||||
uint32_t X2 = 0;
|
||||
uint32_t X3 = 0;
|
||||
uint32_t X4 = 0;
|
||||
uint32_t X5 = 0;
|
||||
uint32_t X6 = 0;
|
||||
uint32_t X7 = 0;
|
||||
uint32_t X8 = 0;
|
||||
uint32_t X9 = 0;
|
||||
uint32_t X10 = 0;
|
||||
uint32_t X11 = 0;
|
||||
uint32_t X12 = 0;
|
||||
uint32_t X13 = 0;
|
||||
uint32_t X14 = 0;
|
||||
uint32_t X15 = 0;
|
||||
uint32_t X16 = 0;
|
||||
uint32_t X17 = 0;
|
||||
uint32_t X18 = 0;
|
||||
uint32_t X19 = 0;
|
||||
uint32_t X20 = 0;
|
||||
uint32_t X21 = 0;
|
||||
uint32_t X22 = 0;
|
||||
uint32_t X23 = 0;
|
||||
uint32_t X24 = 0;
|
||||
uint32_t X25 = 0;
|
||||
uint32_t X26 = 0;
|
||||
uint32_t X27 = 0;
|
||||
uint32_t X28 = 0;
|
||||
uint32_t X29 = 0;
|
||||
uint32_t X30 = 0;
|
||||
uint32_t X31 = 0;
|
||||
uint32_t PC = 0;
|
||||
uint32_t NEXT_PC = 0;
|
||||
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
|
||||
uint64_t icount = 0;
|
||||
} reg;
|
||||
@ -230,8 +242,8 @@ protected:
|
||||
|
||||
uint64_t interrupt_sim=0;
|
||||
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
|
||||
};
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2021 MINRES Technologies GmbH
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -30,6 +30,7 @@
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifndef _TGF_C_H_
|
||||
#define _TGF_C_H_
|
||||
|
||||
@ -45,23 +46,91 @@ struct tgf_c;
|
||||
|
||||
template <> struct traits<tgf_c> {
|
||||
|
||||
constexpr static char const* const core_type = "TGF_C";
|
||||
constexpr static char const* const core_type = "TGF_C";
|
||||
|
||||
static constexpr std::array<const char*, 35> reg_names{
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
|
||||
static constexpr std::array<const char*, 33> reg_names{
|
||||
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
|
||||
|
||||
static constexpr std::array<const char*, 35> reg_aliases{
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
|
||||
static constexpr std::array<const char*, 33> reg_aliases{
|
||||
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
|
||||
|
||||
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
|
||||
enum constants {XLEN=32, PCLEN=32, MUL_LEN=64, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff};
|
||||
|
||||
constexpr static unsigned FP_REGS_SIZE = 0;
|
||||
|
||||
enum reg_e {
|
||||
X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, NUM_REGS,
|
||||
TRAP_STATE=NUM_REGS,
|
||||
X0,
|
||||
X1,
|
||||
X2,
|
||||
X3,
|
||||
X4,
|
||||
X5,
|
||||
X6,
|
||||
X7,
|
||||
X8,
|
||||
X9,
|
||||
X10,
|
||||
X11,
|
||||
X12,
|
||||
X13,
|
||||
X14,
|
||||
X15,
|
||||
X16,
|
||||
X17,
|
||||
X18,
|
||||
X19,
|
||||
X20,
|
||||
X21,
|
||||
X22,
|
||||
X23,
|
||||
X24,
|
||||
X25,
|
||||
X26,
|
||||
X27,
|
||||
X28,
|
||||
X29,
|
||||
X30,
|
||||
X31,
|
||||
PC,
|
||||
NUM_REGS,
|
||||
NEXT_PC=NUM_REGS,
|
||||
TRAP_STATE,
|
||||
PENDING_TRAP,
|
||||
ICOUNT
|
||||
MACHINE_STATE,
|
||||
LAST_BRANCH,
|
||||
ICOUNT,
|
||||
ZERO = X0,
|
||||
RA = X1,
|
||||
SP = X2,
|
||||
GP = X3,
|
||||
TP = X4,
|
||||
T0 = X5,
|
||||
T1 = X6,
|
||||
T2 = X7,
|
||||
S0 = X8,
|
||||
S1 = X9,
|
||||
A0 = X10,
|
||||
A1 = X11,
|
||||
A2 = X12,
|
||||
A3 = X13,
|
||||
A4 = X14,
|
||||
A5 = X15,
|
||||
A6 = X16,
|
||||
A7 = X17,
|
||||
S2 = X18,
|
||||
S3 = X19,
|
||||
S4 = X20,
|
||||
S5 = X21,
|
||||
S6 = X22,
|
||||
S7 = X23,
|
||||
S8 = X24,
|
||||
S9 = X25,
|
||||
S10 = X26,
|
||||
S11 = X27,
|
||||
T3 = X28,
|
||||
T4 = X29,
|
||||
T5 = X30,
|
||||
T6 = X31
|
||||
};
|
||||
|
||||
using reg_t = uint32_t;
|
||||
@ -74,109 +143,17 @@ template <> struct traits<tgf_c> {
|
||||
|
||||
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||
|
||||
static constexpr std::array<const uint32_t, 38> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64}};
|
||||
static constexpr std::array<const uint32_t, 39> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
|
||||
|
||||
static constexpr std::array<const uint32_t, 38> reg_byte_offsets{
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145}};
|
||||
static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
|
||||
|
||||
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||
|
||||
enum sreg_flag_e { FLAGS };
|
||||
|
||||
enum mem_type_e { MEM, CSR, FENCE, RES };
|
||||
|
||||
enum class opcode_e : unsigned short {
|
||||
LUI = 0,
|
||||
AUIPC = 1,
|
||||
JAL = 2,
|
||||
JALR = 3,
|
||||
BEQ = 4,
|
||||
BNE = 5,
|
||||
BLT = 6,
|
||||
BGE = 7,
|
||||
BLTU = 8,
|
||||
BGEU = 9,
|
||||
LB = 10,
|
||||
LH = 11,
|
||||
LW = 12,
|
||||
LBU = 13,
|
||||
LHU = 14,
|
||||
SB = 15,
|
||||
SH = 16,
|
||||
SW = 17,
|
||||
ADDI = 18,
|
||||
SLTI = 19,
|
||||
SLTIU = 20,
|
||||
XORI = 21,
|
||||
ORI = 22,
|
||||
ANDI = 23,
|
||||
SLLI = 24,
|
||||
SRLI = 25,
|
||||
SRAI = 26,
|
||||
ADD = 27,
|
||||
SUB = 28,
|
||||
SLL = 29,
|
||||
SLT = 30,
|
||||
SLTU = 31,
|
||||
XOR = 32,
|
||||
SRL = 33,
|
||||
SRA = 34,
|
||||
OR = 35,
|
||||
AND = 36,
|
||||
FENCE = 37,
|
||||
FENCE_I = 38,
|
||||
ECALL = 39,
|
||||
EBREAK = 40,
|
||||
URET = 41,
|
||||
SRET = 42,
|
||||
MRET = 43,
|
||||
WFI = 44,
|
||||
SFENCE_VMA = 45,
|
||||
CSRRW = 46,
|
||||
CSRRS = 47,
|
||||
CSRRC = 48,
|
||||
CSRRWI = 49,
|
||||
CSRRSI = 50,
|
||||
CSRRCI = 51,
|
||||
MUL = 52,
|
||||
MULH = 53,
|
||||
MULHSU = 54,
|
||||
MULHU = 55,
|
||||
DIV = 56,
|
||||
DIVU = 57,
|
||||
REM = 58,
|
||||
REMU = 59,
|
||||
CADDI4SPN = 60,
|
||||
CLW = 61,
|
||||
CSW = 62,
|
||||
CADDI = 63,
|
||||
CNOP = 64,
|
||||
CJAL = 65,
|
||||
CLI = 66,
|
||||
CLUI = 67,
|
||||
CADDI16SP = 68,
|
||||
CSRLI = 69,
|
||||
CSRAI = 70,
|
||||
CANDI = 71,
|
||||
CSUB = 72,
|
||||
CXOR = 73,
|
||||
COR = 74,
|
||||
CAND = 75,
|
||||
CJ = 76,
|
||||
CBEQZ = 77,
|
||||
CBNEZ = 78,
|
||||
CSLLI = 79,
|
||||
CLWSP = 80,
|
||||
CMV = 81,
|
||||
CJR = 82,
|
||||
CADD = 83,
|
||||
CJALR = 84,
|
||||
CEBREAK = 85,
|
||||
CSWSP = 86,
|
||||
DII = 87,
|
||||
MAX_OPCODE
|
||||
};
|
||||
};
|
||||
|
||||
struct tgf_c: public arch_if {
|
||||
@ -222,42 +199,41 @@ struct tgf_c: public arch_if {
|
||||
inline uint32_t get_last_branch() { return reg.last_branch; }
|
||||
|
||||
protected:
|
||||
struct TGF_C_regs {
|
||||
uint32_t X0 = 0;
|
||||
uint32_t X1 = 0;
|
||||
uint32_t X2 = 0;
|
||||
uint32_t X3 = 0;
|
||||
uint32_t X4 = 0;
|
||||
uint32_t X5 = 0;
|
||||
uint32_t X6 = 0;
|
||||
uint32_t X7 = 0;
|
||||
uint32_t X8 = 0;
|
||||
uint32_t X9 = 0;
|
||||
uint32_t X10 = 0;
|
||||
uint32_t X11 = 0;
|
||||
uint32_t X12 = 0;
|
||||
uint32_t X13 = 0;
|
||||
uint32_t X14 = 0;
|
||||
uint32_t X15 = 0;
|
||||
uint32_t X16 = 0;
|
||||
uint32_t X17 = 0;
|
||||
uint32_t X18 = 0;
|
||||
uint32_t X19 = 0;
|
||||
uint32_t X20 = 0;
|
||||
uint32_t X21 = 0;
|
||||
uint32_t X22 = 0;
|
||||
uint32_t X23 = 0;
|
||||
uint32_t X24 = 0;
|
||||
uint32_t X25 = 0;
|
||||
uint32_t X26 = 0;
|
||||
uint32_t X27 = 0;
|
||||
uint32_t X28 = 0;
|
||||
uint32_t X29 = 0;
|
||||
uint32_t X30 = 0;
|
||||
uint32_t X31 = 0;
|
||||
uint32_t PC = 0;
|
||||
uint32_t NEXT_PC = 0;
|
||||
uint8_t PRIV = 0;
|
||||
struct TGF_C_regs {
|
||||
uint32_t X0 = 0;
|
||||
uint32_t X1 = 0;
|
||||
uint32_t X2 = 0;
|
||||
uint32_t X3 = 0;
|
||||
uint32_t X4 = 0;
|
||||
uint32_t X5 = 0;
|
||||
uint32_t X6 = 0;
|
||||
uint32_t X7 = 0;
|
||||
uint32_t X8 = 0;
|
||||
uint32_t X9 = 0;
|
||||
uint32_t X10 = 0;
|
||||
uint32_t X11 = 0;
|
||||
uint32_t X12 = 0;
|
||||
uint32_t X13 = 0;
|
||||
uint32_t X14 = 0;
|
||||
uint32_t X15 = 0;
|
||||
uint32_t X16 = 0;
|
||||
uint32_t X17 = 0;
|
||||
uint32_t X18 = 0;
|
||||
uint32_t X19 = 0;
|
||||
uint32_t X20 = 0;
|
||||
uint32_t X21 = 0;
|
||||
uint32_t X22 = 0;
|
||||
uint32_t X23 = 0;
|
||||
uint32_t X24 = 0;
|
||||
uint32_t X25 = 0;
|
||||
uint32_t X26 = 0;
|
||||
uint32_t X27 = 0;
|
||||
uint32_t X28 = 0;
|
||||
uint32_t X29 = 0;
|
||||
uint32_t X30 = 0;
|
||||
uint32_t X31 = 0;
|
||||
uint32_t PC = 0;
|
||||
uint32_t NEXT_PC = 0;
|
||||
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
|
||||
uint64_t icount = 0;
|
||||
} reg;
|
||||
@ -266,8 +242,8 @@ protected:
|
||||
|
||||
uint64_t interrupt_sim=0;
|
||||
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
|
||||
};
|
||||
|
||||
|
||||
@ -76,7 +76,7 @@ public:
|
||||
|
||||
sync_type get_sync() override { return POST_SYNC; };
|
||||
|
||||
void callback(instr_info_t instr_info, exec_info const&) override;
|
||||
void callback(instr_info_t instr_info) override;
|
||||
|
||||
private:
|
||||
iss::instrumentation_if *arch_instr;
|
||||
|
||||
@ -69,7 +69,7 @@ public:
|
||||
|
||||
sync_type get_sync() override { return POST_SYNC; };
|
||||
|
||||
void callback(instr_info_t, exec_info const&) override;
|
||||
void callback(instr_info_t instr_info) override;
|
||||
|
||||
private:
|
||||
Json::Value root;
|
||||
|
||||
@ -33,10 +33,10 @@
|
||||
#ifndef _SYSC_SIFIVE_FE310_H_
|
||||
#define _SYSC_SIFIVE_FE310_H_
|
||||
|
||||
#include "scc/initiator_mixin.h"
|
||||
#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
|
||||
#include "tlm/scc/initiator_mixin.h"
|
||||
#include "scc/traceable.h"
|
||||
#include "scc/utilities.h"
|
||||
#include "scv4tlm/tlm_rec_initiator_socket.h"
|
||||
#include <cci_configuration>
|
||||
#include <tlm>
|
||||
#include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
|
||||
@ -75,7 +75,7 @@ class core_wrapper;
|
||||
|
||||
class core_complex : public sc_core::sc_module, public scc::traceable {
|
||||
public:
|
||||
scc::initiator_mixin<scv4tlm::tlm_rec_initiator_socket<32>> initiator{"intor"};
|
||||
tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
|
||||
|
||||
sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -29,7 +29,7 @@
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#include "util/ities.h"
|
||||
#include <util/logging.h>
|
||||
#include <iss/arch/tgf_b.h>
|
||||
@ -39,10 +39,10 @@
|
||||
|
||||
using namespace iss::arch;
|
||||
|
||||
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_b>::reg_names;
|
||||
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_b>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_b>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_b>::reg_byte_offsets;
|
||||
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_b>::reg_names;
|
||||
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_b>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_b>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_b>::reg_byte_offsets;
|
||||
|
||||
tgf_b::tgf_b() {
|
||||
reg.icount = 0;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -29,7 +29,7 @@
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#include "util/ities.h"
|
||||
#include <util/logging.h>
|
||||
#include <iss/arch/tgf_c.h>
|
||||
@ -39,10 +39,10 @@
|
||||
|
||||
using namespace iss::arch;
|
||||
|
||||
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_c>::reg_names;
|
||||
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_c>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
|
||||
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_c>::reg_names;
|
||||
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_c>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
|
||||
|
||||
tgf_c::tgf_c() {
|
||||
reg.icount = 0;
|
||||
|
||||
@ -83,7 +83,7 @@ int main(int argc, char *argv[]) {
|
||||
("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
|
||||
("mem,m", po::value<std::string>(), "the memory input file")
|
||||
("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
|
||||
("backend", po::value<std::string>()->default_value("interp"), "the memory input file")
|
||||
("backend", po::value<std::string>()->default_value("tcc"), "the memory input file")
|
||||
("isa", po::value<std::string>()->default_value("tgf_c"), "isa to use for simulation");
|
||||
// clang-format on
|
||||
auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
|
||||
|
||||
@ -83,7 +83,7 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
|
||||
|
||||
}
|
||||
|
||||
void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const&) {
|
||||
void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
|
||||
assert(arch_instr && "No instrumentation interface available but callback executed");
|
||||
auto entry = delays[instr_info.instr_id];
|
||||
bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8);
|
||||
|
||||
@ -90,6 +90,6 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
|
||||
return true;
|
||||
}
|
||||
|
||||
void iss::plugin::instruction_count::callback(instr_info_t instr_info, exec_info const&) {
|
||||
void iss::plugin::instruction_count::callback(instr_info_t instr_info) {
|
||||
rep_counts[instr_info.instr_id]++;
|
||||
}
|
||||
|
||||
@ -331,7 +331,7 @@ void core_complex::disass_output(uint64_t pc, const std::string instr_str) {
|
||||
tr_handle.record_attribute("PC", pc);
|
||||
tr_handle.record_attribute("INSTR", instr_str);
|
||||
tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
|
||||
tr_handle.record_attribute("MSTATUS", cpu->get_state().mstatus.st.value);
|
||||
tr_handle.record_attribute("MSTATUS", cpu->get_state().mstatus.backing.val);
|
||||
tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000);
|
||||
#endif
|
||||
}
|
||||
@ -388,7 +388,7 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
|
||||
if (is_fetch && tr_handle.is_active()) {
|
||||
tr_handle.end_transaction();
|
||||
}
|
||||
auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this);
|
||||
auto preExt = new tlm::scc::scv4tlm::tlm_recording_extension(tr_handle, this);
|
||||
gp.set_extension(preExt);
|
||||
}
|
||||
#endif
|
||||
@ -434,7 +434,7 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
|
||||
sc_time delay{quantum_keeper.get_local_time()};
|
||||
#ifdef WITH_SCV
|
||||
if (m_db != nullptr && tr_handle.is_valid()) {
|
||||
auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this);
|
||||
auto preExt = new tlm::scc::scv4tlm::tlm_recording_extension(tr_handle, this);
|
||||
gp.set_extension(preExt);
|
||||
}
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -377,6 +377,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 2);
|
||||
gen_trap_check(tu);
|
||||
@ -423,6 +424,7 @@ private:
|
||||
new_pc_val,
|
||||
tu.l_not(tu.constant(0x1, 32U))), 32);
|
||||
tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 3);
|
||||
@ -464,6 +466,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 4);
|
||||
gen_trap_check(tu);
|
||||
@ -504,6 +507,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 5);
|
||||
gen_trap_check(tu);
|
||||
@ -548,6 +552,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 6);
|
||||
gen_trap_check(tu);
|
||||
@ -592,6 +597,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 7);
|
||||
gen_trap_check(tu);
|
||||
@ -632,6 +638,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 8);
|
||||
gen_trap_check(tu);
|
||||
@ -672,6 +679,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 9);
|
||||
gen_trap_check(tu);
|
||||
@ -1613,6 +1621,7 @@ private:
|
||||
tu.constant(1, 64U),
|
||||
tu.trunc(tu.constant(imm, 32U), 32));
|
||||
tu.close_scope();
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
|
||||
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 38);
|
||||
gen_trap_check(tu);
|
||||
@ -2046,11 +2055,13 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
|
||||
tu(" *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
|
||||
tu("leave_trap(core_ptr, {});", lvl);
|
||||
tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
|
||||
@ -2059,6 +2070,7 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
|
||||
tu("trap_entry:");
|
||||
tu("enter_trap(core_ptr, *trap_state, *pc);");
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
|
||||
tu("return *next_pc;");
|
||||
}
|
||||
|
||||
|
||||
@ -449,6 +449,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 2);
|
||||
gen_trap_check(tu);
|
||||
@ -486,6 +487,7 @@ private:
|
||||
new_pc_val,
|
||||
tu.l_not(tu.constant(0x1, 32U))), 32);
|
||||
tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 3);
|
||||
gen_trap_check(tu);
|
||||
@ -526,6 +528,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 4);
|
||||
gen_trap_check(tu);
|
||||
@ -566,6 +569,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 5);
|
||||
gen_trap_check(tu);
|
||||
@ -610,6 +614,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 6);
|
||||
gen_trap_check(tu);
|
||||
@ -654,6 +659,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 7);
|
||||
gen_trap_check(tu);
|
||||
@ -694,6 +700,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 8);
|
||||
gen_trap_check(tu);
|
||||
@ -734,6 +741,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 9);
|
||||
gen_trap_check(tu);
|
||||
@ -1675,6 +1683,7 @@ private:
|
||||
tu.constant(1, 64U),
|
||||
tu.trunc(tu.constant(imm, 32U), 32));
|
||||
tu.close_scope();
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
|
||||
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 38);
|
||||
gen_trap_check(tu);
|
||||
@ -2553,6 +2562,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 65);
|
||||
gen_trap_check(tu);
|
||||
@ -2858,6 +2868,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 76);
|
||||
gen_trap_check(tu);
|
||||
@ -2897,6 +2908,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 77);
|
||||
gen_trap_check(tu);
|
||||
@ -2936,6 +2948,7 @@ private:
|
||||
auto is_cont_v = tu.choose(
|
||||
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
|
||||
tu.constant(0U, 32), tu.constant(1U, 32));
|
||||
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 78);
|
||||
gen_trap_check(tu);
|
||||
@ -3042,6 +3055,7 @@ private:
|
||||
tu.open_scope();
|
||||
auto PC_val_v = tu.assignment("PC_val", tu.load(rs1 + traits<ARCH>::X0, 0), 32);
|
||||
tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 82);
|
||||
gen_trap_check(tu);
|
||||
@ -3094,6 +3108,7 @@ private:
|
||||
tu.constant(2, 32U)), 1 + traits<ARCH>::X0);
|
||||
auto PC_val_v = tu.assignment("PC_val", tu.load(rs1 + traits<ARCH>::X0, 0), 32);
|
||||
tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 84);
|
||||
gen_trap_check(tu);
|
||||
@ -3232,11 +3247,13 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
|
||||
tu(" *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
|
||||
tu("leave_trap(core_ptr, {});", lvl);
|
||||
tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
|
||||
@ -3245,6 +3262,7 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
|
||||
tu("trap_entry:");
|
||||
tu("enter_trap(core_ptr, *trap_state, *pc);");
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
|
||||
tu("return *next_pc;");
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user