Merge branch 'develop' of

https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop

CMakeLists.txt

@@ -15,19 +15,20 @@ find_package(Boost COMPONENTS coroutine REQUIRED)
 add_subdirectory(softfloat)
 
 set(LIB_SOURCES 
-	src/iss/arch/tgc_c.cpp
+    src/iss/plugin/instruction_count.cpp
-	src/vm/tcc/vm_tgc_c.cpp
+	src/iss/arch/tgc5c.cpp
-	src/vm/interp/vm_tgc_c.cpp
+	src/vm/tcc/vm_tgc5c.cpp
+	src/vm/interp/vm_tgc5c.cpp
 	src/vm/fp_functions.cpp
 )
 if(WITH_TCC)
 	list(APPEND LIB_SOURCES
-		src/vm/tcc/vm_tgc_c.cpp
+	   src/vm/tcc/vm_tgc5c.cpp
-	)
+    )
 endif()
 if(WITH_LLVM)
 	list(APPEND LIB_SOURCES
-		src/vm/llvm/vm_tgc_c.cpp
+		src/vm/llvm/vm_tgc5c.cpp
 		src/vm/llvm/fp_impl.cpp
 	)
 endif()

gen_input/TGC_C.core_desc

@@ -1,8 +1,8 @@
-import "ISA/RV32I.core_desc"
+import "ISA/RVI.core_desc"
 import "ISA/RVM.core_desc"
 import "ISA/RVC.core_desc"
 
-Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
+Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
     architectural_state {
         XLEN=32;
         // definitions for the architecture wrapper

src/iss/arch/tgc5c.cpp

@@ -30,7 +30,7 @@
  *
  *******************************************************************************/
 
-#include "tgc_c.h"
+#include "tgc5c.h"
 #include "util/ities.h"
 #include <util/logging.h>
 #include <cstdio>
@@ -39,18 +39,18 @@
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5c>::reg_names;
-constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5c>::reg_aliases;
-constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_byte_offsets;
 
-tgc_c::tgc_c()  = default;
+tgc5c::tgc5c()  = default;
 
-tgc_c::~tgc_c() = default;
+tgc5c::~tgc5c() = default;
 
-void tgc_c::reset(uint64_t address) {
+void tgc5c::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<tgc_c>::reg_t*>(get_regs_base_ptr());
+    auto base_ptr = reinterpret_cast<traits<tgc5c>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i)
+    for(size_t i=0; i<traits<tgc5c>::NUM_REGS; ++i)
         *(base_ptr+i)=0;
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
@@ -59,11 +59,11 @@ void tgc_c::reset(uint64_t address) {
     reg.icount=0;
 }
 
-uint8_t *tgc_c::get_regs_base_ptr() {
+uint8_t *tgc5c::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }
 
-tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &addr) {
+tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
+    return phys_addr_t(pc); // change logical address to physical address
 }
 

src/iss/arch/tgc5c.h

@@ -30,8 +30,8 @@
  *
  *******************************************************************************/
 
-#ifndef _TGC_C_H_
+#ifndef _TGC5C_H_
-#define _TGC_C_H_
+#define _TGC5C_H_
 
 #include <array>
 #include <iss/arch/traits.h>
@@ -41,11 +41,11 @@
 namespace iss {
 namespace arch {
 
-struct tgc_c;
+struct tgc5c;
 
-template <> struct traits<tgc_c> {
+template <> struct traits<tgc5c> {
 
-    constexpr static char const* const core_type = "TGC_C";
+    constexpr static char const* const core_type = "TGC5C";
     
     static constexpr std::array<const char*, 36> reg_names{
         {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
@@ -175,15 +175,15 @@ template <> struct traits<tgc_c> {
     };
 };
 
-struct tgc_c: public arch_if {
+struct tgc5c: public arch_if {
 
-    using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
+    using virt_addr_t = typename traits<tgc5c>::virt_addr_t;
-    using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
+    using phys_addr_t = typename traits<tgc5c>::phys_addr_t;
-    using reg_t =  typename traits<tgc_c>::reg_t;
+    using reg_t =  typename traits<tgc5c>::reg_t;
-    using addr_t = typename traits<tgc_c>::addr_t;
+    using addr_t = typename traits<tgc5c>::addr_t;
 
-    tgc_c();
+    tgc5c();
-    ~tgc_c();
+    ~tgc5c();
 
     void reset(uint64_t address=0) override;
 
@@ -195,6 +195,14 @@ struct tgc_c: public arch_if {
 
     inline uint64_t stop_code() { return interrupt_sim; }
 
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<tgc5c>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5c>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
     virtual phys_addr_t virt2phys(const iss::addr_t& addr);
 
     virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
@@ -203,7 +211,7 @@ struct tgc_c: public arch_if {
 
 
 #pragma pack(push, 1)
-    struct TGC_C_regs { 
+    struct TGC5C_regs { 
         uint32_t X0 = 0; 
         uint32_t X1 = 0; 
         uint32_t X2 = 0; 
@@ -254,8 +262,9 @@ struct tgc_c: public arch_if {
 
     uint32_t get_fcsr(){return 0;}
     void set_fcsr(uint32_t val){}
+
 };
 
 }
 }            
-#endif /* _TGC_C_H_ */
+#endif /* _TGC5C_H_ */

src/iss/arch/tgc_mapper.h

@@ -2,49 +2,49 @@
 #define _ISS_ARCH_TGC_MAPPER_H
 
 #include "riscv_hart_m_p.h"
-#include "tgc_c.h"
+#include "tgc5c.h"
-using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
+using tgc5c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5c>;
-#ifdef CORE_TGC_A
+#ifdef CORE_TGC5A
 #include "riscv_hart_m_p.h"
-#include <iss/arch/tgc_a.h>
+#include <iss/arch/tgc5a.h>
-using tgc_a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_a>;
+using tgc5a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5a>;
 #endif
-#ifdef CORE_TGC_B
+#ifdef CORE_TGC5B
 #include "riscv_hart_m_p.h"
-#include <iss/arch/tgc_b.h>
+#include <iss/arch/tgc5b.h>
-using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
+using tgc5b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5b>;
 #endif
-#ifdef CORE_TGC_C_XRB_NN
+#ifdef CORE_TGC5C_XRB_NN
 #include "riscv_hart_m_p.h"
 #include "hwl.h"
-#include <iss/arch/tgc_c_xrb_nn.h>
+#include <iss/arch/tgc5c_xrb_nn.h>
-using tgc_c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>>;
+using tgc5c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc5c_xrb_nn>>;
 #endif
-#ifdef CORE_TGC_D
+#ifdef CORE_TGC5D
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc_d.h>
+#include <iss/arch/tgc5d.h>
-using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+using tgc5d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
-#ifdef CORE_TGC_D_XRB_MAC
+#ifdef CORE_TGC5D_XRB_MAC
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc_d_xrb_mac.h>
+#include <iss/arch/tgc5d_xrb_mac.h>
-using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+using tgc5d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
-#ifdef CORE_TGC_D_XRB_NN
+#ifdef CORE_TGC5D_XRB_NN
 #include "riscv_hart_mu_p.h"
 #include "hwl.h"
-#include <iss/arch/tgc_d_xrb_nn.h>
+#include <iss/arch/tgc5d_xrb_nn.h>
-using tgc_d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
+using tgc5d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
 #endif
-#ifdef CORE_TGC_E
+#ifdef CORE_TGC5E
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc_e.h>
+#include <iss/arch/tgc5e.h>
-using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+using tgc5e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
-#ifdef CORE_TGC_X
+#ifdef CORE_TGC5X
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc_x.h>
+#include <iss/arch/tgc5x.h>
-using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
+using tgc5x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
 #endif
 
 #endif

src/sysc/core_complex.cpp

@@ -147,8 +147,8 @@ public:
             std::tie(cpu, vm) = f.create(type+"|"+backend);
         } else {
             auto base_isa = type.substr(0, 5);
-            if(base_isa=="tgc_d" || base_isa=="tgc_e") {
+            if(base_isa=="tgc5d" || base_isa=="tgc5e") {
-                std::tie(cpu, vm) = f.create(type + "|mu_p_clic_pmp|" + backend, gdb_port, owner);
+                std::tie(cpu, vm) = f.create(type + "|mu_p_clic_pmp|" + backend, gdb_port);
             } else {
                 std::tie(cpu, vm) = f.create(type + "|m_p|" + backend, gdb_port, owner);
            }

src/sysc/core_complex.h

@@ -96,7 +96,7 @@ public:
 
     cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
 
-    cci::cci_param<std::string> core_type{"core_type", "tgc_c"};
+    cci::cci_param<std::string> core_type{"core_type", "tgc5c"};
 
     cci::cci_param<std::string> backend{"backend", "interp"};
 
@@ -121,7 +121,7 @@ public:
 
     scml_property<unsigned long long> reset_address{"reset_address", 0ULL};
 
-    scml_property<std::string> core_type{"core_type", "tgc_c"};
+    scml_property<std::string> core_type{"core_type", "tgc5c"};
 
     scml_property<std::string> backend{"backend", "interp"};
 
@@ -139,7 +139,7 @@ public:
     , elf_file{"elf_file", ""}
     , enable_disass{"enable_disass", false}
     , reset_address{"reset_address", 0ULL}
-    , core_type{"core_type", "tgc_c"}
+    , core_type{"core_type", "tgc5c"}
     , backend{"backend", "interp"}
     , gdb_server_port{"gdb_server_port", 0}
     , dump_ir{"dump_ir", false}

src/sysc/register_tgc_c.cpp

@@ -31,7 +31,7 @@
  *******************************************************************************/
 
 #include "iss_factory.h"
-#include <iss/arch/tgc_c.h>
+#include <iss/arch/tgc5c.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
 #include "sc_core_adapter.h"
@@ -42,15 +42,15 @@ namespace iss {
 namespace interp {
 using namespace sysc;
 volatile std::array<bool, 2> tgc_init = {
-        iss_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+        core_factory::instance().register_creator("tgc5c|m_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
+            arch::tgc5c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc_c*>(cpu), gdb_port)}};
+            return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
         }),
-        iss_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+        core_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
+            arch::tgc5c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc_c*>(cpu), gdb_port)}};
+            return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
         })
 };
 }
@@ -58,15 +58,15 @@ volatile std::array<bool, 2> tgc_init = {
 namespace tcc {
 using namespace sysc;
 volatile std::array<bool, 2> tgc_init = {
-        iss_factory::instance().register_creator("tgc_c|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+        core_factory::instance().register_creator("tgc5c|m_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
+            arch::tgc5c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc_c*>(cpu), gdb_port)}};
+            return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
         }),
-        iss_factory::instance().register_creator("tgc_c|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+        core_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
+            arch::tgc5c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc_c*>(cpu), gdb_port)}};
+            return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
         })
 };
 }

src/vm/interp/vm_tgc5c.cpp

@@ -30,7 +30,7 @@
  *
  *******************************************************************************/
 
-#include <iss/arch/tgc_c.h>
+#include <iss/arch/tgc5c.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
@@ -50,7 +50,7 @@
 
 namespace iss {
 namespace interp {
-namespace tgc_c {
+namespace tgc5c {
 using namespace iss::arch;
 using namespace iss::debugger;
 using namespace std::placeholders;
@@ -152,22 +152,14 @@ private:
     /****************************************************************************
      * start opcode definitions
      ****************************************************************************/
-    struct instruction_descriptor {
+    struct InstructionDesriptor {
         size_t length;
         uint32_t value;
         uint32_t mask;
         typename arch::traits<ARCH>::opcode_e op;
     };
-    struct decoding_tree_node{
-        std::vector<instruction_descriptor> instrs;
-        std::vector<decoding_tree_node*> children;
-        uint32_t submask = std::numeric_limits<uint32_t>::max();
-        uint32_t value;
-        decoding_tree_node(uint32_t value) : value(value){}
-    };
 
-    decoding_tree_node* root {nullptr};
+    const std::array<InstructionDesriptor, 87> instr_descr = {{
-    const std::array<instruction_descriptor, 87> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */
         {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, arch::traits<ARCH>::opcode_e::LUI},
         {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, arch::traits<ARCH>::opcode_e::AUIPC},
@@ -258,75 +250,18 @@ private:
         {16, 0b0000000000000000, 0b1111111111111111, arch::traits<ARCH>::opcode_e::DII},
     }};
 
+    //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        if(this->core.has_mmu()) {
+        auto phys_pc = this->core.v2p(pc);
-            auto phys_pc = this->core.virt2phys(pc);
+        //if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-//            if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+        //    if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
-//                if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
+        //    if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
-//                if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
+        //        if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
-//                    if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok)
+        //} else {
-//                        return iss::Err;
+            if (this->core.read(phys_pc, 4, data) != iss::Ok)  return iss::Err;
-//            } else {
+        //}
-                if (this->core.read(phys_pc, 4, data) != iss::Ok)
-                    return iss::Err;
-//            }
-        } else {
-            if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok)
-                return iss::Err;
-
-        }
         return iss::Ok;
     }
-    void populate_decoding_tree(decoding_tree_node* root){
-        //create submask
-        for(auto instr: root->instrs){
-            root->submask &= instr.mask;
-        }
-        //put each instr according to submask&encoding into children
-        for(auto instr: root->instrs){
-            bool foundMatch = false;
-            for(auto child: root->children){
-                //use value as identifying trait
-                if(child->value == (instr.value&root->submask)){
-                    child->instrs.push_back(instr);
-                    foundMatch = true;
-                }
-            }
-            if(!foundMatch){
-                decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask);
-                child->instrs.push_back(instr);
-                root->children.push_back(child);
-            }
-        }
-        root->instrs.clear();
-        //call populate_decoding_tree for all children
-        if(root->children.size() >1)
-            for(auto child: root->children){
-                populate_decoding_tree(child);      
-            }
-        else{
-            //sort instrs by value of the mask, this works bc we want to have the least restrictive one last
-            std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) {
-            return instr1.mask > instr2.mask;
-            }); 
-        }
-    }
-    typename arch::traits<ARCH>::opcode_e  decode_instr(decoding_tree_node* node, code_word_t word){
-        if(!node->children.size()){
-            if(node->instrs.size() == 1) return node->instrs[0].op;
-            for(auto instr : node->instrs){
-                if((instr.mask&word) == instr.value) return instr.op;
-            }
-        }
-        else{
-            for(auto child : node->children){
-                if (child->value == (node->submask&word)){
-                    return decode_instr(child, word);
-                }  
-            }  
-        }
-        return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
-    }
 };
 
 template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
@@ -353,11 +288,16 @@ constexpr size_t bit_count(uint32_t u) {
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
-    root = new decoding_tree_node(std::numeric_limits<uint32_t>::max());
+    unsigned id=0;
-    for(auto instr:instr_descr){
+    for (auto instr : instr_descr) {
-        root->instrs.push_back(instr);
+        auto quadrant = instr.value & 0x3;
+        qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+    }
+    for(auto& lut: qlut){
+        std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+            return bit_count(a.mask) > bit_count(b.mask);
+        });
     }
-    populate_decoding_tree(root);
 }
 
 inline bool is_count_limit_enabled(finish_cond_e cond){
@@ -368,6 +308,14 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
     return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
 }
 
+template <typename ARCH>
+typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
+    for(auto& e: qlut[instr&0x3]){
+        if(!((instr&e.mask) ^ e.value )) return e.id;
+    }
+    return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
+}
+
 template <typename ARCH>
 typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
     auto pc=start;
@@ -389,7 +337,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
         } else {
             if (is_jump_to_self_enabled(cond) &&
                     (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-            auto inst_id = decode_instr(root, instr);
+            auto inst_id = decode_inst_id(instr);
             // pre execution stuff
              this->core.reg.last_branch = 0;
             if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
@@ -2687,11 +2635,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
     return pc;
 }
 
-} // namespace tgc_c
+} // namespace tgc5c
 
 template <>
-std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
+std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short port, bool dump) {
-    auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
+    auto ret = new tgc5c::vm_impl<arch::tgc5c>(*core, dump);
     if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }
@@ -2704,15 +2652,15 @@ std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short por
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("tgc5c|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc_c>();
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
-		    auto vm = new interp::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
+		    auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         }),
-        core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc_c>();
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
-		    auto vm = new interp::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
+		    auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         })

src/vm/llvm/vm_tgc5c.cpp

@@ -30,8 +30,8 @@
  *
  *******************************************************************************/
 
-#include <iss/arch/tgc_c.h>
 #include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/tgc5c.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
@@ -52,7 +52,7 @@ namespace fp_impl {
 void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
 }
 
-namespace tgc_c {
+namespace tgc5c {
 using namespace ::llvm;
 using namespace iss::arch;
 using namespace iss::debugger;
@@ -111,7 +111,7 @@ protected:
     void gen_trap_check(BasicBlock *bb);
 
     inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
-        return this->builder.CreateLoad(this->get_typeptr(i), get_reg_ptr(i), false);
+        return this->builder.CreateLoad(get_reg_ptr(i), false);
     }
 
     inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
@@ -124,7 +124,7 @@ protected:
     // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
     enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
     enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(static_cast<uint64_t>(EXTR_MASK32)), LUT_SIZE_C = 1 << util::bit_count(static_cast<uint64_t>(EXTR_MASK16)) };
+    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
 
     using this_class = vm_impl<ARCH>;
     using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
@@ -4042,10 +4042,10 @@ private:
      ****************************************************************************/
     std::tuple<continuation_e, BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
 		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
-        this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits<ARCH>::NEXT_PC), get_reg_ptr(traits<ARCH>::NEXT_PC), true),
+        this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
                                    get_reg_ptr(traits<ARCH>::PC), true);
         this->builder.CreateStore(
-            this->builder.CreateAdd(this->builder.CreateLoad(this->get_typeptr(traits<ARCH>::ICOUNT), get_reg_ptr(traits<ARCH>::ICOUNT), true),
+            this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
                                      this->gen_const(64U, 1)),
             get_reg_ptr(traits<ARCH>::ICOUNT), true);
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
@@ -4082,22 +4082,20 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
     code_word_t insn = 0;
-    // const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
+    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
     phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&insn;
-    if(this->core.has_mmu())
+    paddr = this->core.v2p(pc);
-        paddr = this->core.virt2phys(pc);
+    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-    //TODO: re-add page handling
+        auto res = this->core.read(paddr, 2, data);
-//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-//        auto res = this->core.read(paddr, 2, data);
+        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
-//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
-//        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
+        }
-//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+    } else {
-//        }
-//    } else {
         auto res = this->core.read(paddr, 4, data);
         if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-//    }
+    }
     if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
     // curr pc on stack
     ++inst_cnt;
@@ -4111,7 +4109,7 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
 
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
     this->builder.SetInsertPoint(leave_blk);
-    this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::NEXT_PC), get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
+    this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
@@ -4135,53 +4133,31 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
 
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
     this->builder.SetInsertPoint(trap_blk);
-    auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::TRAP_STATE), get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
+    auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
     this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
                               get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
     std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
-                              this->adj_to64(this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::PC), get_reg_ptr(traits<ARCH>::PC), false))};
+                              this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
     this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
-    auto *trap_addr_val = this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::NEXT_PC), get_reg_ptr(traits<ARCH>::NEXT_PC), false);
+    auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
     this->builder.CreateRet(trap_addr_val);
 }
 
 template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
-    auto *v = this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::TRAP_STATE), get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
+    auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
     this->gen_cond_branch(this->builder.CreateICmp(
                               ICmpInst::ICMP_EQ, v,
                               ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
                           bb, this->trap_blk, 1);
 }
 
-} // namespace tgc_c
+} // namespace tgc5c
 
 template <>
-std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
+std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short port, bool dump) {
-    auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
+    auto ret = new tgc5c::vm_impl<arch::tgc5c>(*core, dump);
     if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }
 } // namespace llvm
 } // namespace iss
-
-#include <iss/factory.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("tgc_c|m_p|llvm", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc_c>();
-            auto* vm = new llvm::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
-            if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        }),
-        core_factory::instance().register_creator("tgc_c|mu_p|llvm", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc_c>();
-            auto* vm = new llvm::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
-            if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        })
-};
-}
-}

src/vm/tcc/vm_tgc5c.cpp

@@ -30,7 +30,7 @@
  *
  *******************************************************************************/
 
-#include <iss/arch/tgc_c.h>
+#include <iss/arch/tgc5c.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
@@ -48,7 +48,7 @@
 
 namespace iss {
 namespace tcc {
-namespace tgc_c {
+namespace tgc5c {
 using namespace iss::arch;
 using namespace iss::debugger;
 
@@ -120,7 +120,57 @@ protected:
         }
     }
 
-    
+    // some compile time constants
+    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
+    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
+    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
+    enum { LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)), LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16)) };
+
+    std::array<compile_func, LUT_SIZE> lut;
+
+    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
+    std::array<compile_func, LUT_SIZE> lut_11;
+
+    std::array<compile_func *, 4> qlut;
+
+    std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
+
+    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
+                         compile_func f) {
+        if (pos < 0) {
+            lut[idx] = f;
+        } else {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
+            } else {
+                if ((valid & bitmask) == 0) {
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
+                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
+                } else {
+                    auto new_val = idx << 1;
+                    if ((value & bitmask) != 0) new_val++;
+                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
+                }
+            }
+        }
+    }
+
+    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
+
+    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
+        if (pos >= 0) {
+            auto bitmask = 1UL << pos;
+            if ((mask & bitmask) == 0) {
+                lut_val = extract_fields(pos - 1, val, mask, lut_val);
+            } else {
+                auto new_val = lut_val << 1;
+                if ((val & bitmask) != 0) new_val++;
+                lut_val = extract_fields(pos - 1, val, mask, new_val);
+            }
+        }
+        return lut_val;
+    }
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
         auto mask = (1ULL<<W) - 1;
@@ -132,23 +182,14 @@ private:
     /****************************************************************************
      * start opcode definitions
      ****************************************************************************/
-    struct instruction_descriptor {
+    struct InstructionDesriptor {
         size_t length;
         uint32_t value;
         uint32_t mask;
         compile_func op;
     };
-    struct decoding_tree_node{
-        std::vector<instruction_descriptor> instrs;
-        std::vector<decoding_tree_node*> children;
-        uint32_t submask = std::numeric_limits<uint32_t>::max();
-        uint32_t value;
-        decoding_tree_node(uint32_t value) : value(value){}
-    };
 
-    decoding_tree_node* root {nullptr};
+    const std::array<InstructionDesriptor, 87> instr_descr = {{
-
-    const std::array<instruction_descriptor, 87> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */
         /* instruction LUI, encoding '0b00000000000000000000000000110111' */
         {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
@@ -452,14 +493,14 @@ private:
             this->gen_raise_trap(tu, 0,  2);
         }
         else{
-        	auto new_pc = tu.assignment(tu.ext((tu.bitwise_and((tu.add(tu.load(rs1+ traits::X0, 0),tu.constant((int16_t)sext<12>(imm),16))),tu.constant(~0x1,8))),32,true),32);
+        	auto new_pc = tu.assignment(tu.ext((tu.bitwise_and((tu.add(tu.load(rs1+ traits::X0, 0),tu.constant((int16_t)sext<12>(imm),16))),tu.constant(~ 0x1,8))),32,true),32);
         	tu.open_if(tu.srem(new_pc,tu.constant(static_cast<uint32_t>(traits:: INSTR_ALIGNMENT),32)));
         	this->gen_raise_trap(tu, 0,  0);
         	tu.open_else();
         	if(rd!= 0) {
         	    tu.store(rd + traits::X0,tu.ext((tu.add(tu.ext(cur_pc_val,32,false),tu.constant( 4,8))),32,true));
         	}
-        	auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(new_pc,tu.constant(~0x1,8)),32);
+        	auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(new_pc,tu.constant(~ 0x1,8)),32);
         	tu.store(traits::NEXT_PC, PC_val_v);
         	tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
         	tu.close_scope();
@@ -1921,7 +1962,7 @@ private:
         else{
         	auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32);
         	if(zimm!= 0) {
-        	    tu.write_mem(traits::CSR, csr, tu.bitwise_and(xrd,tu.constant(~((uint32_t)zimm),32)));
+        	    tu.write_mem(traits::CSR, csr, tu.bitwise_and(xrd,tu.constant(~ ((uint32_t)zimm),32)));
         	}
         	if(rd!= 0) {
         	    tu.store(rd + traits::X0,xrd);
@@ -2122,13 +2163,13 @@ private:
         	auto divisor = tu.assignment(tu.ext(tu.load(rs2+ traits::X0, 0),32,false),32);
         	if(rd!= 0){ tu.open_if(tu.icmp(ICmpInst::ICMP_NE,divisor,tu.constant( 0,8)));
         	auto MMIN = tu.assignment(tu.constant(((uint32_t)1)<<(static_cast<uint32_t>(traits:: XLEN)-1),32),32);
-        	tu.open_if(tu.logical_and(tu.icmp(ICmpInst::ICMP_EQ,tu.load(rs1+ traits::X0, 0),MMIN),tu.icmp(ICmpInst::ICMP_EQ,divisor,tu.constant(-1,8))));
+        	tu.open_if(tu.logical_and(tu.icmp(ICmpInst::ICMP_EQ,tu.load(rs1+ traits::X0, 0),MMIN),tu.icmp(ICmpInst::ICMP_EQ,divisor,tu.constant(- 1,8))));
         	tu.store(rd + traits::X0,MMIN);
         	tu.open_else();
         	tu.store(rd + traits::X0,tu.ext((tu.sdiv(dividend,divisor)),32,true));
         	tu.close_scope();
         	tu.open_else();
-        	tu.store(rd + traits::X0,tu.constant((uint32_t)-1,32));
+        	tu.store(rd + traits::X0,tu.constant((uint32_t)- 1,32));
         	tu.close_scope();
         	}
         }
@@ -2167,7 +2208,7 @@ private:
         	}
         	tu.open_else();
         	if(rd!=0) {
-        	    tu.store(rd + traits::X0,tu.constant((uint32_t)-1,32));
+        	    tu.store(rd + traits::X0,tu.constant((uint32_t)- 1,32));
         	}
         	tu.close_scope();
         }
@@ -2202,7 +2243,7 @@ private:
         else{
         	tu.open_if(tu.icmp(ICmpInst::ICMP_NE,tu.load(rs2+ traits::X0, 0),tu.constant( 0,8)));
         	auto MMIN = tu.assignment(tu.constant( 1<<(static_cast<uint32_t>(traits:: XLEN)-1),8),32);
-        	tu.open_if(tu.logical_and(tu.icmp(ICmpInst::ICMP_EQ,tu.load(rs1+ traits::X0, 0),MMIN),tu.icmp(ICmpInst::ICMP_EQ,tu.ext(tu.load(rs2+ traits::X0, 0),32,false),tu.constant(-1,8))));
+        	tu.open_if(tu.logical_and(tu.icmp(ICmpInst::ICMP_EQ,tu.load(rs1+ traits::X0, 0),MMIN),tu.icmp(ICmpInst::ICMP_EQ,tu.ext(tu.load(rs2+ traits::X0, 0),32,false),tu.constant(- 1,8))));
         	if(rd!=0) {
         	    tu.store(rd + traits::X0,tu.constant( 0,8));
         	}
@@ -2914,7 +2955,7 @@ private:
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
         if(rs1&&rs1<static_cast<uint32_t>(traits:: RFS)) {
-            auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(tu.load(rs1%static_cast<uint32_t>(traits:: RFS)+ traits::X0, 0),tu.constant(~0x1,8)),32);
+            auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(tu.load(rs1%static_cast<uint32_t>(traits:: RFS)+ traits::X0, 0),tu.constant(~ 0x1,8)),32);
             tu.store(traits::NEXT_PC, PC_val_v);
             tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
         }
@@ -3002,7 +3043,7 @@ private:
         else{
         	auto new_pc = tu.assignment(tu.load(rs1+ traits::X0, 0),32);
         	tu.store(1 + traits::X0,tu.ext((tu.add(tu.ext(cur_pc_val,32,false),tu.constant( 2,8))),32,true));
-        	auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(new_pc,tu.constant(~0x1,8)),32);
+        	auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(new_pc,tu.constant(~ 0x1,8)),32);
         	tu.store(traits::NEXT_PC, PC_val_v);
         	tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
         }
@@ -3095,64 +3136,11 @@ private:
         vm_impl::gen_trap_check(tu);
         return BRANCH;
     }
-    
-    //decoding functionality
-
-    void populate_decoding_tree(decoding_tree_node* root){
-        //create submask
-        for(auto instr: root->instrs){
-            root->submask &= instr.mask;
-        }
-        //put each instr according to submask&encoding into children
-        for(auto instr: root->instrs){
-            bool foundMatch = false;
-            for(auto child: root->children){
-                //use value as identifying trait
-                if(child->value == (instr.value&root->submask)){
-                    child->instrs.push_back(instr);
-                    foundMatch = true;
-                }
-            }
-            if(!foundMatch){
-                decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask);
-                child->instrs.push_back(instr);
-                root->children.push_back(child);
-            }
-        }
-        root->instrs.clear();
-        //call populate_decoding_tree for all children
-        if(root->children.size() >1)
-            for(auto child: root->children){
-                populate_decoding_tree(child);      
-            }
-        else{
-            //sort instrs by value of the mask, this works bc we want to have the least restrictive one last
-            std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) {
-            return instr1.mask > instr2.mask;
-            }); 
-        }
-    }
-    compile_func decode_instr(decoding_tree_node* node, code_word_t word){
-        if(!node->children.size()){
-            if(node->instrs.size() == 1) return node->instrs[0].op;
-            for(auto instr : node->instrs){
-                if((instr.mask&word) == instr.value) return instr.op;
-            }
-        }
-        else{
-            for(auto child : node->children){
-                if (child->value == (node->submask&word)){
-                    return decode_instr(child, word);
-                }  
-            }  
-        }
-        return nullptr;
-    }
 };
 
-template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
+template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
-    volatile CODE_WORD x = instr;
+    volatile CODE_WORD x = insn;
-    instr = 2 * x;
+    insn = 2 * x;
 }
 
 template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
@@ -3160,11 +3148,14 @@ template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
-    root = new decoding_tree_node(std::numeric_limits<uint32_t>::max());
+    qlut[0] = lut_00.data();
-    for(auto instr:instr_descr){
+    qlut[1] = lut_01.data();
-        root->instrs.push_back(instr);
+    qlut[2] = lut_10.data();
+    qlut[3] = lut_11.data();
+    for (auto instr : instr_descr) {
+        auto quantrant = instr.value & 0x3;
+        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
     }
-    populate_decoding_tree(root);
 }
 
 template <typename ARCH>
@@ -3172,11 +3163,11 @@ std::tuple<continuation_e>
 vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
-    code_word_t instr = 0;
+    code_word_t insn = 0;
+    // const typename traits::addr_t upper_bits = ~traits::PGMASK;
     phys_addr_t paddr(pc);
-    if(this->core.has_mmu())
+    auto *const data = (uint8_t *)&insn;
-        paddr = this->core.virt2phys(pc);
+    paddr = this->core.v2p(pc);
-    //TODO: re-add page handling
 //    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
 //        auto res = this->core.read(paddr, 2, data);
 //        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
@@ -3184,17 +3175,18 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
 //            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
 //        }
 //    } else {
-        auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
+        auto res = this->core.read(paddr, 4, data);
         if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
 //    }
-    if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
     // curr pc on stack
     ++inst_cnt;
-    auto f = decode_instr(root, instr);
+    auto lut_val = extract_fields(insn);
+    auto f = qlut[insn & 0x3][lut_val];
     if (f == nullptr) {
         f = &this_class::illegal_intruction;
     }
-    return (this->*f)(pc, instr, tu);
+    return (this->*f)(pc, insn, tu);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
@@ -3218,11 +3210,11 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu("return *next_pc;");
 }
 
-} // namespace tgc_c
+} // namespace tgc5c
 
 template <>
-std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
+std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short port, bool dump) {
-    auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
+    auto ret = new tgc5c::vm_impl<arch::tgc5c>(*core, dump);
     if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }
@@ -3235,15 +3227,15 @@ std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short por
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("tgc_c|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("tgc5c|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc_c>();
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
-            auto* vm = new tcc::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
+		    auto vm = new tcc::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         }),
-        core_factory::instance().register_creator("tgc_c|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc_c>();
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
-            auto* vm = new tcc::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
+		    auto vm = new tcc::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         })