add read misa callback
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2f4cfb68dc
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@ -309,8 +309,6 @@ public:
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T satp;
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T satp;
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static constexpr T get_misa() { return (1UL << 30) | ISA_I | ISA_M | ISA_A | ISA_U | ISA_S | ISA_M; }
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static constexpr uint32_t get_mask() {
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static constexpr uint32_t get_mask() {
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return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011 // only machine mode is supported
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return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011 // only machine mode is supported
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}
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}
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@ -434,10 +432,8 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
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: state()
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: state()
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, cycle_offset(0)
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, cycle_offset(0)
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, instr_if(*this) {
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, instr_if(*this) {
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csr[misa] = hart_state<reg_t>::get_misa();
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csr[misa] = traits<BASE>::MISA_VAL;
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uart_buf.str("");
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uart_buf.str("");
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// read-only registers
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csr_wr_cb[misa] = nullptr;
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for (unsigned addr = mcycle; addr <= hpmcounter31; ++addr) csr_wr_cb[addr] = nullptr;
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for (unsigned addr = mcycle; addr <= hpmcounter31; ++addr) csr_wr_cb[addr] = nullptr;
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for (unsigned addr = mcycleh; addr <= hpmcounter31h; ++addr) csr_wr_cb[addr] = nullptr;
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for (unsigned addr = mcycleh; addr <= hpmcounter31h; ++addr) csr_wr_cb[addr] = nullptr;
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// special handling
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// special handling
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@ -462,6 +458,9 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
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csr_rd_cb[addr] = &riscv_hart_m_p<BASE>::read_reg;
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csr_rd_cb[addr] = &riscv_hart_m_p<BASE>::read_reg;
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csr_wr_cb[addr] = &riscv_hart_m_p<BASE>::write_reg;
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csr_wr_cb[addr] = &riscv_hart_m_p<BASE>::write_reg;
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}
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}
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// read-only registers
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csr_rd_cb[misa] = &riscv_hart_m_p<BASE>::read_reg;
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csr_wr_cb[misa] = nullptr;
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}
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}
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template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
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template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
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