DBT-RISE/DBT-RISE-TGC
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update vm_tgc_c due reworked CoreDSL generator

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Eyck Jentzsch
2022-05-11 18:52:15 +02:00
parent 9db4e3fd87
commit e382217e04
1 changed files with 1 additions and 1 deletions
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src/vm/interp/vm_tgc_c.cpp
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@@ -1921,7 +1921,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction // execute instruction
try { try {
{ {
if((rd % traits::RFS) != 0) *(X+rd) = (uint32_t)(int32_t)sext<6>(imm); if((rd % traits::RFS) != 0) *(X+rd % traits::RFS) = (int8_t)sext<6>(imm);
} }
} catch(...){} } catch(...){}
} }