DBT-RISE
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DBT-RISE-TGC
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use marchid in platform

This commit is contained in:
Eyck Jentzsch 2021-09-30 19:27:03 +02:00
parent 4186723d37
commit d78fcc48e5
3 changed files with 4 additions and 4 deletions
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4
incl/iss/arch/riscv_hart_m_p.h
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@ -307,7 +307,7 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
// reset values
csr[misa] = traits<BASE>::MISA_VAL;
csr[mvendorid] = 0x669;
csr[marchid] = 0x80000003;
csr[marchid] = traits<BASE>::MARCHID_VAL;
csr[mimpid] = 1;
uart_buf.str("");
@ -922,7 +922,7 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception
switch(cause){
case 0:
csr[mtval] = instr;
csr[mtval] = addr;
break;
case 2:
csr[mtval] = (instr & 0x3)==3?instr:instr&0xffff;

2
incl/iss/arch/riscv_hart_msu_vp.h
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@ -419,7 +419,7 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
// reset values
csr[misa] = traits<BASE>::MISA_VAL;
csr[mvendorid] = 0x669;
csr[marchid] = 0x80000003;
csr[marchid] = traits<BASE>::MARCHID_VAL;
csr[mimpid] = 1;
uart_buf.str("");

2
incl/iss/arch/riscv_hart_mu_p.h
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@ -349,7 +349,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
// reset values
csr[misa] = traits<BASE>::MISA_VAL;
csr[mvendorid] = 0x669;
csr[marchid] = 0x80000004;
csr[marchid] = traits<BASE>::MARCHID_VAL;
csr[mimpid] = 1;
csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file