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cf7b62a3f9
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@ -67,6 +67,7 @@ set_target_properties(${PROJECT_NAME} PROPERTIES
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if(SystemC_FOUND)
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if(SystemC_FOUND)
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add_library(${PROJECT_NAME}_sc src/sysc/core_complex.cpp)
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add_library(${PROJECT_NAME}_sc src/sysc/core_complex.cpp)
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target_compile_definitions(${PROJECT_NAME}_sc PUBLIC WITH_SYSTEMC)
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target_compile_definitions(${PROJECT_NAME}_sc PUBLIC WITH_SYSTEMC)
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target_compile_definitions(${PROJECT_NAME}_sc PRIVATE CORE_${CORE_NAME})
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target_include_directories(${PROJECT_NAME}_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
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target_include_directories(${PROJECT_NAME}_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
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if(SCV_FOUND)
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if(SCV_FOUND)
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@ -87,7 +88,7 @@ endif()
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project(tgc-sim)
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project(tgc-sim)
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add_executable(${PROJECT_NAME} src/main.cpp)
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add_executable(${PROJECT_NAME} src/main.cpp)
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# This sets the include directory for the reference project. This is the -I flag in gcc.
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# This sets the include directory for the reference project. This is the -I flag in gcc.
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target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
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if(WITH_LLVM)
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if(WITH_LLVM)
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target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
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target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
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target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
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target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
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@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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Core TGF_B provides RV32I {
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Core TGC_B provides RV32I {
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architectural_state {
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architectural_state {
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unsigned XLEN=32;
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unsigned XLEN=32;
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unsigned PCLEN=32;
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unsigned PCLEN=32;
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@ -14,7 +14,7 @@ Core TGF_B provides RV32I {
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}
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}
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}
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}
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Core TGF_C provides RV32I, RV32M, RV32IC {
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Core TGC_C provides RV32I, RV32M, RV32IC {
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architectural_state {
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architectural_state {
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unsigned XLEN=32;
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unsigned XLEN=32;
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unsigned PCLEN=32;
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unsigned PCLEN=32;
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@ -25,3 +25,13 @@ Core TGF_C provides RV32I, RV32M, RV32IC {
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unsigned PGMASK = 0xfff; //PGSIZE-1
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unsigned PGMASK = 0xfff; //PGSIZE-1
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}
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}
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}
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}
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Core TGC_D provides RV32I, RV32M, RV32IC {
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architectural_state {
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unsigned XLEN=32;
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unsigned PCLEN=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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unsigned MISA_VAL = 0b01000000000000000001000100000100;
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}
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}
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@ -1 +1 @@
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/tgf_b.h
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/tgc_*.h
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@ -30,8 +30,8 @@
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*
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*
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*******************************************************************************/
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*******************************************************************************/
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#ifndef _TGF_C_H_
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#ifndef _TGC_C_H_
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#define _TGF_C_H_
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#define _TGC_C_H_
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#include <array>
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#include <array>
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#include <iss/arch/traits.h>
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#include <iss/arch/traits.h>
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@ -41,11 +41,11 @@
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namespace iss {
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namespace iss {
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namespace arch {
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namespace arch {
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struct tgf_c;
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struct tgc_c;
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template <> struct traits<tgf_c> {
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template <> struct traits<tgc_c> {
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constexpr static char const* const core_type = "TGF_C";
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constexpr static char const* const core_type = "TGC_C";
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static constexpr std::array<const char*, 35> reg_names{
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static constexpr std::array<const char*, 35> reg_names{
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{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
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{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
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@ -53,7 +53,7 @@ template <> struct traits<tgf_c> {
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static constexpr std::array<const char*, 35> reg_aliases{
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static constexpr std::array<const char*, 35> reg_aliases{
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{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
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{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
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enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, eei_aligned_addresses=1, MUL_LEN=64};
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enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, eei_aligned_addresses=1, MUL_LEN=64};
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constexpr static unsigned FP_REGS_SIZE = 0;
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constexpr static unsigned FP_REGS_SIZE = 0;
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@ -179,15 +179,15 @@ template <> struct traits<tgf_c> {
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};
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};
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};
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};
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struct tgf_c: public arch_if {
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struct tgc_c: public arch_if {
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using virt_addr_t = typename traits<tgf_c>::virt_addr_t;
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using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
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using phys_addr_t = typename traits<tgf_c>::phys_addr_t;
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using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
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using reg_t = typename traits<tgf_c>::reg_t;
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using reg_t = typename traits<tgc_c>::reg_t;
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using addr_t = typename traits<tgf_c>::addr_t;
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using addr_t = typename traits<tgc_c>::addr_t;
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tgf_c();
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tgc_c();
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~tgf_c();
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~tgc_c();
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void reset(uint64_t address=0) override;
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void reset(uint64_t address=0) override;
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@ -208,9 +208,9 @@ struct tgf_c: public arch_if {
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inline uint64_t stop_code() { return interrupt_sim; }
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inline uint64_t stop_code() { return interrupt_sim; }
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inline phys_addr_t v2p(const iss::addr_t& addr){
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inline phys_addr_t v2p(const iss::addr_t& addr){
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if (addr.space != traits<tgf_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
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if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
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addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
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addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
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return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf_c>::addr_mask);
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return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
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} else
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} else
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return virt2phys(addr);
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return virt2phys(addr);
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}
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}
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@ -223,7 +223,7 @@ struct tgf_c: public arch_if {
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protected:
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protected:
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#pragma pack(push, 1)
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#pragma pack(push, 1)
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struct TGF_C_regs {
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struct TGC_C_regs {
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uint32_t X0 = 0;
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uint32_t X0 = 0;
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uint32_t X1 = 0;
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uint32_t X1 = 0;
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uint32_t X2 = 0;
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uint32_t X2 = 0;
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@ -275,4 +275,4 @@ protected:
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}
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}
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}
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}
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#endif /* _TGF_C_H_ */
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#endif /* _TGC_C_H_ */
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@ -1 +1 @@
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/tgf_b.cpp
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/tgc_*.cpp
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@ -32,26 +32,26 @@
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#include "util/ities.h"
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#include "util/ities.h"
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#include <util/logging.h>
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#include <util/logging.h>
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#include <iss/arch/tgf_c.h>
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#include <iss/arch/tgc_c.h>
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#include <cstdio>
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#include <cstdio>
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#include <cstring>
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#include <cstring>
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#include <fstream>
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#include <fstream>
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using namespace iss::arch;
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using namespace iss::arch;
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constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_c>::reg_names;
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constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgc_c>::reg_names;
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constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_c>::reg_aliases;
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constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
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constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
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constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
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constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
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constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
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tgf_c::tgf_c() {
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tgc_c::tgc_c() {
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reg.icount = 0;
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reg.icount = 0;
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}
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}
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tgf_c::~tgf_c() = default;
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tgc_c::~tgc_c() = default;
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void tgf_c::reset(uint64_t address) {
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void tgc_c::reset(uint64_t address) {
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for(size_t i=0; i<traits<tgf_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf_c>::reg_t),0));
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for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgc_c>::reg_t),0));
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reg.PC=address;
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reg.PC=address;
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reg.NEXT_PC=reg.PC;
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reg.NEXT_PC=reg.PC;
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reg.PRIV=0x3;
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reg.PRIV=0x3;
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@ -59,11 +59,11 @@ void tgf_c::reset(uint64_t address) {
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reg.icount=0;
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reg.icount=0;
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}
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}
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uint8_t *tgf_c::get_regs_base_ptr() {
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uint8_t *tgc_c::get_regs_base_ptr() {
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return reinterpret_cast<uint8_t*>(®);
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return reinterpret_cast<uint8_t*>(®);
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}
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}
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tgf_c::phys_addr_t tgf_c::virt2phys(const iss::addr_t &pc) {
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tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
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return phys_addr_t(pc); // change logical address to physical address
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return phys_addr_t(pc); // change logical address to physical address
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}
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}
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14
src/main.cpp
14
src/main.cpp
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@ -36,10 +36,14 @@
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#include <boost/lexical_cast.hpp>
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#include <boost/lexical_cast.hpp>
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#include <boost/program_options.hpp>
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#include <boost/program_options.hpp>
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#include <iss/arch/riscv_hart_m_p.h>
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#include <iss/arch/riscv_hart_m_p.h>
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#ifdef WITH_TGF_B
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#ifdef CORE_TGC_C
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#include <iss/arch/tgf_b.h>
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#include "iss/arch/tgc_c.h"
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using core_type = iss::arch::tgc_c;
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#endif
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#ifdef CORE_TGC_D
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#include "iss/arch/tgc_d.h"
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using core_type = iss::arch::tgc_d;
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#endif
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#endif
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#include <iss/arch/tgf_c.h>
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#ifdef WITH_LLVM
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#ifdef WITH_LLVM
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#include <iss/llvm/jit_helper.h>
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#include <iss/llvm/jit_helper.h>
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#endif
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#endif
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@ -139,7 +143,7 @@ int main(int argc, char *argv[]) {
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#endif
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#endif
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if (isa_opt == "tgf_c") {
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if (isa_opt == "tgf_c") {
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std::tie(cpu, vm) =
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std::tie(cpu, vm) =
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create_cpu<iss::arch::tgf_c>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
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create_cpu<core_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
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} else {
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} else {
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LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
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LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
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return 127;
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return 127;
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@ -179,7 +183,7 @@ int main(int argc, char *argv[]) {
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}
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}
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uint64_t start_address = 0;
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uint64_t start_address = 0;
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if (clim.count("mem"))
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if (clim.count("mem"))
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vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::tgf_c>::MEM);
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vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<core_type>::MEM);
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if (clim.count("elf"))
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if (clim.count("elf"))
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for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
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for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
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auto start_addr = vm->get_arch()->load_file(input);
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auto start_addr = vm->get_arch()->load_file(input);
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@ -32,7 +32,14 @@
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#include "sysc/core_complex.h"
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#include "sysc/core_complex.h"
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#include "iss/arch/riscv_hart_m_p.h"
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#include "iss/arch/riscv_hart_m_p.h"
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#include "iss/arch/tgf_c.h"
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#ifdef CORE_TGC_C
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#include "iss/arch/tgc_c.h"
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using core_type = iss::arch::tgc_c;
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#endif
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#ifdef CORE_TGC_D
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#include "iss/arch/tgc_d.h"
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using core_type = iss::arch::tgc_d;
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#endif
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#include "iss/debugger/encoderdecoder.h"
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#include "iss/debugger/encoderdecoder.h"
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#include "iss/debugger/gdb_session.h"
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#include "iss/debugger/gdb_session.h"
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#include "iss/debugger/server.h"
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#include "iss/debugger/server.h"
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@ -59,7 +66,6 @@ namespace {
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iss::debugger::encoder_decoder encdec;
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iss::debugger::encoder_decoder encdec;
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}
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}
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using core_type = iss::arch::tgf_c;
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namespace {
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namespace {
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@ -1 +1 @@
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/vm_tgf_b.cpp
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/vm_tgc_*.cpp
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@ -31,7 +31,7 @@
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*******************************************************************************/
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*******************************************************************************/
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#include "../fp_functions.h"
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#include "../fp_functions.h"
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#include <iss/arch/tgf_c.h>
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#include <iss/arch/tgc_c.h>
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#include <iss/arch/riscv_hart_m_p.h>
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#include <iss/arch/riscv_hart_m_p.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/server.h>
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#include <iss/debugger/server.h>
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@ -50,7 +50,7 @@
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namespace iss {
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namespace iss {
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namespace interp {
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namespace interp {
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namespace tgf_c {
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namespace tgc_c {
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using namespace iss::arch;
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using namespace iss::arch;
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using namespace iss::debugger;
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using namespace iss::debugger;
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@ -3542,8 +3542,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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} // namespace mnrv32
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} // namespace mnrv32
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template <>
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template <>
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std::unique_ptr<vm_if> create<arch::tgf_c>(arch::tgf_c *core, unsigned short port, bool dump) {
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std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
|
||||||
auto ret = new tgf_c::vm_impl<arch::tgf_c>(*core, dump);
|
auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
|
||||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
||||||
return std::unique_ptr<vm_if>(ret);
|
return std::unique_ptr<vm_if>(ret);
|
||||||
}
|
}
|
Loading…
Reference in New Issue