DBT-RISE/DBT-RISE-TGC
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update names

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This commit is contained in:
Eyck Jentzsch
2021-05-13 15:38:33 +02:00
parent f2bf6d682a
commit cf7b62a3f9
10 changed files with 67 additions and 46 deletions
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14
gen_input/TGFS.core_desc
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@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGF_B provides RV32I {
Core TGC_B provides RV32I {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
@ -14,7 +14,7 @@ Core TGF_B provides RV32I {
}
}
Core TGF_C provides RV32I, RV32M, RV32IC {
Core TGC_C provides RV32I, RV32M, RV32IC {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
@ -25,3 +25,13 @@ Core TGF_C provides RV32I, RV32M, RV32IC {
unsigned PGMASK = 0xfff; //PGSIZE-1
}
}
Core TGC_D provides RV32I, RV32M, RV32IC {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
}
}