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DBT-RISE-TGC
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fixes according to fixed generator

This commit is contained in:
Eyck Jentzsch 2023-03-26 14:44:15 +02:00
parent d881cb6e63
commit c5465bf9e2
1 changed files with 45 additions and 50 deletions
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93
src/vm/interp/vm_tgc_c.cpp
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@ -363,7 +363,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = (int32_t)imm; *(X+rd) = (uint32_t)((int32_t)imm);
} }
} }
} }
@ -448,7 +448,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
uint32_t new_pc = (*(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm)) & ~ 0x1; uint32_t new_pc = (*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 0x1;
if(new_pc % traits::INSTR_ALIGNMENT) { if(new_pc % traits::INSTR_ALIGNMENT) {
raise(0, 0); raise(0, 0);
} }
@ -483,7 +483,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
if(*(X+rs1 % traits::RFS) == *(X+rs2 % traits::RFS)) { if(*(X+rs1) == *(X+rs2)) {
if(imm % traits::INSTR_ALIGNMENT) { if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0); raise(0, 0);
} }
@ -516,7 +516,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
if(*(X+rs1 % traits::RFS) != *(X+rs2 % traits::RFS)) { if(*(X+rs1) != *(X+rs2)) {
if(imm % traits::INSTR_ALIGNMENT) { if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0); raise(0, 0);
} }
@ -549,7 +549,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
if((int32_t)*(X+rs1 % traits::RFS) < (int32_t)*(X+rs2 % traits::RFS)) { if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) {
if(imm % traits::INSTR_ALIGNMENT) { if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0); raise(0, 0);
} }
@ -582,7 +582,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
if((int32_t)*(X+rs1 % traits::RFS) >= (int32_t)*(X+rs2 % traits::RFS)) { if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) {
if(imm % traits::INSTR_ALIGNMENT) { if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0); raise(0, 0);
} }
@ -615,7 +615,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
if(*(X+rs1 % traits::RFS) < *(X+rs2 % traits::RFS)) { if(*(X+rs1) < *(X+rs2)) {
if(imm % traits::INSTR_ALIGNMENT) { if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0); raise(0, 0);
} }
@ -648,7 +648,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
if(*(X+rs1 % traits::RFS) >= *(X+rs2 % traits::RFS)) { if(*(X+rs1) >= *(X+rs2)) {
if(imm % traits::INSTR_ALIGNMENT) { if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0); raise(0, 0);
} }
@ -681,12 +681,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
int8_t read_res = super::template read_mem<int8_t>(traits::MEM, load_address); int8_t read_res = super::template read_mem<int8_t>(traits::MEM, load_address);
if(this->core.trap_state>=0x80000000UL) goto TRAP_LB; if(this->core.trap_state>=0x80000000UL) goto TRAP_LB;
int8_t res = (int8_t)read_res; int8_t res = (int8_t)read_res;
if(rd != 0) { if(rd != 0) {
*(X+rd) = (int32_t)res; *(X+rd) = (uint32_t)res;
} }
} }
} }
@ -712,12 +712,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
int16_t read_res = super::template read_mem<int16_t>(traits::MEM, load_address); int16_t read_res = super::template read_mem<int16_t>(traits::MEM, load_address);
if(this->core.trap_state>=0x80000000UL) goto TRAP_LH; if(this->core.trap_state>=0x80000000UL) goto TRAP_LH;
int16_t res = (int16_t)read_res; int16_t res = (int16_t)read_res;
if(rd != 0) { if(rd != 0) {
*(X+rd) = (int32_t)res; *(X+rd) = (uint32_t)res;
} }
} }
} }
@ -743,12 +743,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address); int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address);
if(this->core.trap_state>=0x80000000UL) goto TRAP_LW; if(this->core.trap_state>=0x80000000UL) goto TRAP_LW;
int32_t res = (int32_t)read_res; int32_t res = (int32_t)read_res;
if(rd != 0) { if(rd != 0) {
*(X+rd) = (int32_t)res; *(X+rd) = (uint32_t)res;
} }
} }
} }
@ -774,7 +774,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
uint8_t read_res = super::template read_mem<uint8_t>(traits::MEM, load_address); uint8_t read_res = super::template read_mem<uint8_t>(traits::MEM, load_address);
if(this->core.trap_state>=0x80000000UL) goto TRAP_LBU; if(this->core.trap_state>=0x80000000UL) goto TRAP_LBU;
uint8_t res = (uint8_t)read_res; uint8_t res = (uint8_t)read_res;
@ -805,7 +805,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
uint32_t load_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
uint16_t read_res = super::template read_mem<uint16_t>(traits::MEM, load_address); uint16_t read_res = super::template read_mem<uint16_t>(traits::MEM, load_address);
if(this->core.trap_state>=0x80000000UL) goto TRAP_LHU; if(this->core.trap_state>=0x80000000UL) goto TRAP_LHU;
uint16_t res = (uint16_t)read_res; uint16_t res = (uint16_t)read_res;
@ -836,8 +836,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
super::template write_mem<uint8_t>(traits::MEM, store_address, (int8_t)*(X+rs2 % traits::RFS)); super::template write_mem<uint8_t>(traits::MEM, store_address, (int8_t)*(X+rs2));
if(this->core.trap_state>=0x80000000UL) goto TRAP_SB; if(this->core.trap_state>=0x80000000UL) goto TRAP_SB;
} }
} }
@ -863,8 +863,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
super::template write_mem<uint16_t>(traits::MEM, store_address, (int16_t)*(X+rs2 % traits::RFS)); super::template write_mem<uint16_t>(traits::MEM, store_address, (int16_t)*(X+rs2));
if(this->core.trap_state>=0x80000000UL) goto TRAP_SH; if(this->core.trap_state>=0x80000000UL) goto TRAP_SH;
} }
} }
@ -890,8 +890,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
uint32_t store_address = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
super::template write_mem<uint32_t>(traits::MEM, store_address, (int32_t)*(X+rs2 % traits::RFS)); super::template write_mem<uint32_t>(traits::MEM, store_address, (int32_t)*(X+rs2));
if(this->core.trap_state>=0x80000000UL) goto TRAP_SW; if(this->core.trap_state>=0x80000000UL) goto TRAP_SW;
} }
} }
@ -918,7 +918,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1 % traits::RFS) + (int16_t)sext<12>(imm); *(X+rd) = *(X+rs1) + (int16_t)sext<12>(imm);
} }
} }
} }
@ -945,7 +945,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = ((int32_t)*(X+rs1 % traits::RFS) < (int16_t)sext<12>(imm))? 1 : 0; *(X+rd) = ((int32_t)*(X+rs1) < (int16_t)sext<12>(imm))? 1 : 0;
} }
} }
} }
@ -972,7 +972,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = (*(X+rs1 % traits::RFS) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0; *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0;
} }
} }
} }
@ -999,7 +999,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1 % traits::RFS) ^ (int16_t)sext<12>(imm); *(X+rd) = *(X+rs1) ^ (uint32_t)((int16_t)sext<12>(imm));
} }
} }
} }
@ -1026,7 +1026,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1 % traits::RFS) | (int16_t)sext<12>(imm); *(X+rd) = *(X+rs1) | (uint32_t)((int16_t)sext<12>(imm));
} }
} }
} }
@ -1053,7 +1053,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1 % traits::RFS) & (int16_t)sext<12>(imm); *(X+rd) = *(X+rs1) & (uint32_t)((int16_t)sext<12>(imm));
} }
} }
} }
@ -1080,7 +1080,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1 % traits::RFS) << shamt; *(X+rd) = *(X+rs1) << shamt;
} }
} }
} }
@ -1107,7 +1107,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1 % traits::RFS) >> shamt; *(X+rd) = *(X+rs1) >> shamt;
} }
} }
} }
@ -1134,7 +1134,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = (int32_t)*(X+rs1 % traits::RFS) >> shamt; *(X+rd) = (int32_t)*(X+rs1) >> shamt;
} }
} }
} }
@ -1161,7 +1161,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1 % traits::RFS) + *(X+rs2 % traits::RFS); *(X+rd) = *(X+rs1) + *(X+rs2);
} }
} }
} }
@ -1188,7 +1188,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1 % traits::RFS) - *(X+rs2 % traits::RFS); *(X+rd) = *(X+rs1) - *(X+rs2);
} }
} }
} }
@ -1215,7 +1215,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1 % traits::RFS) << (*(X+rs2 % traits::RFS) & (traits::XLEN - 1)); *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1));
} }
} }
} }
@ -1237,17 +1237,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4; *NEXT_PC = *PC + 4;
// execute instruction // execute instruction
{ {
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
}
else {
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2); raise(0, 2);
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = (int32_t)*(X+rs1 % traits::RFS) < (int32_t)*(X+rs2 % traits::RFS)? 1 : 0; *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0;
}
} }
} }
} }
@ -1274,7 +1269,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = (uint32_t)*(X+rs1 % traits::RFS) < (uint32_t)*(X+rs2 % traits::RFS)? 1 : 0; *(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0;
} }
} }
} }
@ -1301,7 +1296,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1 % traits::RFS) ^ *(X+rs2 % traits::RFS); *(X+rd) = *(X+rs1) ^ *(X+rs2);
} }
} }
} }
@ -1328,7 +1323,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1 % traits::RFS) >> (*(X+rs2 % traits::RFS) & (traits::XLEN - 1)); *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
} }
} }
} }
@ -1355,7 +1350,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = (int32_t)*(X+rs1 % traits::RFS) >> (*(X+rs2 % traits::RFS) & (traits::XLEN - 1)); *(X+rd) = (int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
} }
} }
} }
@ -1382,7 +1377,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1 % traits::RFS) | *(X+rs2 % traits::RFS); *(X+rd) = *(X+rs1) | *(X+rs2);
} }
} }
} }
@ -1409,7 +1404,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1 % traits::RFS) & *(X+rs2 % traits::RFS); *(X+rd) = *(X+rs1) & *(X+rs2);
} }
} }
} }
@ -1509,7 +1504,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2); raise(0, 2);
} }
else { else {
uint32_t xrs1 = *(X+rs1 % traits::RFS); uint32_t xrs1 = *(X+rs1);
if(rd != 0) { if(rd != 0) {
uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr); uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRW; if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRW;
@ -1549,7 +1544,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr); uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRS; if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRS;
uint32_t xrd = read_res; uint32_t xrd = read_res;
uint32_t xrs1 = *(X+rs1 % traits::RFS); uint32_t xrs1 = *(X+rs1);
if(rs1 != 0) { if(rs1 != 0) {
super::template write_mem<uint32_t>(traits::CSR, csr, xrd | xrs1); super::template write_mem<uint32_t>(traits::CSR, csr, xrd | xrs1);
if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRS; if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRS;
@ -1584,7 +1579,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr); uint32_t read_res = super::template read_mem<uint32_t>(traits::CSR, csr);
if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRC; if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRC;
uint32_t xrd = read_res; uint32_t xrd = read_res;
uint32_t xrs1 = *(X+rs1 % traits::RFS); uint32_t xrs1 = *(X+rs1);
if(rs1 != 0) { if(rs1 != 0) {
super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ xrs1); super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ xrs1);
if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRC; if(this->core.trap_state>=0x80000000UL) goto TRAP_CSRRC;