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DBT-RISE-TGC
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apply clang-format 10 fixes

This commit is contained in:
Eyck Jentzsch 2023-12-01 14:50:54 +01:00
parent e921201f7b
commit bc4ea30815
6 changed files with 17 additions and 9 deletions
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1
src/iss/arch/hwl.h
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@ -35,6 +35,7 @@
#ifndef _RISCV_HART_M_P_HWL_H #ifndef _RISCV_HART_M_P_HWL_H
#define _RISCV_HART_M_P_HWL_H #define _RISCV_HART_M_P_HWL_H
#include "riscv_hart_common.h"
#include <iss/vm_types.h> #include <iss/vm_types.h>
namespace iss { namespace iss {

3
src/iss/arch/riscv_hart_m_p.h
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@ -824,7 +824,8 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
x |= 0x80; // set pll lock upon writing x |= 0x80; // set pll lock upon writing
return iss::Ok; return iss::Ok;
} break; } break;
default: {} default: {
}
} }
} break; } break;
case traits<BASE>::CSR: { case traits<BASE>::CSR: {

3
src/iss/arch/riscv_hart_msu_vp.h
View File

@ -804,7 +804,8 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
x |= 0x80; // set pll lock upon writing x |= 0x80; // set pll lock upon writing
return iss::Ok; return iss::Ok;
} break; } break;
default: {} default: {
}
} }
} break; } break;
case traits<BASE>::CSR: { case traits<BASE>::CSR: {

3
src/iss/arch/riscv_hart_mu_p.h
View File

@ -1007,7 +1007,8 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
x |= 0x80; // set pll lock upon writing x |= 0x80; // set pll lock upon writing
return iss::Ok; return iss::Ok;
} break; } break;
default: {} default: {
}
} }
} break; } break;
case traits<BASE>::CSR: { case traits<BASE>::CSR: {

8
src/sysc/core_complex.cpp
View File

@ -430,7 +430,9 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t* const data,
dbus_inc += incr; dbus_inc += incr;
} }
SCCTRACE(this->name()) << "[local time: " << delay << "]: finish read_mem(0x" << std::hex << addr << ") : 0x" SCCTRACE(this->name()) << "[local time: " << delay << "]: finish read_mem(0x" << std::hex << addr << ") : 0x"
<< (length == 4 ? *(uint32_t*)data : length == 2 ? *(uint16_t*)data : (unsigned)*data); << (length == 4 ? *(uint32_t*)data
: length == 2 ? *(uint16_t*)data
: (unsigned)*data);
if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) { if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
return false; return false;
} }
@ -475,7 +477,9 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t* cons
else else
dbus_inc += (delay - quantum_keeper.get_local_time()) / curr_clk; dbus_inc += (delay - quantum_keeper.get_local_time()) / curr_clk;
SCCTRACE() << "[local time: " << delay << "]: finish write_mem(0x" << std::hex << addr << ") : 0x" SCCTRACE() << "[local time: " << delay << "]: finish write_mem(0x" << std::hex << addr << ") : 0x"
<< (length == 4 ? *(uint32_t*)data : length == 2 ? *(uint16_t*)data : (unsigned)*data); << (length == 4 ? *(uint32_t*)data
: length == 2 ? *(uint16_t*)data
: (unsigned)*data);
if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) { if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
return false; return false;
} }

2
src/vm/interp/vm_tgc5c.cpp
View File

@ -2689,9 +2689,9 @@ std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short por
} // namespace interp } // namespace interp
} // namespace iss } // namespace iss
#include <iss/factory.h>
#include <iss/arch/riscv_hart_m_p.h> #include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_mu_p.h> #include <iss/arch/riscv_hart_mu_p.h>
#include <iss/factory.h>
namespace iss { namespace iss {
namespace { namespace {
volatile std::array<bool, 2> dummy = { volatile std::array<bool, 2> dummy = {