diff --git a/src/iss/arch/hwl.h b/src/iss/arch/hwl.h
index c0b5185..2da5f3a 100644
--- a/src/iss/arch/hwl.h
+++ b/src/iss/arch/hwl.h
@@ -35,6 +35,7 @@
 #ifndef _RISCV_HART_M_P_HWL_H
 #define _RISCV_HART_M_P_HWL_H
 
+#include "riscv_hart_common.h"
 #include <iss/vm_types.h>
 
 namespace iss {
diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index e4b9c7c..e22c970 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -824,7 +824,8 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
                 x |= 0x80; // set pll lock upon writing
                 return iss::Ok;
             } break;
-            default: {}
+            default: {
+            }
             }
         } break;
         case traits<BASE>::CSR: {
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index ca0bfd9..2a4bc90 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -804,7 +804,8 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                 x |= 0x80; // set pll lock upon writing
                 return iss::Ok;
             } break;
-            default: {}
+            default: {
+            }
             }
         } break;
         case traits<BASE>::CSR: {
@@ -1227,9 +1228,9 @@ template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_har
                 break;
             } else if(!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
                 break;
-            } else if(type == (iss::access_type::FETCH ? !(pte & PTE_X)
-                                                       : type == iss::access_type::READ ? !(pte & PTE_R) && !(mxr && (pte & PTE_X))
-                                                                                        : !((pte & PTE_R) && (pte & PTE_W)))) {
+            } else if(type == (iss::access_type::FETCH          ? !(pte & PTE_X)
+                               : type == iss::access_type::READ ? !(pte & PTE_R) && !(mxr && (pte & PTE_X))
+                                                                : !((pte & PTE_R) && (pte & PTE_W)))) {
                 break;
             } else if((ppn & ((reg_t(1) << ptshift) - 1)) != 0) {
                 break;
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index 9255fb7..7aa8b21 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -1007,7 +1007,8 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                 x |= 0x80; // set pll lock upon writing
                 return iss::Ok;
             } break;
-            default: {}
+            default: {
+            }
             }
         } break;
         case traits<BASE>::CSR: {
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index e7cfbbc..7b3e601 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -430,7 +430,9 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t* const data,
                 dbus_inc += incr;
         }
         SCCTRACE(this->name()) << "[local time: " << delay << "]: finish read_mem(0x" << std::hex << addr << ") : 0x"
-                               << (length == 4 ? *(uint32_t*)data : length == 2 ? *(uint16_t*)data : (unsigned)*data);
+                               << (length == 4   ? *(uint32_t*)data
+                                   : length == 2 ? *(uint16_t*)data
+                                                 : (unsigned)*data);
         if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }
@@ -475,7 +477,9 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t* cons
         else
             dbus_inc += (delay - quantum_keeper.get_local_time()) / curr_clk;
         SCCTRACE() << "[local time: " << delay << "]: finish write_mem(0x" << std::hex << addr << ") : 0x"
-                   << (length == 4 ? *(uint32_t*)data : length == 2 ? *(uint16_t*)data : (unsigned)*data);
+                   << (length == 4   ? *(uint32_t*)data
+                       : length == 2 ? *(uint16_t*)data
+                                     : (unsigned)*data);
         if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }
diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp
index be65682..99419ac 100644
--- a/src/vm/interp/vm_tgc5c.cpp
+++ b/src/vm/interp/vm_tgc5c.cpp
@@ -2689,9 +2689,9 @@ std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short por
 } // namespace interp
 } // namespace iss
 
-#include <iss/factory.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {