DBT-RISE/DBT-RISE-TGC
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apply clang-format 10 fixes

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This commit is contained in:
Eyck Jentzsch
2023-12-01 14:50:54 +01:00
parent e921201f7b
commit bc4ea30815
6 changed files with 17 additions and 9 deletions
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1
src/iss/arch/hwl.h
View File

@ -35,6 +35,7 @@
#ifndef _RISCV_HART_M_P_HWL_H
#define _RISCV_HART_M_P_HWL_H
#include "riscv_hart_common.h"
#include <iss/vm_types.h>
namespace iss {

3
src/iss/arch/riscv_hart_m_p.h
View File

@ -824,7 +824,8 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
x |= 0x80; // set pll lock upon writing
return iss::Ok;
} break;
default: {}
default: {
}
}
} break;
case traits<BASE>::CSR: {

9
src/iss/arch/riscv_hart_msu_vp.h
View File

@ -804,7 +804,8 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
x |= 0x80; // set pll lock upon writing
return iss::Ok;
} break;
default: {}
default: {
}
}
} break;
case traits<BASE>::CSR: {
@ -1227,9 +1228,9 @@ template <typename BASE> typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_har
break;
} else if(!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
break;
} else if(type == (iss::access_type::FETCH ? !(pte & PTE_X)
: type == iss::access_type::READ ? !(pte & PTE_R) && !(mxr && (pte & PTE_X))
: !((pte & PTE_R) && (pte & PTE_W)))) {
} else if(type == (iss::access_type::FETCH ? !(pte & PTE_X)
: type == iss::access_type::READ ? !(pte & PTE_R) && !(mxr && (pte & PTE_X))
: !((pte & PTE_R) && (pte & PTE_W)))) {
break;
} else if((ppn & ((reg_t(1) << ptshift) - 1)) != 0) {
break;

3
src/iss/arch/riscv_hart_mu_p.h
View File

@ -1007,7 +1007,8 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
x |= 0x80; // set pll lock upon writing
return iss::Ok;
} break;
default: {}
default: {
}
}
} break;
case traits<BASE>::CSR: {