DBT-RISE/DBT-RISE-TGC
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applies clang-format

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This commit is contained in:
Eyck Jentzsch
2024-08-17 13:33:14 +02:00
parent 0996d15bd4
commit bb4e2766d1
9 changed files with 4185 additions and 4197 deletions
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55
src/sysc/core_complex.cpp
View File

@ -42,7 +42,6 @@
#include <iss/plugin/loader.h>
#endif
#include "sc_core_adapter_if.h"
#include <iss/arch/tgc_mapper.h>
#include <scc/report.h>
#include <util/ities.h>
#include <iostream>
@ -208,8 +207,7 @@ core_complex<BUSWIDTH>::core_complex(sc_module_name const& name)
}
#endif
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::init() {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::init() {
trc = new core_trace();
ibus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
auto lut_entry = fetch_lut.getEntry(start);
@ -254,19 +252,16 @@ void core_complex<BUSWIDTH>::init() {
#endif
}
template <unsigned int BUSWIDTH>
core_complex<BUSWIDTH>::~core_complex() {
template <unsigned int BUSWIDTH> core_complex<BUSWIDTH>::~core_complex() {
delete cpu;
delete trc;
for(auto* p : plugin_list)
delete p;
}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::trace(sc_trace_file* trf) const {}
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::trace(sc_trace_file* trf) const {}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::before_end_of_elaboration() {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::before_end_of_elaboration() {
SCCDEBUG(SCMOD) << "instantiating iss::arch::tgf with " << GET_PROP_VALUE(backend) << " backend";
// cpu = scc::make_unique<core_wrapper>(this);
cpu = new core_wrapper(this);
@ -307,8 +302,7 @@ void core_complex<BUSWIDTH>::before_end_of_elaboration() {
}
}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::start_of_simulation() {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::start_of_simulation() {
// quantum_keeper.reset();
if(GET_PROP_VALUE(elf_file).size() > 0) {
istringstream is(GET_PROP_VALUE(elf_file));
@ -331,8 +325,7 @@ void core_complex<BUSWIDTH>::start_of_simulation() {
}
}
template <unsigned int BUSWIDTH>
bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_str) {
template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_str) {
if(trc->m_db == nullptr)
return false;
if(trc->tr_handle.is_active())
@ -346,8 +339,7 @@ bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_
return true;
}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::forward() {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::forward() {
#ifndef CWR_SYSTEMC
set_clock_period(clk_i.read());
#else
@ -356,30 +348,24 @@ void core_complex<BUSWIDTH>::forward() {
#endif
}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::set_clock_period(sc_core::sc_time period) {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::set_clock_period(sc_core::sc_time period) {
curr_clk = period;
if(period == SC_ZERO_TIME)
cpu->set_interrupt_execution(true);
}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::rst_cb() {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::rst_cb() {
if(rst_i.read())
cpu->set_interrupt_execution(true);
}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::local_irq_cb() {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::local_irq_cb() {
for(auto i = 0U; i < local_irq_i.size(); ++i) {
if(local_irq_i[i].event()) {
cpu->local_irq(16 + i, local_irq_i[i].read());
@ -387,8 +373,7 @@ void core_complex<BUSWIDTH>::local_irq_cb() {
}
}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::run() {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::run() {
wait(SC_ZERO_TIME); // separate from elaboration phase
do {
wait(SC_ZERO_TIME);
@ -406,8 +391,7 @@ void core_complex<BUSWIDTH>::run() {
sc_stop();
}
template <unsigned int BUSWIDTH>
bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
auto lut_entry = dmi_lut.getEntry(addr);
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
@ -465,8 +449,7 @@ bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* c
}
}
template <unsigned int BUSWIDTH>
bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
auto lut_entry = write_lut.getEntry(addr);
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
auto offset = addr - lut_entry.get_start_address();
@ -514,8 +497,7 @@ bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uin
}
}
template <unsigned int BUSWIDTH>
bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
tlm::tlm_generic_payload gp;
gp.set_command(tlm::TLM_READ_COMMAND);
gp.set_address(addr);
@ -525,8 +507,7 @@ bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_
return dbus->transport_dbg(gp) == length;
}
template <unsigned int BUSWIDTH>
bool core_complex<BUSWIDTH>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
write_buf.resize(length);
std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
tlm::tlm_generic_payload gp;

23
src/sysc/core_complex.h
View File

@ -33,10 +33,10 @@
#ifndef _SYSC_CORE_COMPLEX_H_
#define _SYSC_CORE_COMPLEX_H_
#include <scc/signal_opt_ports.h>
#include <scc/tick2time.h>
#include <scc/traceable.h>
#include <scc/utilities.h>
#include <scc/signal_opt_ports.h>
#include <tlm/scc/initiator_mixin.h>
#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
#ifdef CWR_SYSTEMC
@ -71,28 +71,27 @@ struct core_complex_if {
virtual ~core_complex_if() = default;
virtual bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) =0;
virtual bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) = 0;
virtual bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data) =0;
virtual bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data) = 0;
virtual bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) =0;
virtual bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) = 0;
virtual bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) =0;
virtual bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) = 0;
virtual bool disass_output(uint64_t pc, const std::string instr) =0;
virtual bool disass_output(uint64_t pc, const std::string instr) = 0;
virtual unsigned get_last_bus_cycles() =0;
virtual unsigned get_last_bus_cycles() = 0;
//! Allow quantum keeper handling
virtual void sync(uint64_t) =0;
virtual void sync(uint64_t) = 0;
virtual char const* hier_name() = 0;
scc::sc_in_opt<uint64_t> mtime_i{"mtime_i"};
};
template <unsigned int BUSWIDTH = scc::LT>
class core_complex : public sc_core::sc_module, public scc::traceable, public core_complex_if {
template <unsigned int BUSWIDTH = scc::LT> class core_complex : public sc_core::sc_module, public scc::traceable, public core_complex_if {
public:
tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>> ibus{"ibus"};
@ -208,9 +207,7 @@ public:
void set_clock_period(sc_core::sc_time period);
char const* hier_name() override {
return name();
}
char const* hier_name() override { return name(); }
protected:
void before_end_of_elaboration() override;

6
src/sysc/sc_core_adapter.h
View File

@ -55,8 +55,8 @@ public:
s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') << std::setw(sizeof(reg_t) * 2)
<< (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount + this->cycle_offset << "]";
SCCDEBUG(owner->hier_name()) << "disass: "
<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
<< std::setfill(' ') << std::left << instr << s.str();
<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t"
<< std::setw(40) << std::setfill(' ') << std::left << instr << s.str();
}
};
@ -113,7 +113,7 @@ public:
iss::status read_csr(unsigned addr, reg_t& val) override {
if((addr == iss::arch::time || addr == iss::arch::timeh)) {
uint64_t time_val = owner->mtime_i.get_interface()? owner->mtime_i.read():0;
uint64_t time_val = owner->mtime_i.get_interface() ? owner->mtime_i.read() : 0;
if(addr == iss::arch::time) {
val = static_cast<reg_t>(time_val);
} else if(addr == iss::arch::timeh) {