DBT-RISE/DBT-RISE-TGC
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applies clang-format

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This commit is contained in:
Eyck Jentzsch
2024-08-17 13:33:14 +02:00
parent 0996d15bd4
commit bb4e2766d1
9 changed files with 4185 additions and 4197 deletions
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18
src/iss/arch/riscv_hart_msu_vp.h
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@ -671,8 +671,10 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
}
return res;
} catch(trap_access& ta) {
this->reg.trap_state = (1 << 31) | ta.id;
fault_data = ta.addr;
if((access & access_type::DEBUG) == 0) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
}
return iss::Err;
}
} break;
@ -710,8 +712,10 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
}
return iss::Ok;
} catch(trap_access& ta) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
if((access & access_type::DEBUG) == 0) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
}
return iss::Err;
}
}
@ -841,8 +845,10 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
}
return iss::Ok;
} catch(trap_access& ta) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
if((access & access_type::DEBUG) == 0) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
}
return iss::Err;
}
}