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fixes constructor calls of derived riscv_hart classes

This commit is contained in:
Eyck Jentzsch 2023-09-27 07:51:49 +02:00
parent 2095ac985b
commit b7f023756e
3 changed files with 10 additions and 4 deletions
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4
src/iss/arch/hwl.h
View File

@ -46,7 +46,7 @@ public:
using this_class = hwl<BASE>; using this_class = hwl<BASE>;
using reg_t = typename BASE::reg_t; using reg_t = typename BASE::reg_t;
hwl(); hwl(feature_config cfg = feature_config{});
virtual ~hwl() = default; virtual ~hwl() = default;
protected: protected:
@ -56,7 +56,7 @@ protected:
template<typename BASE> template<typename BASE>
inline hwl<BASE>::hwl() { inline hwl<BASE>::hwl(feature_config cfg): BASE(cfg) {
for (unsigned addr = 0x800; addr < 0x803; ++addr){ for (unsigned addr = 0x800; addr < 0x803; ++addr){
this->register_custom_csr_rd(addr); this->register_custom_csr_rd(addr);
this->register_custom_csr_wr(addr); this->register_custom_csr_wr(addr);

2
src/iss/arch/riscv_hart_common.h
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@ -226,6 +226,8 @@ struct feature_config {
unsigned clic_num_trigger{0}; unsigned clic_num_trigger{0};
uint64_t tcm_base{0x10000000}; uint64_t tcm_base{0x10000000};
uint64_t tcm_size{0x8000}; uint64_t tcm_size{0x8000};
uint64_t io_address{0xf0000000};
uint64_t io_addr_mask{0xf0000000};
}; };
class trap_load_access_fault : public trap_access { class trap_load_access_fault : public trap_access {

8
src/iss/arch/wt_cache.h
View File

@ -81,7 +81,7 @@ public:
using mem_write_f = typename BASE::mem_write_f; using mem_write_f = typename BASE::mem_write_f;
using phys_addr_t = typename BASE::phys_addr_t; using phys_addr_t = typename BASE::phys_addr_t;
wt_cache(); wt_cache(feature_config cfg = feature_config{});
virtual ~wt_cache() = default; virtual ~wt_cache() = default;
unsigned size{4096}; unsigned size{4096};
@ -103,7 +103,11 @@ protected:
template<typename BASE> template<typename BASE>
inline wt_cache<BASE>::wt_cache() { inline wt_cache<BASE>::wt_cache(feature_config cfg)
:BASE(cfg)
, io_address{cfg.io_address}
, io_addr_mask{cfg.io_addr_mask}
{
auto cb = base_class::replace_mem_access( auto cb = base_class::replace_mem_access(
[this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l,d);}, [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l,d);},
[this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l,d);}); [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l,d);});