DBT-RISE/DBT-RISE-TGC
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fixes build system to handle TCC properly

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This commit is contained in:
Eyck Jentzsch
2023-07-09 22:20:50 +02:00
parent 145a0cf68b
commit b4b03f7850
8 changed files with 123 additions and 216 deletions
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17
src/sysc/sc_core_adapter.h
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@ -11,14 +11,13 @@
#include <scc/report.h>
#include <util/ities.h>
#include "core_complex.h"
#include "sc_core_adapter_if.h"
#include <iss/iss.h>
#include <iss/vm_types.h>
#include <iostream>
template<typename PLAT>
class sc_core_adapter : public PLAT {
class sc_core_adapter : public PLAT, public sc_core_adapter_if {
public:
using reg_t = typename iss::arch::traits<typename PLAT::core>::reg_t;
using phys_addr_t = typename iss::arch::traits<typename PLAT::core>::phys_addr_t;
@ -26,13 +25,15 @@ public:
sc_core_adapter(sysc::tgfs::core_complex *owner)
: owner(owner) { }
uint32_t get_mode() { return this->reg.PRIV; }
void set_mhartid(unsigned id) override { PLAT::set_mhartid(id); }
inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
uint32_t get_mode() override { return this->reg.PRIV; }
inline bool get_interrupt_execution() { return this->interrupt_sim; }
void set_interrupt_execution(bool v) override { this->interrupt_sim = v?1:0; }
heart_state_t &get_state() { return this->state; }
bool get_interrupt_execution() override { return this->interrupt_sim; }
uint64_t get_state() override { return this->state.mstatus.backing.val; }
void notify_phase(iss::arch_if::exec_phase p) override {
if (p == iss::arch_if::ISTART)
@ -113,7 +114,7 @@ public:
PLAT::wait_until(flags);
}
void local_irq(short id, bool value) {
void local_irq(short id, bool value) override {
reg_t mask = 0;
switch (id) {
case 3: // SW