DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

[WIP]

Browse Source
This commit is contained in:
Eyck Jentzsch
2020-05-31 16:41:04 +02:00
parent 10797a473d
commit abcfb75011
13 changed files with 2356 additions and 3079 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
gen_input/minres_rv.core_desc
View File

@ -22,6 +22,7 @@ Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
constants {
XLEN:=32;
PCLEN:=32;
MUL_LEN:=64;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100000101;
@ -35,6 +36,7 @@ Core RV32GC provides RV32I, RV32M, RV32A, RV32F, RV32D, RV32IC, RV32FC, RV32DC {
XLEN:=32;
FLEN:=64;
PCLEN:=32;
MUL_LEN:=64;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100101101;
@ -60,6 +62,7 @@ Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV64IC, RV32FC, RV32DC {
XLEN:=64;
FLEN:=64;
PCLEN:=64;
MUL_LEN:=128;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100101101;