update core definitions to include Zicsr and Zifencei (#276)
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@ -1 +1 @@
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Subproject commit 9e3119a8064e8515eeca7e5298f88d0d9d224458
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Subproject commit e7aaec6ad9336bd83b4da63dd0c96f8d11887661
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@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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Core TGC_B provides RV32I {
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Core TGC_B provides RV32I, Zicsr, Zifencei {
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architectural_state {
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architectural_state {
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XLEN=32;
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XLEN=32;
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// definitions for the architecture wrapper
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// definitions for the architecture wrapper
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@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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Core TGC_C provides RV32I, RV32M, RV32IC {
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Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
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architectural_state {
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architectural_state {
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XLEN=32;
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XLEN=32;
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// definitions for the architecture wrapper
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// definitions for the architecture wrapper
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@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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Core TGC_D provides RV32I, RV32M, RV32IC {
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Core TGC_D provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
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architectural_state {
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architectural_state {
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XLEN=32;
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XLEN=32;
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// definitions for the architecture wrapper
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// definitions for the architecture wrapper
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@ -62,7 +62,7 @@ InstructionSet X_RB_MAC extends RISCVBase {
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}
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}
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}
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}
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Core TGC_D_XRB_MAC provides RV32I, RV32M, RV32IC, X_RB_MAC {
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Core TGC_D_XRB_MAC provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_MAC {
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architectural_state {
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architectural_state {
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XLEN=32;
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XLEN=32;
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// definitions for the architecture wrapper
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// definitions for the architecture wrapper
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