update core definitions to include Zicsr and Zifencei (#276)

2021-10-30 12:56:31 +02:00
parent 334d3fb296
commit a20f39e847
5 changed files with 5 additions and 5 deletions
--- a/gen_input/TGC_C.core_desc
+++ b/gen_input/TGC_C.core_desc
@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVC.core_desc"

-Core TGC_C provides RV32I, RV32M, RV32IC {
+Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
    architectural_state {
        XLEN=32;
        // definitions for the architecture wrapper