update core definitions to include Zicsr and Zifencei (#276)

gen_input/TGC_B.core_desc

@@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
 
-Core TGC_B provides RV32I {
+Core TGC_B provides RV32I, Zicsr, Zifencei {
 	architectural_state {
         XLEN=32;
         // definitions for the architecture wrapper