fixes CSR access rights
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6213445bc4
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98dd329833
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@ -454,11 +454,13 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
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//csr_wr_cb[addr] = &this_class::write_csr_reg;
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}
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// common regs
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const std::array<unsigned, 8> addrs{{
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misa, mvendorid, marchid, mimpid,
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mepc, mtvec, mscratch, mtval
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}};
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for(auto addr: addrs) {
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const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
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for(auto addr: roaddrs) {
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csr_rd_cb[addr] = &this_class::read_csr_reg;
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csr_wr_cb[addr] = &this_class::write_null;
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}
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const std::array<unsigned, 4> rwaddrs{{mepc, mtvec, mscratch, mtval}};
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for(auto addr: rwaddrs) {
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csr_rd_cb[addr] = &this_class::read_csr_reg;
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csr_wr_cb[addr] = &this_class::write_csr_reg;
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}
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@ -398,12 +398,16 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
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//csr_wr_cb[addr] = &this_class::write_csr_reg;
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}
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// common regs
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const std::array<unsigned, 12> addrs{{
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misa, mvendorid, marchid, mimpid,
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const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
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for(auto addr: roaddrs) {
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csr_rd_cb[addr] = &this_class::read_csr_reg;
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csr_wr_cb[addr] = &this_class::write_null;
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}
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const std::array<unsigned, 8> rwaddrs{{
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mepc, mtvec, mscratch, mtval,
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uepc, utvec, uscratch, utval,
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}};
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for(auto addr: addrs) {
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for(auto addr: rwaddrs) {
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csr_rd_cb[addr] = &this_class::read_csr_reg;
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csr_wr_cb[addr] = &this_class::write_csr_reg;
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}
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