From 98dd329833515428237698a01e1883934356e748 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Tue, 4 Apr 2023 09:23:08 +0200
Subject: [PATCH] fixes CSR access rights

---
 src/iss/arch/riscv_hart_m_p.h  | 12 +++++++-----
 src/iss/arch/riscv_hart_mu_p.h | 10 +++++++---
 2 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index 890bf6c..5967c29 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -454,11 +454,13 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
         //csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // common regs
-    const std::array<unsigned, 8> addrs{{
-    	misa, mvendorid, marchid, mimpid,
-    	mepc, mtvec, mscratch, mtval
-    }};
-    for(auto addr: addrs) {
+    const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
+    for(auto addr: roaddrs) {
+        csr_rd_cb[addr] = &this_class::read_csr_reg;
+        csr_wr_cb[addr] = &this_class::write_null;
+    }
+    const std::array<unsigned, 4> rwaddrs{{mepc, mtvec, mscratch, mtval}};
+    for(auto addr: rwaddrs) {
         csr_rd_cb[addr] = &this_class::read_csr_reg;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index c896701..8a1ce3d 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -398,12 +398,16 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
         //csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // common regs
-    const std::array<unsigned, 12> addrs{{
-        misa, mvendorid, marchid, mimpid,
+    const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
+    for(auto addr: roaddrs) {
+        csr_rd_cb[addr] = &this_class::read_csr_reg;
+        csr_wr_cb[addr] = &this_class::write_null;
+    }
+    const std::array<unsigned, 8> rwaddrs{{
         mepc, mtvec, mscratch, mtval,
         uepc, utvec, uscratch, utval,
     }};
-    for(auto addr: addrs) {
+    for(auto addr: rwaddrs) {
         csr_rd_cb[addr] = &this_class::read_csr_reg;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
     }