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fixes CSR access rights

This commit is contained in:
Eyck Jentzsch 2023-04-04 09:23:08 +02:00
parent 6213445bc4
commit 98dd329833
2 changed files with 14 additions and 8 deletions
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12
src/iss/arch/riscv_hart_m_p.h
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@ -454,11 +454,13 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
//csr_wr_cb[addr] = &this_class::write_csr_reg; //csr_wr_cb[addr] = &this_class::write_csr_reg;
} }
// common regs // common regs
const std::array<unsigned, 8> addrs{{ const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
misa, mvendorid, marchid, mimpid, for(auto addr: roaddrs) {
mepc, mtvec, mscratch, mtval csr_rd_cb[addr] = &this_class::read_csr_reg;
}}; csr_wr_cb[addr] = &this_class::write_null;
for(auto addr: addrs) { }
const std::array<unsigned, 4> rwaddrs{{mepc, mtvec, mscratch, mtval}};
for(auto addr: rwaddrs) {
csr_rd_cb[addr] = &this_class::read_csr_reg; csr_rd_cb[addr] = &this_class::read_csr_reg;
csr_wr_cb[addr] = &this_class::write_csr_reg; csr_wr_cb[addr] = &this_class::write_csr_reg;
} }

10
src/iss/arch/riscv_hart_mu_p.h
View File

@ -398,12 +398,16 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
//csr_wr_cb[addr] = &this_class::write_csr_reg; //csr_wr_cb[addr] = &this_class::write_csr_reg;
} }
// common regs // common regs
const std::array<unsigned, 12> addrs{{ const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
misa, mvendorid, marchid, mimpid, for(auto addr: roaddrs) {
csr_rd_cb[addr] = &this_class::read_csr_reg;
csr_wr_cb[addr] = &this_class::write_null;
}
const std::array<unsigned, 8> rwaddrs{{
mepc, mtvec, mscratch, mtval, mepc, mtvec, mscratch, mtval,
uepc, utvec, uscratch, utval, uepc, utvec, uscratch, utval,
}}; }};
for(auto addr: addrs) { for(auto addr: rwaddrs) {
csr_rd_cb[addr] = &this_class::read_csr_reg; csr_rd_cb[addr] = &this_class::read_csr_reg;
csr_wr_cb[addr] = &this_class::write_csr_reg; csr_wr_cb[addr] = &this_class::write_csr_reg;
} }