DBT-RISE/DBT-RISE-TGC
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minor improvements to readability

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This commit is contained in:
Eyck-Alexander Jentzsch 2024-10-21 16:46:32 +02:00
parent 0e88664ff7
commit 978c3db06e
1 changed files with 2 additions and 2 deletions
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4
src/iss/arch/riscv_hart_m_p.h
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@ -720,7 +720,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
return iss::Err;
}
try {
if(length > 1 && (addr & (length - 1)) && (access & access_type::DEBUG) != access_type::DEBUG) {
if(length > 1 && (addr & (length - 1)) && !is_debug(access)) {
this->reg.trap_state = (1UL << 31) | 6 << 16;
fault_data = addr;
return iss::Err;
@ -740,7 +740,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
} else {
res = write_mem(phys_addr, length, data);
}
if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
if(unlikely(res != iss::Ok && !is_debug(access))) {
this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
fault_data = addr;
}