From 978c3db06ef5a4abd6b4ffca4df5cfe9ae911ad7 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Mon, 21 Oct 2024 16:46:32 +0200
Subject: [PATCH] minor improvements to readability

---
 src/iss/arch/riscv_hart_m_p.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index 9e8db83..e8f71f7 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -720,7 +720,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
                 return iss::Err;
             }
             try {
-                if(length > 1 && (addr & (length - 1)) && (access & access_type::DEBUG) != access_type::DEBUG) {
+                if(length > 1 && (addr & (length - 1)) && !is_debug(access)) {
                     this->reg.trap_state = (1UL << 31) | 6 << 16;
                     fault_data = addr;
                     return iss::Err;
@@ -740,7 +740,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
                 } else {
                     res = write_mem(phys_addr, length, data);
                 }
-                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
+                if(unlikely(res != iss::Ok && !is_debug(access))) {
                     this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data = addr;
                 }