DBT-RISE/DBT-RISE-TGC
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Fixed time csr handling

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This commit is contained in:
Eyck Jentzsch
2019-06-28 20:58:02 +02:00
parent d93c2feec4
commit 7f06bba239
6 changed files with 26 additions and 5 deletions
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2
src/iss/rv32gc.cpp
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@@ -66,7 +66,7 @@ void rv32gc::reset(uint64_t address) {
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x0;
reg.machine_state=0x3;
reg.icount=0;
}

2
src/iss/rv64gc.cpp
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@@ -67,7 +67,7 @@ void rv64gc::reset(uint64_t address) {
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x0;
reg.machine_state=0x3;
reg.icount=0;
}

2
src/iss/rv64i.cpp
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@@ -65,7 +65,7 @@ void rv64i::reset(uint64_t address) {
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x0;
reg.machine_state=0x3;
reg.icount=0;
}