adds a instr yaml for TGC
This commit is contained in:
parent
4dbc7433a5
commit
7e45a25218
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@ -0,0 +1,537 @@
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RV32I:
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mask: 0b00000000000000000111000001111111
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encoding: 0b00000000000000000010000000000011
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mask: 0b00000000000000000111000001111111
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- LBU:
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mask: 0b00000000000000000111000001111111
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encoding: 0b00000000000000000001000000100011
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mask: 0b00000000000000000111000001111111
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encoding: 0b00000000000000000010000000100011
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encoding: 0b00000000000000000010000000010011
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mask: 0b00000000000000000111000001111111
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- ORI:
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mask: 0b00000000000000000111000001111111
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- SLLI:
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encoding: 0b00000000000000000001000000010011
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mask: 0b11111110000000000111000001111111
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size: 32
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delay: 1
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- SRLI:
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encoding: 0b00000000000000000101000000010011
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mask: 0b11111110000000000111000001111111
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size: 32
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branch: false
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delay: 1
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- SRAI:
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encoding: 0b01000000000000000101000000010011
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mask: 0b11111110000000000111000001111111
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delay: 1
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- SLL:
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encoding: 0b00000000000000000001000000110011
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mask: 0b11111110000000000111000001111111
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size: 32
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branch: false
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delay: 1
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- SLT:
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encoding: 0b00000000000000000010000000110011
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mask: 0b11111110000000000111000001111111
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size: 32
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branch: false
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delay: 1
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- SLTU:
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encoding: 0b00000000000000000011000000110011
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mask: 0b11111110000000000111000001111111
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branch: false
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delay: 1
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- XOR:
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encoding: 0b00000000000000000100000000110011
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mask: 0b11111110000000000111000001111111
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branch: false
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delay: 1
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- SRL:
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encoding: 0b00000000000000000101000000110011
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mask: 0b11111110000000000111000001111111
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size: 32
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branch: false
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delay: 1
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- SRA:
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encoding: 0b01000000000000000101000000110011
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mask: 0b11111110000000000111000001111111
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size: 32
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delay: 1
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- OR:
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mask: 0b11111110000000000111000001111111
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branch: false
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delay: 1
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- AND:
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encoding: 0b00000000000000000111000000110011
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mask: 0b11111110000000000111000001111111
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size: 32
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branch: false
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delay: 1
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- FENCE:
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encoding: 0b00000000000000000000000000001111
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mask: 0b00000000000000000111000001111111
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size: 32
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branch: false
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delay: 1
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- ECALL:
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encoding: 0b00000000000000000000000001110011
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mask: 0b11111111111111111111111111111111
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size: 32
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branch: false
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- EBREAK:
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mask: 0b11111111111111111111111111111111
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attributes: [[name:no_cont]]
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size: 32
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branch: false
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delay: 1
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- MRET:
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encoding: 0b00110000001000000000000001110011
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mask: 0b11111111111111111111111111111111
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attributes: [[name:no_cont]]
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mask: 0b11111111111111111111111111111111
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size: 32
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branch: false
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delay: 1
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Zicsr:
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- CSRRW:
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encoding: 0b00000000000000000001000001110011
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mask: 0b00000000000000000111000001111111
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size: 32
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branch: false
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delay: 1
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- CSRRS:
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encoding: 0b00000000000000000010000001110011
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mask: 0b00000000000000000111000001111111
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size: 32
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branch: false
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delay: 1
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- CSRRC:
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encoding: 0b00000000000000000011000001110011
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mask: 0b00000000000000000111000001111111
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size: 32
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branch: false
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delay: 1
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- CSRRWI:
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encoding: 0b00000000000000000101000001110011
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mask: 0b00000000000000000111000001111111
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size: 32
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delay: 1
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- CSRRSI:
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Zifencei:
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RV32M:
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- DIVU:
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- REM:
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encoding: 0b00000010000000000110000000110011
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mask: 0b11111110000000000111000001111111
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size: 32
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- REMU:
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mask: 0b11111110000000000111000001111111
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size: 32
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delay: 1
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RV32IC:
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||||
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- CLW:
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||||
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attributes: [[name:no_cont]]
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size: 16
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- CLI:
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mask: 0b1110000000000011
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delay: 1
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- CLUI:
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||||
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||||
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- CJ:
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||||
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||||
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||||
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||||
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- CBEQZ:
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||||
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branch: true
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- CBNEZ:
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||||
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- CSLLI:
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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- CJR:
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||||
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- CADD:
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||||
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mask: 0b1111000000000011
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size: 16
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branch: false
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- CJALR:
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encoding: 0b1001000000000010
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mask: 0b1111000001111111
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attributes: [[name:no_cont]]
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size: 16
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branch: true
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delay: 1
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- CEBREAK:
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encoding: 0b1001000000000010
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mask: 0b1111111111111111
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attributes: [[name:no_cont]]
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size: 16
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branch: false
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delay: 1
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- CSWSP:
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encoding: 0b1100000000000010
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mask: 0b1110000000000011
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size: 16
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branch: false
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delay: 1
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- DII:
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encoding: 0b0000000000000000
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mask: 0b1111111111111111
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attributes: [[name:no_cont]]
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size: 16
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||||
branch: false
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delay: 1
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