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DBT-RISE-TGC
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Asmjit and interp working

This commit is contained in:
Eyck-Alexander Jentzsch 2024-07-10 12:51:31 +02:00
parent 63da7f8d57
commit 4cfb15c7cd
4 changed files with 177 additions and 178 deletions
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2
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 20217-2024 MINRES Technologies GmbH
* Copyright (C) 2017-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
src/iss/arch/tgc5c.h
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File diff suppressed because one or more lines are too long

15
src/vm/asmjit/vm_tgc5c.cpp
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@ -2825,7 +2825,7 @@ private:
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto res = gen_operation(jh, imul, gen_ext(jh,
auto res = gen_operation(jh, smul, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true))
;
@ -2877,7 +2877,7 @@ private:
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto res = gen_operation(jh, imul, gen_ext(jh,
auto res = gen_operation(jh, smul, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true))
;
@ -2930,7 +2930,7 @@ private:
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto res = gen_operation(jh, imul, gen_ext(jh,
auto res = gen_operation(jh, sumul, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), load_reg_from_mem(jh, traits::X0 + rs2))
;
if(rd!=0){
@ -2982,9 +2982,8 @@ private:
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto res = gen_operation(jh, mul,
load_reg_from_mem(jh, traits::X0 + rs1),
load_reg_from_mem(jh, traits::X0 + rs2));
auto res = gen_operation(jh, umul, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
;
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_ext(jh,
@ -3062,7 +3061,7 @@ private:
{
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_ext(jh,
(gen_operation(jh, idiv, dividend, divisor)
(gen_operation(jh, sdiv, dividend, divisor)
), 32, true));
}
cc.bind(label_merge);
@ -3126,7 +3125,7 @@ private:
{
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_operation(jh, div, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
gen_operation(jh, udiv, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
);
}
}

52
src/vm/interp/vm_tgc5c.cpp
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@ -732,9 +732,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
int8_t res_27 = super::template read_mem<int8_t>(traits::MEM, load_address);
int8_t res_40 = super::template read_mem<int8_t>(traits::MEM, load_address);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
int8_t res = (int8_t)res_27;
int8_t res = (int8_t)res_40;
if(rd != 0) {
*(X+rd) = (uint32_t)res;
}
@ -763,9 +763,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
int16_t res_28 = super::template read_mem<int16_t>(traits::MEM, load_address);
int16_t res_41 = super::template read_mem<int16_t>(traits::MEM, load_address);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
int16_t res = (int16_t)res_28;
int16_t res = (int16_t)res_41;
if(rd != 0) {
*(X+rd) = (uint32_t)res;
}
@ -794,9 +794,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
int32_t res_29 = super::template read_mem<int32_t>(traits::MEM, load_address);
int32_t res_42 = super::template read_mem<int32_t>(traits::MEM, load_address);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
int32_t res = (int32_t)res_29;
int32_t res = (int32_t)res_42;
if(rd != 0) {
*(X+rd) = (uint32_t)res;
}
@ -825,9 +825,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
uint8_t res_30 = super::template read_mem<uint8_t>(traits::MEM, load_address);
uint8_t res_43 = super::template read_mem<uint8_t>(traits::MEM, load_address);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
uint8_t res = res_30;
uint8_t res = res_43;
if(rd != 0) {
*(X+rd) = (uint32_t)res;
}
@ -856,9 +856,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
uint16_t res_31 = super::template read_mem<uint16_t>(traits::MEM, load_address);
uint16_t res_44 = super::template read_mem<uint16_t>(traits::MEM, load_address);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
uint16_t res = res_31;
uint16_t res = res_44;
if(rd != 0) {
*(X+rd) = (uint32_t)res;
}
@ -1556,9 +1556,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
else {
uint32_t xrs1 = *(X+rs1);
if(rd != 0) {
uint32_t res_32 = super::template read_mem<uint32_t>(traits::CSR, csr);
uint32_t res_45 = super::template read_mem<uint32_t>(traits::CSR, csr);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
uint32_t xrd = res_32;
uint32_t xrd = res_45;
super::template write_mem<uint32_t>(traits::CSR, csr, xrs1);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
*(X+rd) = xrd;
@ -1591,9 +1591,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_33 = super::template read_mem<uint32_t>(traits::CSR, csr);
uint32_t res_46 = super::template read_mem<uint32_t>(traits::CSR, csr);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
uint32_t xrd = res_33;
uint32_t xrd = res_46;
uint32_t xrs1 = *(X+rs1);
if(rs1 != 0) {
super::template write_mem<uint32_t>(traits::CSR, csr, xrd | xrs1);
@ -1626,9 +1626,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_34 = super::template read_mem<uint32_t>(traits::CSR, csr);
uint32_t res_47 = super::template read_mem<uint32_t>(traits::CSR, csr);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
uint32_t xrd = res_34;
uint32_t xrd = res_47;
uint32_t xrs1 = *(X+rs1);
if(rs1 != 0) {
super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ xrs1);
@ -1661,9 +1661,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_35 = super::template read_mem<uint32_t>(traits::CSR, csr);
uint32_t res_48 = super::template read_mem<uint32_t>(traits::CSR, csr);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
uint32_t xrd = res_35;
uint32_t xrd = res_48;
super::template write_mem<uint32_t>(traits::CSR, csr, (uint32_t)zimm);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
if(rd != 0) {
@ -1693,9 +1693,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_36 = super::template read_mem<uint32_t>(traits::CSR, csr);
uint32_t res_49 = super::template read_mem<uint32_t>(traits::CSR, csr);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
uint32_t xrd = res_36;
uint32_t xrd = res_49;
if(zimm != 0) {
super::template write_mem<uint32_t>(traits::CSR, csr, xrd | (uint32_t)zimm);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
@ -1727,9 +1727,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_37 = super::template read_mem<uint32_t>(traits::CSR, csr);
uint32_t res_50 = super::template read_mem<uint32_t>(traits::CSR, csr);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
uint32_t xrd = res_37;
uint32_t xrd = res_50;
if(zimm != 0) {
super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ ((uint32_t)zimm));
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
@ -2064,9 +2064,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm ));
int32_t res_38 = super::template read_mem<int32_t>(traits::MEM, offs);
int32_t res_51 = super::template read_mem<int32_t>(traits::MEM, offs);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
*(X+rd + 8) = (uint32_t)(int32_t)res_38;
*(X+rd + 8) = (uint32_t)(int32_t)res_51;
}
break;
}// @suppress("No break at end of case")
@ -2486,9 +2486,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm ));
int32_t res_39 = super::template read_mem<int32_t>(traits::MEM, offs);
int32_t res_52 = super::template read_mem<int32_t>(traits::MEM, offs);
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
*(X+rd) = (uint32_t)(int32_t)res_39;
*(X+rd) = (uint32_t)(int32_t)res_52;
}
}
break;