From 4cfb15c7cd288a138c8c8dd409b15c9326c8c8b7 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Wed, 10 Jul 2024 12:51:31 +0200 Subject: [PATCH] Asmjit and interp working --- gen_input/templates/interp/CORENAME.cpp.gtl | 2 +- src/iss/arch/tgc5c.h | 2 +- src/vm/asmjit/vm_tgc5c.cpp | 299 ++++++++++---------- src/vm/interp/vm_tgc5c.cpp | 52 ++-- 4 files changed, 177 insertions(+), 178 deletions(-) diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index 99e60ac..567737d 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) 20217-2024 MINRES Technologies GmbH + * Copyright (C) 2017-2024 MINRES Technologies GmbH * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h index 7d51456..606256a 100644 --- a/src/iss/arch/tgc5c.h +++ b/src/iss/arch/tgc5c.h @@ -53,7 +53,7 @@ template <> struct traits { static constexpr std::array reg_aliases{ {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}}; - enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, RV_CSR_FFLAGS=1ULL, RV_CSR_FRM=2ULL, RV_CSR_FCSR=3ULL, RV_CSR_UTVT=7ULL, RV_CSR_VSTART=8ULL, RV_CSR_VXSAT=9ULL, RV_CSR_VXRM=10ULL, RV_CSR_VCSR=15ULL, RV_CSR_SEED=21ULL, RV_CSR_UNXTI=69ULL, RV_CSR_UINTSTATUS=70ULL, RV_CSR_USCRATCHCSW=72ULL, RV_CSR_USCRATCHCSWL=73ULL, RV_CSR_SSTATUS=256ULL, RV_CSR_SEDELEG=258ULL, RV_CSR_SIDELEG=259ULL, RV_CSR_SIE=260ULL, RV_CSR_STVEC=261ULL, RV_CSR_SCOUNTEREN=262ULL, RV_CSR_STVT=263ULL, RV_CSR_SENVCFG=266ULL, RV_CSR_SSTATEEN0=268ULL, RV_CSR_SSTATEEN1=269ULL, RV_CSR_SSTATEEN2=270ULL, RV_CSR_SSTATEEN3=271ULL, RV_CSR_SSCRATCH=320ULL, RV_CSR_SEPC=321ULL, RV_CSR_SCAUSE=322ULL, RV_CSR_STVAL=323ULL, RV_CSR_SIP=324ULL, RV_CSR_SNXTI=325ULL, RV_CSR_SINTSTATUS=326ULL, RV_CSR_SSCRATCHCSW=328ULL, RV_CSR_SSCRATCHCSWL=329ULL, RV_CSR_STIMECMP=333ULL, RV_CSR_STIMECMPH=349ULL, RV_CSR_SATP=384ULL, RV_CSR_VSSTATUS=512ULL, RV_CSR_VSIE=516ULL, RV_CSR_VSTVEC=517ULL, RV_CSR_VSSCRATCH=576ULL, RV_CSR_VSEPC=577ULL, RV_CSR_VSCAUSE=578ULL, RV_CSR_VSTVAL=579ULL, RV_CSR_VSIP=580ULL, RV_CSR_VSTIMECMP=589ULL, RV_CSR_VSTIMECMPH=605ULL, RV_CSR_VSATP=640ULL, RV_CSR_MSTATUS=768ULL, RV_CSR_MISA=769ULL, RV_CSR_MEDELEG=770ULL, RV_CSR_MIDELEG=771ULL, RV_CSR_MIE=772ULL, RV_CSR_MTVEC=773ULL, RV_CSR_MCOUNTEREN=774ULL, RV_CSR_MTVT=775ULL, RV_CSR_MENVCFG=778ULL, RV_CSR_MSTATEEN0=780ULL, RV_CSR_MSTATEEN1=781ULL, RV_CSR_MSTATEEN2=782ULL, RV_CSR_MSTATEEN3=783ULL, RV_CSR_MSTATUSH=784ULL, RV_CSR_MENVCFGH=794ULL, RV_CSR_MSTATEEN0H=796ULL, RV_CSR_MSTATEEN1H=797ULL, RV_CSR_MSTATEEN2H=798ULL, RV_CSR_MSTATEEN3H=799ULL, RV_CSR_MCOUNTINHIBIT=800ULL, RV_CSR_MHPMEVENT3=803ULL, RV_CSR_MHPMEVENT4=804ULL, RV_CSR_MHPMEVENT5=805ULL, RV_CSR_MHPMEVENT6=806ULL, RV_CSR_MHPMEVENT7=807ULL, RV_CSR_MHPMEVENT8=808ULL, RV_CSR_MHPMEVENT9=809ULL, RV_CSR_MHPMEVENT10=810ULL, RV_CSR_MHPMEVENT11=811ULL, RV_CSR_MHPMEVENT12=812ULL, RV_CSR_MHPMEVENT13=813ULL, RV_CSR_MHPMEVENT14=814ULL, RV_CSR_MHPMEVENT15=815ULL, RV_CSR_MHPMEVENT16=816ULL, RV_CSR_MHPMEVENT17=817ULL, RV_CSR_MHPMEVENT18=818ULL, RV_CSR_MHPMEVENT19=819ULL, RV_CSR_MHPMEVENT20=820ULL, RV_CSR_MHPMEVENT21=821ULL, RV_CSR_MHPMEVENT22=822ULL, RV_CSR_MHPMEVENT23=823ULL, RV_CSR_MHPMEVENT24=824ULL, RV_CSR_MHPMEVENT25=825ULL, RV_CSR_MHPMEVENT26=826ULL, RV_CSR_MHPMEVENT27=827ULL, RV_CSR_MHPMEVENT28=828ULL, RV_CSR_MHPMEVENT29=829ULL, RV_CSR_MHPMEVENT30=830ULL, RV_CSR_MHPMEVENT31=831ULL, RV_CSR_MSCRATCH=832ULL, RV_CSR_MEPC=833ULL, RV_CSR_MCAUSE=834ULL, RV_CSR_MTVAL=835ULL, RV_CSR_MIP=836ULL, RV_CSR_MNXTI=837ULL, RV_CSR_MINTSTATUS=838ULL, RV_CSR_MSCRATCHCSW=840ULL, RV_CSR_MSCRATCHCSWL=841ULL, RV_CSR_MTINST=842ULL, RV_CSR_MTVAL2=843ULL, RV_CSR_PMPCFG0=928ULL, RV_CSR_PMPCFG1=929ULL, RV_CSR_PMPCFG2=930ULL, RV_CSR_PMPCFG3=931ULL, RV_CSR_PMPCFG4=932ULL, RV_CSR_PMPCFG5=933ULL, RV_CSR_PMPCFG6=934ULL, RV_CSR_PMPCFG7=935ULL, RV_CSR_PMPCFG8=936ULL, RV_CSR_PMPCFG9=937ULL, RV_CSR_PMPCFG10=938ULL, RV_CSR_PMPCFG11=939ULL, RV_CSR_PMPCFG12=940ULL, RV_CSR_PMPCFG13=941ULL, RV_CSR_PMPCFG14=942ULL, RV_CSR_PMPCFG15=943ULL, RV_CSR_PMPADDR0=944ULL, RV_CSR_PMPADDR1=945ULL, RV_CSR_PMPADDR2=946ULL, RV_CSR_PMPADDR3=947ULL, RV_CSR_PMPADDR4=948ULL, RV_CSR_PMPADDR5=949ULL, RV_CSR_PMPADDR6=950ULL, RV_CSR_PMPADDR7=951ULL, RV_CSR_PMPADDR8=952ULL, RV_CSR_PMPADDR9=953ULL, RV_CSR_PMPADDR10=954ULL, RV_CSR_PMPADDR11=955ULL, RV_CSR_PMPADDR12=956ULL, RV_CSR_PMPADDR13=957ULL, RV_CSR_PMPADDR14=958ULL, RV_CSR_PMPADDR15=959ULL, RV_CSR_PMPADDR16=960ULL, RV_CSR_PMPADDR17=961ULL, RV_CSR_PMPADDR18=962ULL, RV_CSR_PMPADDR19=963ULL, RV_CSR_PMPADDR20=964ULL, RV_CSR_PMPADDR21=965ULL, RV_CSR_PMPADDR22=966ULL, RV_CSR_PMPADDR23=967ULL, RV_CSR_PMPADDR24=968ULL, RV_CSR_PMPADDR25=969ULL, RV_CSR_PMPADDR26=970ULL, RV_CSR_PMPADDR27=971ULL, RV_CSR_PMPADDR28=972ULL, RV_CSR_PMPADDR29=973ULL, RV_CSR_PMPADDR30=974ULL, RV_CSR_PMPADDR31=975ULL, RV_CSR_PMPADDR32=976ULL, RV_CSR_PMPADDR33=977ULL, RV_CSR_PMPADDR34=978ULL, RV_CSR_PMPADDR35=979ULL, RV_CSR_PMPADDR36=980ULL, RV_CSR_PMPADDR37=981ULL, RV_CSR_PMPADDR38=982ULL, RV_CSR_PMPADDR39=983ULL, RV_CSR_PMPADDR40=984ULL, RV_CSR_PMPADDR41=985ULL, RV_CSR_PMPADDR42=986ULL, RV_CSR_PMPADDR43=987ULL, RV_CSR_PMPADDR44=988ULL, RV_CSR_PMPADDR45=989ULL, RV_CSR_PMPADDR46=990ULL, RV_CSR_PMPADDR47=991ULL, RV_CSR_PMPADDR48=992ULL, RV_CSR_PMPADDR49=993ULL, RV_CSR_PMPADDR50=994ULL, RV_CSR_PMPADDR51=995ULL, RV_CSR_PMPADDR52=996ULL, RV_CSR_PMPADDR53=997ULL, RV_CSR_PMPADDR54=998ULL, RV_CSR_PMPADDR55=999ULL, RV_CSR_PMPADDR56=1000ULL, RV_CSR_PMPADDR57=1001ULL, RV_CSR_PMPADDR58=1002ULL, RV_CSR_PMPADDR59=1003ULL, RV_CSR_PMPADDR60=1004ULL, RV_CSR_PMPADDR61=1005ULL, RV_CSR_PMPADDR62=1006ULL, RV_CSR_PMPADDR63=1007ULL, RV_CSR_SCONTEXT=1448ULL, RV_CSR_HSTATUS=1536ULL, RV_CSR_HEDELEG=1538ULL, RV_CSR_HIDELEG=1539ULL, RV_CSR_HIE=1540ULL, RV_CSR_HTIMEDELTA=1541ULL, RV_CSR_HCOUNTEREN=1542ULL, RV_CSR_HGEIE=1543ULL, RV_CSR_HENVCFG=1546ULL, RV_CSR_HSTATEEN0=1548ULL, RV_CSR_HSTATEEN1=1549ULL, RV_CSR_HSTATEEN2=1550ULL, RV_CSR_HSTATEEN3=1551ULL, RV_CSR_HTIMEDELTAH=1557ULL, RV_CSR_HENVCFGH=1562ULL, RV_CSR_HSTATEEN0H=1564ULL, RV_CSR_HSTATEEN1H=1565ULL, RV_CSR_HSTATEEN2H=1566ULL, RV_CSR_HSTATEEN3H=1567ULL, RV_CSR_HTVAL=1603ULL, RV_CSR_HIP=1604ULL, RV_CSR_HVIP=1605ULL, RV_CSR_HTINST=1610ULL, RV_CSR_HGATP=1664ULL, RV_CSR_HCONTEXT=1704ULL, RV_CSR_MHPMEVENT3H=1827ULL, RV_CSR_MHPMEVENT4H=1828ULL, RV_CSR_MHPMEVENT5H=1829ULL, RV_CSR_MHPMEVENT6H=1830ULL, RV_CSR_MHPMEVENT7H=1831ULL, RV_CSR_MHPMEVENT8H=1832ULL, RV_CSR_MHPMEVENT9H=1833ULL, RV_CSR_MHPMEVENT10H=1834ULL, RV_CSR_MHPMEVENT11H=1835ULL, RV_CSR_MHPMEVENT12H=1836ULL, RV_CSR_MHPMEVENT13H=1837ULL, RV_CSR_MHPMEVENT14H=1838ULL, RV_CSR_MHPMEVENT15H=1839ULL, RV_CSR_MHPMEVENT16H=1840ULL, RV_CSR_MHPMEVENT17H=1841ULL, RV_CSR_MHPMEVENT18H=1842ULL, RV_CSR_MHPMEVENT19H=1843ULL, RV_CSR_MHPMEVENT20H=1844ULL, RV_CSR_MHPMEVENT21H=1845ULL, RV_CSR_MHPMEVENT22H=1846ULL, RV_CSR_MHPMEVENT23H=1847ULL, RV_CSR_MHPMEVENT24H=1848ULL, RV_CSR_MHPMEVENT25H=1849ULL, RV_CSR_MHPMEVENT26H=1850ULL, RV_CSR_MHPMEVENT27H=1851ULL, RV_CSR_MHPMEVENT28H=1852ULL, RV_CSR_MHPMEVENT29H=1853ULL, RV_CSR_MHPMEVENT30H=1854ULL, RV_CSR_MHPMEVENT31H=1855ULL, RV_CSR_MSECCFG=1863ULL, RV_CSR_MSECCFGH=1879ULL, RV_CSR_TSELECT=1952ULL, RV_CSR_TDATA1=1953ULL, RV_CSR_TDATA2=1954ULL, RV_CSR_TDATA3=1955ULL, RV_CSR_TINFO=1956ULL, RV_CSR_TCONTROL=1957ULL, RV_CSR_MCONTEXT=1960ULL, RV_CSR_MSCONTEXT=1962ULL, RV_CSR_DCSR=1968ULL, RV_CSR_DPC=1969ULL, RV_CSR_DSCRATCH0=1970ULL, RV_CSR_DSCRATCH1=1971ULL, RV_CSR_MCYCLE=2816ULL, RV_CSR_MINSTRET=2818ULL, RV_CSR_MHPMCOUNTER3=2819ULL, RV_CSR_MHPMCOUNTER4=2820ULL, RV_CSR_MHPMCOUNTER5=2821ULL, RV_CSR_MHPMCOUNTER6=2822ULL, RV_CSR_MHPMCOUNTER7=2823ULL, RV_CSR_MHPMCOUNTER8=2824ULL, RV_CSR_MHPMCOUNTER9=2825ULL, RV_CSR_MHPMCOUNTER10=2826ULL, RV_CSR_MHPMCOUNTER11=2827ULL, RV_CSR_MHPMCOUNTER12=2828ULL, RV_CSR_MHPMCOUNTER13=2829ULL, RV_CSR_MHPMCOUNTER14=2830ULL, RV_CSR_MHPMCOUNTER15=2831ULL, RV_CSR_MHPMCOUNTER16=2832ULL, RV_CSR_MHPMCOUNTER17=2833ULL, RV_CSR_MHPMCOUNTER18=2834ULL, RV_CSR_MHPMCOUNTER19=2835ULL, RV_CSR_MHPMCOUNTER20=2836ULL, RV_CSR_MHPMCOUNTER21=2837ULL, RV_CSR_MHPMCOUNTER22=2838ULL, RV_CSR_MHPMCOUNTER23=2839ULL, RV_CSR_MHPMCOUNTER24=2840ULL, RV_CSR_MHPMCOUNTER25=2841ULL, RV_CSR_MHPMCOUNTER26=2842ULL, RV_CSR_MHPMCOUNTER27=2843ULL, RV_CSR_MHPMCOUNTER28=2844ULL, RV_CSR_MHPMCOUNTER29=2845ULL, RV_CSR_MHPMCOUNTER30=2846ULL, RV_CSR_MHPMCOUNTER31=2847ULL, RV_CSR_MCYCLEH=2944ULL, RV_CSR_MINSTRETH=2946ULL, RV_CSR_MHPMCOUNTER3H=2947ULL, RV_CSR_MHPMCOUNTER4H=2948ULL, RV_CSR_MHPMCOUNTER5H=2949ULL, RV_CSR_MHPMCOUNTER6H=2950ULL, RV_CSR_MHPMCOUNTER7H=2951ULL, RV_CSR_MHPMCOUNTER8H=2952ULL, RV_CSR_MHPMCOUNTER9H=2953ULL, RV_CSR_MHPMCOUNTER10H=2954ULL, RV_CSR_MHPMCOUNTER11H=2955ULL, RV_CSR_MHPMCOUNTER12H=2956ULL, RV_CSR_MHPMCOUNTER13H=2957ULL, RV_CSR_MHPMCOUNTER14H=2958ULL, RV_CSR_MHPMCOUNTER15H=2959ULL, RV_CSR_MHPMCOUNTER16H=2960ULL, RV_CSR_MHPMCOUNTER17H=2961ULL, RV_CSR_MHPMCOUNTER18H=2962ULL, RV_CSR_MHPMCOUNTER19H=2963ULL, RV_CSR_MHPMCOUNTER20H=2964ULL, RV_CSR_MHPMCOUNTER21H=2965ULL, RV_CSR_MHPMCOUNTER22H=2966ULL, RV_CSR_MHPMCOUNTER23H=2967ULL, RV_CSR_MHPMCOUNTER24H=2968ULL, RV_CSR_MHPMCOUNTER25H=2969ULL, RV_CSR_MHPMCOUNTER26H=2970ULL, RV_CSR_MHPMCOUNTER27H=2971ULL, RV_CSR_MHPMCOUNTER28H=2972ULL, RV_CSR_MHPMCOUNTER29H=2973ULL, RV_CSR_MHPMCOUNTER30H=2974ULL, RV_CSR_MHPMCOUNTER31H=2975ULL, RV_CSR_CYCLE=3072ULL, RV_CSR_TIME=3073ULL, RV_CSR_INSTRET=3074ULL, RV_CSR_HPMCOUNTER3=3075ULL, RV_CSR_HPMCOUNTER4=3076ULL, RV_CSR_HPMCOUNTER5=3077ULL, RV_CSR_HPMCOUNTER6=3078ULL, RV_CSR_HPMCOUNTER7=3079ULL, RV_CSR_HPMCOUNTER8=3080ULL, RV_CSR_HPMCOUNTER9=3081ULL, RV_CSR_HPMCOUNTER10=3082ULL, RV_CSR_HPMCOUNTER11=3083ULL, RV_CSR_HPMCOUNTER12=3084ULL, RV_CSR_HPMCOUNTER13=3085ULL, RV_CSR_HPMCOUNTER14=3086ULL, RV_CSR_HPMCOUNTER15=3087ULL, RV_CSR_HPMCOUNTER16=3088ULL, RV_CSR_HPMCOUNTER17=3089ULL, RV_CSR_HPMCOUNTER18=3090ULL, RV_CSR_HPMCOUNTER19=3091ULL, RV_CSR_HPMCOUNTER20=3092ULL, RV_CSR_HPMCOUNTER21=3093ULL, RV_CSR_HPMCOUNTER22=3094ULL, RV_CSR_HPMCOUNTER23=3095ULL, RV_CSR_HPMCOUNTER24=3096ULL, RV_CSR_HPMCOUNTER25=3097ULL, RV_CSR_HPMCOUNTER26=3098ULL, RV_CSR_HPMCOUNTER27=3099ULL, RV_CSR_HPMCOUNTER28=3100ULL, RV_CSR_HPMCOUNTER29=3101ULL, RV_CSR_HPMCOUNTER30=3102ULL, RV_CSR_HPMCOUNTER31=3103ULL, RV_CSR_VL=3104ULL, RV_CSR_VTYPE=3105ULL, RV_CSR_VLENB=3106ULL, RV_CSR_CYCLEH=3200ULL, RV_CSR_TIMEH=3201ULL, RV_CSR_INSTRETH=3202ULL, RV_CSR_HPMCOUNTER3H=3203ULL, RV_CSR_HPMCOUNTER4H=3204ULL, RV_CSR_HPMCOUNTER5H=3205ULL, RV_CSR_HPMCOUNTER6H=3206ULL, RV_CSR_HPMCOUNTER7H=3207ULL, RV_CSR_HPMCOUNTER8H=3208ULL, RV_CSR_HPMCOUNTER9H=3209ULL, RV_CSR_HPMCOUNTER10H=3210ULL, RV_CSR_HPMCOUNTER11H=3211ULL, RV_CSR_HPMCOUNTER12H=3212ULL, RV_CSR_HPMCOUNTER13H=3213ULL, RV_CSR_HPMCOUNTER14H=3214ULL, RV_CSR_HPMCOUNTER15H=3215ULL, RV_CSR_HPMCOUNTER16H=3216ULL, RV_CSR_HPMCOUNTER17H=3217ULL, RV_CSR_HPMCOUNTER18H=3218ULL, RV_CSR_HPMCOUNTER19H=3219ULL, RV_CSR_HPMCOUNTER20H=3220ULL, RV_CSR_HPMCOUNTER21H=3221ULL, RV_CSR_HPMCOUNTER22H=3222ULL, RV_CSR_HPMCOUNTER23H=3223ULL, RV_CSR_HPMCOUNTER24H=3224ULL, RV_CSR_HPMCOUNTER25H=3225ULL, RV_CSR_HPMCOUNTER26H=3226ULL, RV_CSR_HPMCOUNTER27H=3227ULL, RV_CSR_HPMCOUNTER28H=3228ULL, RV_CSR_HPMCOUNTER29H=3229ULL, RV_CSR_HPMCOUNTER30H=3230ULL, RV_CSR_HPMCOUNTER31H=3231ULL, RV_CSR_SCOUNTOVF=3488ULL, RV_CSR_HGEIP=3602ULL, RV_CSR_MVENDORID=3857ULL, RV_CSR_MARCHID=3858ULL, RV_CSR_MIMPID=3859ULL, RV_CSR_MHARTID=3860ULL, RV_CSR_MCONFIGPTR=3861ULL, RV_CAUSE_MISALIGNED_FETCH=0ULL, RV_CAUSE_FETCH_ACCESS=1ULL, RV_CAUSE_ILLEGAL_INSTRUCTION=2ULL, RV_CAUSE_BREAKPOINT=3ULL, RV_CAUSE_MISALIGNED_LOAD=4ULL, RV_CAUSE_LOAD_ACCESS=5ULL, RV_CAUSE_MISALIGNED_STORE=6ULL, RV_CAUSE_STORE_ACCESS=7ULL, RV_CAUSE_USER_ECALL=8ULL, RV_CAUSE_SUPERVISOR_ECALL=9ULL, RV_CAUSE_VIRTUAL_SUPERVISOR_ECALL=10ULL, RV_CAUSE_MACHINE_ECALL=11ULL, RV_CAUSE_FETCH_PAGE_FAULT=12ULL, RV_CAUSE_LOAD_PAGE_FAULT=13ULL, RV_CAUSE_STORE_PAGE_FAULT=15ULL, RV_CAUSE_FETCH_GUEST_PAGE_FAULT=20ULL, RV_CAUSE_LOAD_GUEST_PAGE_FAULT=21ULL, RV_CAUSE_VIRTUAL_INSTRUCTION=22ULL, RV_CAUSE_STORE_GUEST_PAGE_FAULT=23ULL, RV_MSTATUS_UIE=1ULL, RV_MSTATUS_SIE=2ULL, RV_MSTATUS_HIE=4ULL, RV_MSTATUS_MIE=8ULL, RV_MSTATUS_UPIE=16ULL, RV_MSTATUS_SPIE=32ULL, RV_MSTATUS_UBE=64ULL, RV_MSTATUS_MPIE=128ULL, RV_MSTATUS_SPP=256ULL, RV_MSTATUS_VS=1536ULL, RV_MSTATUS_MPP=6144ULL, RV_MSTATUS_FS=24576ULL, RV_MSTATUS_XS=98304ULL, RV_MSTATUS_MPRV=131072ULL, RV_MSTATUS_SUM=262144ULL, RV_MSTATUS_MXR=524288ULL, RV_MSTATUS_TVM=1048576ULL, RV_MSTATUS_TW=2097152ULL, RV_MSTATUS_TSR=4194304ULL, RV_MSTATUS32_SD=1ULL, RV_PRV_U=0ULL, RV_PRV_S=1ULL, RV_PRV_H=2ULL, RV_PRV_M=3ULL, RV_IRQ_U_SOFT=0ULL, RV_IRQ_S_SOFT=1ULL, RV_IRQ_VS_SOFT=2ULL, RV_IRQ_M_SOFT=3ULL, RV_IRQ_U_TIMER=4ULL, RV_IRQ_S_TIMER=5ULL, RV_IRQ_VS_TIMER=6ULL, RV_IRQ_M_TIMER=7ULL, RV_IRQ_U_EXT=8ULL, RV_IRQ_S_EXT=9ULL, RV_IRQ_VS_EXT=10ULL, RV_IRQ_M_EXT=11ULL, RV_IRQ_S_GEXT=12ULL, RV_IRQ_COP=12ULL, RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=1ULL, RV_MIP_VSSIP=1ULL, RV_MIP_MSIP=1ULL, RV_MIP_UTIP=1ULL, RV_MIP_STIP=1ULL, RV_MIP_VSTIP=1ULL, RV_MIP_MTIP=1ULL, RV_MIP_UEIP=1ULL, RV_MIP_SEIP=1ULL, RV_MIP_VSEIP=1ULL, RV_MIP_MEIP=1ULL, RV_MIP_SGEIP=1ULL, RV_MIP_LCOFIP=1ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL}; + enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, FLEN=0ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, RV_CSR_FFLAGS=1ULL, RV_CSR_FRM=2ULL, RV_CSR_FCSR=3ULL, RV_CSR_UTVT=7ULL, RV_CSR_VSTART=8ULL, RV_CSR_VXSAT=9ULL, RV_CSR_VXRM=10ULL, RV_CSR_VCSR=15ULL, RV_CSR_SEED=21ULL, RV_CSR_UNXTI=69ULL, RV_CSR_UINTSTATUS=70ULL, RV_CSR_USCRATCHCSW=72ULL, RV_CSR_USCRATCHCSWL=73ULL, RV_CSR_SSTATUS=256ULL, RV_CSR_SEDELEG=258ULL, RV_CSR_SIDELEG=259ULL, RV_CSR_SIE=260ULL, RV_CSR_STVEC=261ULL, RV_CSR_SCOUNTEREN=262ULL, RV_CSR_STVT=263ULL, RV_CSR_SENVCFG=266ULL, RV_CSR_SSTATEEN0=268ULL, RV_CSR_SSTATEEN1=269ULL, RV_CSR_SSTATEEN2=270ULL, RV_CSR_SSTATEEN3=271ULL, RV_CSR_SSCRATCH=320ULL, RV_CSR_SEPC=321ULL, RV_CSR_SCAUSE=322ULL, RV_CSR_STVAL=323ULL, RV_CSR_SIP=324ULL, RV_CSR_SNXTI=325ULL, RV_CSR_SINTSTATUS=326ULL, RV_CSR_SSCRATCHCSW=328ULL, RV_CSR_SSCRATCHCSWL=329ULL, RV_CSR_STIMECMP=333ULL, RV_CSR_STIMECMPH=349ULL, RV_CSR_SATP=384ULL, RV_CSR_VSSTATUS=512ULL, RV_CSR_VSIE=516ULL, RV_CSR_VSTVEC=517ULL, RV_CSR_VSSCRATCH=576ULL, RV_CSR_VSEPC=577ULL, RV_CSR_VSCAUSE=578ULL, RV_CSR_VSTVAL=579ULL, RV_CSR_VSIP=580ULL, RV_CSR_VSTIMECMP=589ULL, RV_CSR_VSTIMECMPH=605ULL, RV_CSR_VSATP=640ULL, RV_CSR_MSTATUS=768ULL, RV_CSR_MISA=769ULL, RV_CSR_MEDELEG=770ULL, RV_CSR_MIDELEG=771ULL, RV_CSR_MIE=772ULL, RV_CSR_MTVEC=773ULL, RV_CSR_MCOUNTEREN=774ULL, RV_CSR_MTVT=775ULL, RV_CSR_MENVCFG=778ULL, RV_CSR_MSTATEEN0=780ULL, RV_CSR_MSTATEEN1=781ULL, RV_CSR_MSTATEEN2=782ULL, RV_CSR_MSTATEEN3=783ULL, RV_CSR_MSTATUSH=784ULL, RV_CSR_MENVCFGH=794ULL, RV_CSR_MSTATEEN0H=796ULL, RV_CSR_MSTATEEN1H=797ULL, RV_CSR_MSTATEEN2H=798ULL, RV_CSR_MSTATEEN3H=799ULL, RV_CSR_MCOUNTINHIBIT=800ULL, RV_CSR_MHPMEVENT3=803ULL, RV_CSR_MHPMEVENT4=804ULL, RV_CSR_MHPMEVENT5=805ULL, RV_CSR_MHPMEVENT6=806ULL, RV_CSR_MHPMEVENT7=807ULL, RV_CSR_MHPMEVENT8=808ULL, RV_CSR_MHPMEVENT9=809ULL, RV_CSR_MHPMEVENT10=810ULL, RV_CSR_MHPMEVENT11=811ULL, RV_CSR_MHPMEVENT12=812ULL, RV_CSR_MHPMEVENT13=813ULL, RV_CSR_MHPMEVENT14=814ULL, RV_CSR_MHPMEVENT15=815ULL, RV_CSR_MHPMEVENT16=816ULL, RV_CSR_MHPMEVENT17=817ULL, RV_CSR_MHPMEVENT18=818ULL, RV_CSR_MHPMEVENT19=819ULL, RV_CSR_MHPMEVENT20=820ULL, RV_CSR_MHPMEVENT21=821ULL, RV_CSR_MHPMEVENT22=822ULL, RV_CSR_MHPMEVENT23=823ULL, RV_CSR_MHPMEVENT24=824ULL, RV_CSR_MHPMEVENT25=825ULL, RV_CSR_MHPMEVENT26=826ULL, RV_CSR_MHPMEVENT27=827ULL, RV_CSR_MHPMEVENT28=828ULL, RV_CSR_MHPMEVENT29=829ULL, RV_CSR_MHPMEVENT30=830ULL, RV_CSR_MHPMEVENT31=831ULL, RV_CSR_MSCRATCH=832ULL, RV_CSR_MEPC=833ULL, RV_CSR_MCAUSE=834ULL, RV_CSR_MTVAL=835ULL, RV_CSR_MIP=836ULL, RV_CSR_MNXTI=837ULL, RV_CSR_MINTSTATUS=838ULL, RV_CSR_MSCRATCHCSW=840ULL, RV_CSR_MSCRATCHCSWL=841ULL, RV_CSR_MTINST=842ULL, RV_CSR_MTVAL2=843ULL, RV_CSR_PMPCFG0=928ULL, RV_CSR_PMPCFG1=929ULL, RV_CSR_PMPCFG2=930ULL, RV_CSR_PMPCFG3=931ULL, RV_CSR_PMPCFG4=932ULL, RV_CSR_PMPCFG5=933ULL, RV_CSR_PMPCFG6=934ULL, RV_CSR_PMPCFG7=935ULL, RV_CSR_PMPCFG8=936ULL, RV_CSR_PMPCFG9=937ULL, RV_CSR_PMPCFG10=938ULL, RV_CSR_PMPCFG11=939ULL, RV_CSR_PMPCFG12=940ULL, RV_CSR_PMPCFG13=941ULL, RV_CSR_PMPCFG14=942ULL, RV_CSR_PMPCFG15=943ULL, RV_CSR_PMPADDR0=944ULL, RV_CSR_PMPADDR1=945ULL, RV_CSR_PMPADDR2=946ULL, RV_CSR_PMPADDR3=947ULL, RV_CSR_PMPADDR4=948ULL, RV_CSR_PMPADDR5=949ULL, RV_CSR_PMPADDR6=950ULL, RV_CSR_PMPADDR7=951ULL, RV_CSR_PMPADDR8=952ULL, RV_CSR_PMPADDR9=953ULL, RV_CSR_PMPADDR10=954ULL, RV_CSR_PMPADDR11=955ULL, RV_CSR_PMPADDR12=956ULL, RV_CSR_PMPADDR13=957ULL, RV_CSR_PMPADDR14=958ULL, RV_CSR_PMPADDR15=959ULL, RV_CSR_PMPADDR16=960ULL, RV_CSR_PMPADDR17=961ULL, RV_CSR_PMPADDR18=962ULL, RV_CSR_PMPADDR19=963ULL, RV_CSR_PMPADDR20=964ULL, RV_CSR_PMPADDR21=965ULL, RV_CSR_PMPADDR22=966ULL, RV_CSR_PMPADDR23=967ULL, RV_CSR_PMPADDR24=968ULL, RV_CSR_PMPADDR25=969ULL, RV_CSR_PMPADDR26=970ULL, RV_CSR_PMPADDR27=971ULL, RV_CSR_PMPADDR28=972ULL, RV_CSR_PMPADDR29=973ULL, RV_CSR_PMPADDR30=974ULL, RV_CSR_PMPADDR31=975ULL, RV_CSR_PMPADDR32=976ULL, RV_CSR_PMPADDR33=977ULL, RV_CSR_PMPADDR34=978ULL, RV_CSR_PMPADDR35=979ULL, RV_CSR_PMPADDR36=980ULL, RV_CSR_PMPADDR37=981ULL, RV_CSR_PMPADDR38=982ULL, RV_CSR_PMPADDR39=983ULL, RV_CSR_PMPADDR40=984ULL, RV_CSR_PMPADDR41=985ULL, RV_CSR_PMPADDR42=986ULL, RV_CSR_PMPADDR43=987ULL, RV_CSR_PMPADDR44=988ULL, RV_CSR_PMPADDR45=989ULL, RV_CSR_PMPADDR46=990ULL, RV_CSR_PMPADDR47=991ULL, RV_CSR_PMPADDR48=992ULL, RV_CSR_PMPADDR49=993ULL, RV_CSR_PMPADDR50=994ULL, RV_CSR_PMPADDR51=995ULL, RV_CSR_PMPADDR52=996ULL, RV_CSR_PMPADDR53=997ULL, RV_CSR_PMPADDR54=998ULL, RV_CSR_PMPADDR55=999ULL, RV_CSR_PMPADDR56=1000ULL, RV_CSR_PMPADDR57=1001ULL, RV_CSR_PMPADDR58=1002ULL, RV_CSR_PMPADDR59=1003ULL, RV_CSR_PMPADDR60=1004ULL, RV_CSR_PMPADDR61=1005ULL, RV_CSR_PMPADDR62=1006ULL, RV_CSR_PMPADDR63=1007ULL, RV_CSR_SCONTEXT=1448ULL, RV_CSR_HSTATUS=1536ULL, RV_CSR_HEDELEG=1538ULL, RV_CSR_HIDELEG=1539ULL, RV_CSR_HIE=1540ULL, RV_CSR_HTIMEDELTA=1541ULL, RV_CSR_HCOUNTEREN=1542ULL, RV_CSR_HGEIE=1543ULL, RV_CSR_HENVCFG=1546ULL, RV_CSR_HSTATEEN0=1548ULL, RV_CSR_HSTATEEN1=1549ULL, RV_CSR_HSTATEEN2=1550ULL, RV_CSR_HSTATEEN3=1551ULL, RV_CSR_HTIMEDELTAH=1557ULL, RV_CSR_HENVCFGH=1562ULL, RV_CSR_HSTATEEN0H=1564ULL, RV_CSR_HSTATEEN1H=1565ULL, RV_CSR_HSTATEEN2H=1566ULL, RV_CSR_HSTATEEN3H=1567ULL, RV_CSR_HTVAL=1603ULL, RV_CSR_HIP=1604ULL, RV_CSR_HVIP=1605ULL, RV_CSR_HTINST=1610ULL, RV_CSR_HGATP=1664ULL, RV_CSR_HCONTEXT=1704ULL, RV_CSR_MHPMEVENT3H=1827ULL, RV_CSR_MHPMEVENT4H=1828ULL, RV_CSR_MHPMEVENT5H=1829ULL, RV_CSR_MHPMEVENT6H=1830ULL, RV_CSR_MHPMEVENT7H=1831ULL, RV_CSR_MHPMEVENT8H=1832ULL, RV_CSR_MHPMEVENT9H=1833ULL, RV_CSR_MHPMEVENT10H=1834ULL, RV_CSR_MHPMEVENT11H=1835ULL, RV_CSR_MHPMEVENT12H=1836ULL, RV_CSR_MHPMEVENT13H=1837ULL, RV_CSR_MHPMEVENT14H=1838ULL, RV_CSR_MHPMEVENT15H=1839ULL, RV_CSR_MHPMEVENT16H=1840ULL, RV_CSR_MHPMEVENT17H=1841ULL, RV_CSR_MHPMEVENT18H=1842ULL, RV_CSR_MHPMEVENT19H=1843ULL, RV_CSR_MHPMEVENT20H=1844ULL, RV_CSR_MHPMEVENT21H=1845ULL, RV_CSR_MHPMEVENT22H=1846ULL, RV_CSR_MHPMEVENT23H=1847ULL, RV_CSR_MHPMEVENT24H=1848ULL, RV_CSR_MHPMEVENT25H=1849ULL, RV_CSR_MHPMEVENT26H=1850ULL, RV_CSR_MHPMEVENT27H=1851ULL, RV_CSR_MHPMEVENT28H=1852ULL, RV_CSR_MHPMEVENT29H=1853ULL, RV_CSR_MHPMEVENT30H=1854ULL, RV_CSR_MHPMEVENT31H=1855ULL, RV_CSR_MSECCFG=1863ULL, RV_CSR_MSECCFGH=1879ULL, RV_CSR_TSELECT=1952ULL, RV_CSR_TDATA1=1953ULL, RV_CSR_TDATA2=1954ULL, RV_CSR_TDATA3=1955ULL, RV_CSR_TINFO=1956ULL, RV_CSR_TCONTROL=1957ULL, RV_CSR_MCONTEXT=1960ULL, RV_CSR_MSCONTEXT=1962ULL, RV_CSR_DCSR=1968ULL, RV_CSR_DPC=1969ULL, RV_CSR_DSCRATCH0=1970ULL, RV_CSR_DSCRATCH1=1971ULL, RV_CSR_MCYCLE=2816ULL, RV_CSR_MINSTRET=2818ULL, RV_CSR_MHPMCOUNTER3=2819ULL, RV_CSR_MHPMCOUNTER4=2820ULL, RV_CSR_MHPMCOUNTER5=2821ULL, RV_CSR_MHPMCOUNTER6=2822ULL, RV_CSR_MHPMCOUNTER7=2823ULL, RV_CSR_MHPMCOUNTER8=2824ULL, RV_CSR_MHPMCOUNTER9=2825ULL, RV_CSR_MHPMCOUNTER10=2826ULL, RV_CSR_MHPMCOUNTER11=2827ULL, RV_CSR_MHPMCOUNTER12=2828ULL, RV_CSR_MHPMCOUNTER13=2829ULL, RV_CSR_MHPMCOUNTER14=2830ULL, RV_CSR_MHPMCOUNTER15=2831ULL, RV_CSR_MHPMCOUNTER16=2832ULL, RV_CSR_MHPMCOUNTER17=2833ULL, RV_CSR_MHPMCOUNTER18=2834ULL, RV_CSR_MHPMCOUNTER19=2835ULL, RV_CSR_MHPMCOUNTER20=2836ULL, RV_CSR_MHPMCOUNTER21=2837ULL, RV_CSR_MHPMCOUNTER22=2838ULL, RV_CSR_MHPMCOUNTER23=2839ULL, RV_CSR_MHPMCOUNTER24=2840ULL, RV_CSR_MHPMCOUNTER25=2841ULL, RV_CSR_MHPMCOUNTER26=2842ULL, RV_CSR_MHPMCOUNTER27=2843ULL, RV_CSR_MHPMCOUNTER28=2844ULL, RV_CSR_MHPMCOUNTER29=2845ULL, RV_CSR_MHPMCOUNTER30=2846ULL, RV_CSR_MHPMCOUNTER31=2847ULL, RV_CSR_MCYCLEH=2944ULL, RV_CSR_MINSTRETH=2946ULL, RV_CSR_MHPMCOUNTER3H=2947ULL, RV_CSR_MHPMCOUNTER4H=2948ULL, RV_CSR_MHPMCOUNTER5H=2949ULL, RV_CSR_MHPMCOUNTER6H=2950ULL, RV_CSR_MHPMCOUNTER7H=2951ULL, RV_CSR_MHPMCOUNTER8H=2952ULL, RV_CSR_MHPMCOUNTER9H=2953ULL, RV_CSR_MHPMCOUNTER10H=2954ULL, RV_CSR_MHPMCOUNTER11H=2955ULL, RV_CSR_MHPMCOUNTER12H=2956ULL, RV_CSR_MHPMCOUNTER13H=2957ULL, RV_CSR_MHPMCOUNTER14H=2958ULL, RV_CSR_MHPMCOUNTER15H=2959ULL, RV_CSR_MHPMCOUNTER16H=2960ULL, RV_CSR_MHPMCOUNTER17H=2961ULL, RV_CSR_MHPMCOUNTER18H=2962ULL, RV_CSR_MHPMCOUNTER19H=2963ULL, RV_CSR_MHPMCOUNTER20H=2964ULL, RV_CSR_MHPMCOUNTER21H=2965ULL, RV_CSR_MHPMCOUNTER22H=2966ULL, RV_CSR_MHPMCOUNTER23H=2967ULL, RV_CSR_MHPMCOUNTER24H=2968ULL, RV_CSR_MHPMCOUNTER25H=2969ULL, RV_CSR_MHPMCOUNTER26H=2970ULL, RV_CSR_MHPMCOUNTER27H=2971ULL, RV_CSR_MHPMCOUNTER28H=2972ULL, RV_CSR_MHPMCOUNTER29H=2973ULL, RV_CSR_MHPMCOUNTER30H=2974ULL, RV_CSR_MHPMCOUNTER31H=2975ULL, RV_CSR_CYCLE=3072ULL, RV_CSR_TIME=3073ULL, RV_CSR_INSTRET=3074ULL, RV_CSR_HPMCOUNTER3=3075ULL, RV_CSR_HPMCOUNTER4=3076ULL, RV_CSR_HPMCOUNTER5=3077ULL, RV_CSR_HPMCOUNTER6=3078ULL, RV_CSR_HPMCOUNTER7=3079ULL, RV_CSR_HPMCOUNTER8=3080ULL, RV_CSR_HPMCOUNTER9=3081ULL, RV_CSR_HPMCOUNTER10=3082ULL, RV_CSR_HPMCOUNTER11=3083ULL, RV_CSR_HPMCOUNTER12=3084ULL, RV_CSR_HPMCOUNTER13=3085ULL, RV_CSR_HPMCOUNTER14=3086ULL, RV_CSR_HPMCOUNTER15=3087ULL, RV_CSR_HPMCOUNTER16=3088ULL, RV_CSR_HPMCOUNTER17=3089ULL, RV_CSR_HPMCOUNTER18=3090ULL, RV_CSR_HPMCOUNTER19=3091ULL, RV_CSR_HPMCOUNTER20=3092ULL, RV_CSR_HPMCOUNTER21=3093ULL, RV_CSR_HPMCOUNTER22=3094ULL, RV_CSR_HPMCOUNTER23=3095ULL, RV_CSR_HPMCOUNTER24=3096ULL, RV_CSR_HPMCOUNTER25=3097ULL, RV_CSR_HPMCOUNTER26=3098ULL, RV_CSR_HPMCOUNTER27=3099ULL, RV_CSR_HPMCOUNTER28=3100ULL, RV_CSR_HPMCOUNTER29=3101ULL, RV_CSR_HPMCOUNTER30=3102ULL, RV_CSR_HPMCOUNTER31=3103ULL, RV_CSR_VL=3104ULL, RV_CSR_VTYPE=3105ULL, RV_CSR_VLENB=3106ULL, RV_CSR_CYCLEH=3200ULL, RV_CSR_TIMEH=3201ULL, RV_CSR_INSTRETH=3202ULL, RV_CSR_HPMCOUNTER3H=3203ULL, RV_CSR_HPMCOUNTER4H=3204ULL, RV_CSR_HPMCOUNTER5H=3205ULL, RV_CSR_HPMCOUNTER6H=3206ULL, RV_CSR_HPMCOUNTER7H=3207ULL, RV_CSR_HPMCOUNTER8H=3208ULL, RV_CSR_HPMCOUNTER9H=3209ULL, RV_CSR_HPMCOUNTER10H=3210ULL, RV_CSR_HPMCOUNTER11H=3211ULL, RV_CSR_HPMCOUNTER12H=3212ULL, RV_CSR_HPMCOUNTER13H=3213ULL, RV_CSR_HPMCOUNTER14H=3214ULL, RV_CSR_HPMCOUNTER15H=3215ULL, RV_CSR_HPMCOUNTER16H=3216ULL, RV_CSR_HPMCOUNTER17H=3217ULL, RV_CSR_HPMCOUNTER18H=3218ULL, RV_CSR_HPMCOUNTER19H=3219ULL, RV_CSR_HPMCOUNTER20H=3220ULL, RV_CSR_HPMCOUNTER21H=3221ULL, RV_CSR_HPMCOUNTER22H=3222ULL, RV_CSR_HPMCOUNTER23H=3223ULL, RV_CSR_HPMCOUNTER24H=3224ULL, RV_CSR_HPMCOUNTER25H=3225ULL, RV_CSR_HPMCOUNTER26H=3226ULL, RV_CSR_HPMCOUNTER27H=3227ULL, RV_CSR_HPMCOUNTER28H=3228ULL, RV_CSR_HPMCOUNTER29H=3229ULL, RV_CSR_HPMCOUNTER30H=3230ULL, RV_CSR_HPMCOUNTER31H=3231ULL, RV_CSR_SCOUNTOVF=3488ULL, RV_CSR_HGEIP=3602ULL, RV_CSR_MVENDORID=3857ULL, RV_CSR_MARCHID=3858ULL, RV_CSR_MIMPID=3859ULL, RV_CSR_MHARTID=3860ULL, RV_CSR_MCONFIGPTR=3861ULL, RV_CAUSE_MISALIGNED_FETCH=0ULL, RV_CAUSE_FETCH_ACCESS=1ULL, RV_CAUSE_ILLEGAL_INSTRUCTION=2ULL, RV_CAUSE_BREAKPOINT=3ULL, RV_CAUSE_MISALIGNED_LOAD=4ULL, RV_CAUSE_LOAD_ACCESS=5ULL, RV_CAUSE_MISALIGNED_STORE=6ULL, RV_CAUSE_STORE_ACCESS=7ULL, RV_CAUSE_USER_ECALL=8ULL, RV_CAUSE_SUPERVISOR_ECALL=9ULL, RV_CAUSE_VIRTUAL_SUPERVISOR_ECALL=10ULL, RV_CAUSE_MACHINE_ECALL=11ULL, RV_CAUSE_FETCH_PAGE_FAULT=12ULL, RV_CAUSE_LOAD_PAGE_FAULT=13ULL, RV_CAUSE_STORE_PAGE_FAULT=15ULL, RV_CAUSE_FETCH_GUEST_PAGE_FAULT=20ULL, RV_CAUSE_LOAD_GUEST_PAGE_FAULT=21ULL, RV_CAUSE_VIRTUAL_INSTRUCTION=22ULL, RV_CAUSE_STORE_GUEST_PAGE_FAULT=23ULL, RV_MSTATUS_UIE=1ULL, RV_MSTATUS_SIE=2ULL, RV_MSTATUS_HIE=4ULL, RV_MSTATUS_MIE=8ULL, RV_MSTATUS_UPIE=16ULL, RV_MSTATUS_SPIE=32ULL, RV_MSTATUS_UBE=64ULL, RV_MSTATUS_MPIE=128ULL, RV_MSTATUS_SPP=256ULL, RV_MSTATUS_VS=1536ULL, RV_MSTATUS_MPP=6144ULL, RV_MSTATUS_FS=24576ULL, RV_MSTATUS_XS=98304ULL, RV_MSTATUS_MPRV=131072ULL, RV_MSTATUS_SUM=262144ULL, RV_MSTATUS_MXR=524288ULL, RV_MSTATUS_TVM=1048576ULL, RV_MSTATUS_TW=2097152ULL, RV_MSTATUS_TSR=4194304ULL, RV_MSTATUS32_SD=1ULL, RV_PRV_U=0ULL, RV_PRV_S=1ULL, RV_PRV_H=2ULL, RV_PRV_M=3ULL, RV_IRQ_U_SOFT=0ULL, RV_IRQ_S_SOFT=1ULL, RV_IRQ_VS_SOFT=2ULL, RV_IRQ_M_SOFT=3ULL, RV_IRQ_U_TIMER=4ULL, RV_IRQ_S_TIMER=5ULL, RV_IRQ_VS_TIMER=6ULL, RV_IRQ_M_TIMER=7ULL, RV_IRQ_U_EXT=8ULL, RV_IRQ_S_EXT=9ULL, RV_IRQ_VS_EXT=10ULL, RV_IRQ_M_EXT=11ULL, RV_IRQ_S_GEXT=12ULL, RV_IRQ_COP=12ULL, RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=1ULL, RV_MIP_VSSIP=1ULL, RV_MIP_MSIP=1ULL, RV_MIP_UTIP=1ULL, RV_MIP_STIP=1ULL, RV_MIP_VSTIP=1ULL, RV_MIP_MTIP=1ULL, RV_MIP_UEIP=1ULL, RV_MIP_SEIP=1ULL, RV_MIP_VSEIP=1ULL, RV_MIP_MEIP=1ULL, RV_MIP_SGEIP=1ULL, RV_MIP_LCOFIP=1ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL}; constexpr static unsigned FP_REGS_SIZE = 0; diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp index c6acf66..e30c907 100644 --- a/src/vm/asmjit/vm_tgc5c.cpp +++ b/src/vm/asmjit/vm_tgc5c.cpp @@ -344,7 +344,7 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - (uint32_t)((int32_t)imm)); + (uint32_t)((int32_t)imm)); } } auto returnValue = CONT; @@ -390,7 +390,7 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - (uint32_t)(PC+(int32_t)imm)); + (uint32_t)(PC+(int32_t)imm)); } } auto returnValue = CONT; @@ -440,7 +440,7 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - (uint32_t)(PC+4)); + (uint32_t)(PC+4)); } auto PC_val_v = (uint32_t)(PC+(int32_t)sext<21>(imm)); cc.mov(jh.next_pc, PC_val_v); @@ -507,7 +507,7 @@ private: { if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - (uint32_t)(PC+4)); + (uint32_t)(PC+4)); } auto PC_val_v = new_pc; cc.mov(jh.next_pc, PC_val_v); @@ -916,8 +916,8 @@ private: gen_read_mem(jh, traits::MEM, load_address, 1), 8, false); if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - res, 32, true)); + gen_ext(jh, + res, 32, true)); } } auto returnValue = CONT; @@ -969,8 +969,8 @@ private: gen_read_mem(jh, traits::MEM, load_address, 2), 16, false); if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - res, 32, true)); + gen_ext(jh, + res, 32, true)); } } auto returnValue = CONT; @@ -1022,8 +1022,8 @@ private: gen_read_mem(jh, traits::MEM, load_address, 4), 32, false); if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - res, 32, true)); + gen_ext(jh, + res, 32, true)); } } auto returnValue = CONT; @@ -1074,8 +1074,8 @@ private: auto res = gen_read_mem(jh, traits::MEM, load_address, 1); if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - res, 32, false)); + gen_ext(jh, + res, 32, false)); } } auto returnValue = CONT; @@ -1126,8 +1126,8 @@ private: auto res = gen_read_mem(jh, traits::MEM, load_address, 2); if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - res, 32, false)); + gen_ext(jh, + res, 32, false)); } } auto returnValue = CONT; @@ -1318,9 +1318,9 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) - ), 32, true)); + gen_ext(jh, + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) + ), 32, true)); } } auto returnValue = CONT; @@ -1379,8 +1379,8 @@ private: cc.mov(tmp_reg,1); cc.bind(label_merge); cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, tmp_reg - , 32, false) + gen_ext(jh, tmp_reg + , 32, false) ); } } @@ -1440,8 +1440,8 @@ private: cc.mov(tmp_reg,1); cc.bind(label_merge); cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, tmp_reg - , 32, false) + gen_ext(jh, tmp_reg + , 32, false) ); } } @@ -1490,8 +1490,8 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) - ); + gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) + ); } } auto returnValue = CONT; @@ -1538,8 +1538,8 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) - ); + gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) + ); } } auto returnValue = CONT; @@ -1586,8 +1586,8 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) - ); + gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) + ); } } auto returnValue = CONT; @@ -1634,8 +1634,8 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), shamt) - ); + gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), shamt) + ); } } auto returnValue = CONT; @@ -1682,8 +1682,8 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1), shamt) - ); + gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1), shamt) + ); } } auto returnValue = CONT; @@ -1730,10 +1730,10 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - (gen_operation(jh, sar, gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1), 32, true), shamt) - ), 32, false)); + gen_ext(jh, + (gen_operation(jh, sar, gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1), 32, true), shamt) + ), 32, false)); } } auto returnValue = CONT; @@ -1780,9 +1780,9 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) - ), 32, false)); + gen_ext(jh, + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + ), 32, false)); } } auto returnValue = CONT; @@ -1829,9 +1829,9 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - (gen_operation(jh, sub, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) - ), 32, true)); + gen_ext(jh, + (gen_operation(jh, sub, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + ), 32, true)); } } auto returnValue = CONT; @@ -1878,9 +1878,9 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1)) - )) - , 32, false)); + gen_ext(jh, gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1)) + )) + , 32, false)); } } auto returnValue = CONT; @@ -1940,8 +1940,8 @@ private: cc.mov(tmp_reg,1); cc.bind(label_merge); cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, tmp_reg - , 32, false) + gen_ext(jh, tmp_reg + , 32, false) ); } } @@ -2001,8 +2001,8 @@ private: cc.mov(tmp_reg,1); cc.bind(label_merge); cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, tmp_reg - , 32, false) + gen_ext(jh, tmp_reg + , 32, false) ); } } @@ -2051,8 +2051,8 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) - ); + gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + ); } } auto returnValue = CONT; @@ -2099,9 +2099,9 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1)) - )) - , 32, false)); + gen_ext(jh, gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1)) + )) + , 32, false)); } } auto returnValue = CONT; @@ -2148,11 +2148,11 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - (gen_ext(jh, gen_operation(jh, sar, gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1), 32, true), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1)) - )) - , 32, true)), 32, true)); + gen_ext(jh, + (gen_ext(jh, gen_operation(jh, sar, gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1), 32, true), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1)) + )) + , 32, true)), 32, true)); } } auto returnValue = CONT; @@ -2199,8 +2199,8 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) - ); + gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + ); } } auto returnValue = CONT; @@ -2247,8 +2247,8 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) - ); + gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + ); } } auto returnValue = CONT; @@ -2479,7 +2479,7 @@ private: auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); gen_write_mem(jh, traits::CSR, csr, xrs1, 4); cc.mov(get_ptr_for(jh, traits::X0+ rd), - xrd); + xrd); } else{ gen_write_mem(jh, traits::CSR, csr, xrs1, 4); @@ -2535,7 +2535,7 @@ private: } if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - xrd); + xrd); } } auto returnValue = CONT; @@ -2588,7 +2588,7 @@ private: } if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - xrd); + xrd); } } auto returnValue = CONT; @@ -2637,7 +2637,7 @@ private: gen_write_mem(jh, traits::CSR, csr, (uint32_t)zimm, 4); if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - xrd); + xrd); } } auto returnValue = CONT; @@ -2689,7 +2689,7 @@ private: } if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - xrd); + xrd); } } auto returnValue = CONT; @@ -2741,7 +2741,7 @@ private: } if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - xrd); + xrd); } } auto returnValue = CONT; @@ -2825,14 +2825,14 @@ private: gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); } else{ - auto res = gen_operation(jh, imul, gen_ext(jh, + auto res = gen_operation(jh, smul, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, true)) ; if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - res, 32, true)); + gen_ext(jh, + res, 32, true)); } } auto returnValue = CONT; @@ -2877,15 +2877,15 @@ private: gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); } else{ - auto res = gen_operation(jh, imul, gen_ext(jh, + auto res = gen_operation(jh, smul, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, true)) ; if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - (gen_operation(jh, sar, res, static_cast(traits::XLEN)) - ), 32, true)); + gen_ext(jh, + (gen_operation(jh, sar, res, static_cast(traits::XLEN)) + ), 32, true)); } } auto returnValue = CONT; @@ -2930,14 +2930,14 @@ private: gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); } else{ - auto res = gen_operation(jh, imul, gen_ext(jh, + auto res = gen_operation(jh, sumul, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true), load_reg_from_mem(jh, traits::X0 + rs2)) ; if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - (gen_operation(jh, sar, res, static_cast(traits::XLEN)) - ), 32, true)); + gen_ext(jh, + (gen_operation(jh, sar, res, static_cast(traits::XLEN)) + ), 32, true)); } } auto returnValue = CONT; @@ -2982,14 +2982,13 @@ private: gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); } else{ - auto res = gen_operation(jh, mul, - load_reg_from_mem(jh, traits::X0 + rs1), - load_reg_from_mem(jh, traits::X0 + rs2)); + auto res = gen_operation(jh, umul, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + ; if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - (gen_operation(jh, shr, res, static_cast(traits::XLEN)) - ), 32, false)); + gen_ext(jh, + (gen_operation(jh, shr, res, static_cast(traits::XLEN)) + ), 32, false)); } } auto returnValue = CONT; @@ -3055,15 +3054,15 @@ private: cc.je(label_else); { cc.mov(get_ptr_for(jh, traits::X0+ rd), - MMIN); + MMIN); } cc.jmp(label_merge); cc.bind(label_else); { cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - (gen_operation(jh, idiv, dividend, divisor) - ), 32, true)); + gen_ext(jh, + (gen_operation(jh, sdiv, dividend, divisor) + ), 32, true)); } cc.bind(label_merge); } @@ -3071,7 +3070,7 @@ private: cc.bind(label_else); { cc.mov(get_ptr_for(jh, traits::X0+ rd), - (uint32_t)- 1); + (uint32_t)- 1); } cc.bind(label_merge); } @@ -3126,8 +3125,8 @@ private: { if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, div, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) - ); + gen_operation(jh, udiv, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + ); } } cc.jmp(label_merge); @@ -3135,7 +3134,7 @@ private: { if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - (uint32_t)- 1); + (uint32_t)- 1); } } cc.bind(label_merge); @@ -3200,7 +3199,7 @@ private: { if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, 0, 32, false) + gen_ext(jh, 0, 32, false) ); } } @@ -3209,11 +3208,11 @@ private: { if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - (gen_operation(jh, srem, gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs2), 32, true)) - ), 32, false)); + gen_ext(jh, + (gen_operation(jh, srem, gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs2), 32, true)) + ), 32, false)); } } cc.bind(label_merge); @@ -3223,7 +3222,7 @@ private: { if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - load_reg_from_mem(jh, traits::X0 + rs1)); + load_reg_from_mem(jh, traits::X0 + rs1)); } } cc.bind(label_merge); @@ -3278,8 +3277,8 @@ private: { if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, urem, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) - ); + gen_operation(jh, urem, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + ); } } cc.jmp(label_merge); @@ -3287,7 +3286,7 @@ private: { if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - load_reg_from_mem(jh, traits::X0 + rs1)); + load_reg_from_mem(jh, traits::X0 + rs1)); } } cc.bind(label_merge); @@ -3331,9 +3330,9 @@ private: /*generate behavior*/ if(imm){ cc.mov(get_ptr_for(jh, traits::X0+ rd+8), - gen_ext(jh, - (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + 2), imm) - ), 32, false)); + gen_ext(jh, + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + 2), imm) + ), 32, false)); } else{ gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); @@ -3380,9 +3379,9 @@ private: (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1+8), uimm) ), 32, false); cc.mov(get_ptr_for(jh, traits::X0+ rd+8), - gen_ext(jh, - gen_ext(jh, - gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 32, true)); + gen_ext(jh, + gen_ext(jh, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 32, true)); auto returnValue = CONT; gen_instr_epilogue(jh); @@ -3469,9 +3468,9 @@ private: else{ if(rs1!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rs1), - gen_ext(jh, - (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int8_t)sext<6>(imm)) - ), 32, true)); + gen_ext(jh, + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int8_t)sext<6>(imm)) + ), 32, true)); } } auto returnValue = CONT; @@ -3546,7 +3545,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ 1), - (uint32_t)(PC+2)); + (uint32_t)(PC+2)); auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm)); cc.mov(jh.next_pc, PC_val_v); cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); @@ -3593,7 +3592,7 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - (uint32_t)((int8_t)sext<6>(imm))); + (uint32_t)((int8_t)sext<6>(imm))); } } auto returnValue = CONT; @@ -3638,7 +3637,7 @@ private: } if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - (uint32_t)((int32_t)sext<18>(imm))); + (uint32_t)((int32_t)sext<18>(imm))); } auto returnValue = CONT; @@ -3678,9 +3677,9 @@ private: /*generate behavior*/ if(nzimm){ cc.mov(get_ptr_for(jh, traits::X0+ 2), - gen_ext(jh, - (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + 2), (int16_t)sext<10>(nzimm)) - ), 32, true)); + gen_ext(jh, + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + 2), (int16_t)sext<10>(nzimm)) + ), 32, true)); } else{ gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); @@ -3759,8 +3758,8 @@ private: cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ rs1+8), - gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1+8), shamt) - ); + gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1+8), shamt) + ); auto returnValue = CONT; gen_instr_epilogue(jh); @@ -3800,18 +3799,18 @@ private: /*generate behavior*/ if(shamt){ cc.mov(get_ptr_for(jh, traits::X0+ rs1+8), - gen_ext(jh, - (gen_operation(jh, sar, (gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1+8), 32, false)), shamt) - ), 32, true)); + gen_ext(jh, + (gen_operation(jh, sar, (gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1+8), 32, false)), shamt) + ), 32, true)); } else{ if(static_cast(traits::XLEN)==128){ cc.mov(get_ptr_for(jh, traits::X0+ rs1+8), - gen_ext(jh, - (gen_operation(jh, sar, (gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1+8), 32, false)), 64) - ), 32, true)); + gen_ext(jh, + (gen_operation(jh, sar, (gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1+8), 32, false)), 64) + ), 32, true)); } } auto returnValue = CONT; @@ -3852,9 +3851,9 @@ private: cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ rs1+8), - gen_ext(jh, - (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1+8), (int8_t)sext<6>(imm)) - ), 32, true)); + gen_ext(jh, + (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1+8), (int8_t)sext<6>(imm)) + ), 32, true)); auto returnValue = CONT; gen_instr_epilogue(jh); @@ -3893,9 +3892,9 @@ private: cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ rd+8), - gen_ext(jh, - (gen_operation(jh, sub, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8)) - ), 32, true)); + gen_ext(jh, + (gen_operation(jh, sub, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8)) + ), 32, true)); auto returnValue = CONT; gen_instr_epilogue(jh); @@ -3934,8 +3933,8 @@ private: cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ rd+8), - gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8)) - ); + gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8)) + ); auto returnValue = CONT; gen_instr_epilogue(jh); @@ -3974,8 +3973,8 @@ private: cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ rd+8), - gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8)) - ); + gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8)) + ); auto returnValue = CONT; gen_instr_epilogue(jh); @@ -4014,8 +4013,8 @@ private: cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ rd+8), - gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8)) - ); + gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8)) + ); auto returnValue = CONT; gen_instr_epilogue(jh); @@ -4192,8 +4191,8 @@ private: else{ if(rs1!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rs1), - gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), nzuimm) - ); + gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), nzuimm) + ); } } auto returnValue = CONT; @@ -4241,9 +4240,9 @@ private: (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + 2), uimm) ), 32, false); cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - gen_ext(jh, - gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 32, true)); + gen_ext(jh, + gen_ext(jh, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 32, true)); } auto returnValue = CONT; @@ -4288,7 +4287,7 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - load_reg_from_mem(jh, traits::X0 + rs2)); + load_reg_from_mem(jh, traits::X0 + rs2)); } } auto returnValue = CONT; @@ -4414,9 +4413,9 @@ private: else{ if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, - (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rd), load_reg_from_mem(jh, traits::X0 + rs2)) - ), 32, false)); + gen_ext(jh, + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rd), load_reg_from_mem(jh, traits::X0 + rs2)) + ), 32, false)); } } auto returnValue = CONT; @@ -4461,7 +4460,7 @@ private: else{ auto new_pc = load_reg_from_mem(jh, traits::X0 + rs1); cc.mov(get_ptr_for(jh, traits::X0+ 1), - (uint32_t)(PC+2)); + (uint32_t)(PC+2)); auto PC_val_v = gen_operation(jh, band, new_pc, ~ 1) ; cc.mov(jh.next_pc, PC_val_v); diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp index a8d1e8f..70b1195 100644 --- a/src/vm/interp/vm_tgc5c.cpp +++ b/src/vm/interp/vm_tgc5c.cpp @@ -732,9 +732,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); - int8_t res_27 = super::template read_mem(traits::MEM, load_address); + int8_t res_40 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int8_t res = (int8_t)res_27; + int8_t res = (int8_t)res_40; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -763,9 +763,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); - int16_t res_28 = super::template read_mem(traits::MEM, load_address); + int16_t res_41 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int16_t res = (int16_t)res_28; + int16_t res = (int16_t)res_41; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -794,9 +794,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); - int32_t res_29 = super::template read_mem(traits::MEM, load_address); + int32_t res_42 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int32_t res = (int32_t)res_29; + int32_t res = (int32_t)res_42; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -825,9 +825,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); - uint8_t res_30 = super::template read_mem(traits::MEM, load_address); + uint8_t res_43 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint8_t res = res_30; + uint8_t res = res_43; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -856,9 +856,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); - uint16_t res_31 = super::template read_mem(traits::MEM, load_address); + uint16_t res_44 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint16_t res = res_31; + uint16_t res = res_44; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -1556,9 +1556,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { uint32_t xrs1 = *(X+rs1); if(rd != 0) { - uint32_t res_32 = super::template read_mem(traits::CSR, csr); + uint32_t res_45 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_32; + uint32_t xrd = res_45; super::template write_mem(traits::CSR, csr, xrs1); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); *(X+rd) = xrd; @@ -1591,9 +1591,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint32_t res_33 = super::template read_mem(traits::CSR, csr); + uint32_t res_46 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_33; + uint32_t xrd = res_46; uint32_t xrs1 = *(X+rs1); if(rs1 != 0) { super::template write_mem(traits::CSR, csr, xrd | xrs1); @@ -1626,9 +1626,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint32_t res_34 = super::template read_mem(traits::CSR, csr); + uint32_t res_47 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_34; + uint32_t xrd = res_47; uint32_t xrs1 = *(X+rs1); if(rs1 != 0) { super::template write_mem(traits::CSR, csr, xrd & ~ xrs1); @@ -1661,9 +1661,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint32_t res_35 = super::template read_mem(traits::CSR, csr); + uint32_t res_48 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_35; + uint32_t xrd = res_48; super::template write_mem(traits::CSR, csr, (uint32_t)zimm); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); if(rd != 0) { @@ -1693,9 +1693,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint32_t res_36 = super::template read_mem(traits::CSR, csr); + uint32_t res_49 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_36; + uint32_t xrd = res_49; if(zimm != 0) { super::template write_mem(traits::CSR, csr, xrd | (uint32_t)zimm); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); @@ -1727,9 +1727,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint32_t res_37 = super::template read_mem(traits::CSR, csr); + uint32_t res_50 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_37; + uint32_t xrd = res_50; if(zimm != 0) { super::template write_mem(traits::CSR, csr, xrd & ~ ((uint32_t)zimm)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); @@ -2064,9 +2064,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm )); - int32_t res_38 = super::template read_mem(traits::MEM, offs); + int32_t res_51 = super::template read_mem(traits::MEM, offs); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - *(X+rd + 8) = (uint32_t)(int32_t)res_38; + *(X+rd + 8) = (uint32_t)(int32_t)res_51; } break; }// @suppress("No break at end of case") @@ -2486,9 +2486,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm )); - int32_t res_39 = super::template read_mem(traits::MEM, offs); + int32_t res_52 = super::template read_mem(traits::MEM, offs); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - *(X+rd) = (uint32_t)(int32_t)res_39; + *(X+rd) = (uint32_t)(int32_t)res_52; } } break;