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updates templates and adds newly generated files

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Eyck-Alexander Jentzsch
2025-02-03 12:32:36 +01:00
parent 28af695592
commit 4cef0f57c1
5 changed files with 335 additions and 162 deletions
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43
gen_input/templates/interp/CORENAME.cpp.gtl
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@@ -42,6 +42,7 @@ def nativeTypeSize(int size){
#include <iss/iss.h>
#include <iss/interp/vm_base.h>
#include <vm/fp_functions.h>
#include <vm/vector_functions.h>
#include <vm/aes_sbox.h>
#include <util/logging.h>
#include <boost/coroutine2/all.hpp>
@@ -106,6 +107,33 @@ protected:
def fcsr = registers.find {it.name=='FCSR'}
if(fcsr != null) {%>
inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
<%}
def vector = registers.find {it.name=='vtype'}
if(vector != null) {%>
inline const char *vname(size_t index){return index < 32?name(index+traits::V0):"illegal";}
inline const char *sew_name(size_t bits){
switch(bits){
case 0b000: return "e8";
case 0b001: return "e16";
case 0b010: return "e32";
case 0b011: return "e64";
default: return "illegal";
}
}
inline const char *lmul_name(size_t bits){
switch(bits){
case 0b101: return "mf8";
case 0b110: return "mf4";
case 0b111: return "mf2";
case 0b000: return "";
case 0b001: return "m2";
case 0b010: return "m4";
case 0b011: return "m8";
default: return "illegal";
}
}
inline const char *ma_name(bool ma){return ma ? "ma":"mu";}
inline const char *ta_name(bool ta){return ta ? "ta":"tu";}
<%}%>
virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
@@ -128,7 +156,16 @@ if(fcsr != null) {%>
inline void set_tval(uint64_t new_tval){
tval = new_tval;
}
<%if(vector != null) {%>
uint64_t vlseg(uint8_t* V, uint8_t vd, uint64_t rs1_val, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t elem_byte_size,
int8_t EMUL_pow, uint8_t segment_size){
return softvector::vector_load_store_segment(this->get_arch(), softvector::softvec_read, V, vd, rs1_val, vl, vstart, vtype, vm, elem_byte_size, EMUL_pow, segment_size);
}
uint64_t vsseg(uint8_t* V, uint8_t vd, uint64_t rs1_val, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t elem_byte_size,
int8_t EMUL_pow, uint8_t segment_size){
return softvector::vector_load_store_segment(this->get_arch(), softvector::softvec_write, V, vd, rs1_val, vl, vstart, vtype, vm, elem_byte_size, EMUL_pow, segment_size);
}
<%}%>
uint64_t fetch_count{0};
uint64_t tval{0};
@@ -272,8 +309,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// used registers<%instr.usedVariables.each{ k,v->
if(v.isArray) {%>
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %>
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
<%}}%>// calculate next pc value
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);<%}}%>
// calculate next pc value
*NEXT_PC = *PC + ${instr.length/8};
// execute instruction<%instr.behavior.eachLine{%>
${it}<%}%>